4.8. ETH¶
4.8.1. About This Document¶
Document Title |
User Guide of MCAL ETH Driver |
Document Version |
Version 1.2 |
Company |
Texas Instruments |
Document Name |
ETH User Guide |
4.8.2. Document Revision History¶
Version |
Date |
Revision History |
Status |
|---|---|---|---|
Version 1.0 |
05 Aug 2022 |
Initial Version |
Approved |
Version 1.1 |
04 Aug 2023 |
Updated as per HTML format. |
Approved |
Version 1.2 |
09 Sept 2023 |
Updated configuration parameters |
Approved |
4.8.3. Table of contents¶
4.8.4. Acronyms and Definitions¶
Acronyms and Definitions used are presented in below table.
Acronyms |
Descriptions |
|---|---|
EC |
Ethernet controller |
Eth |
Ethernet Controller Driver (AUTOSAR BSW module) |
EthIf |
Ethernet Interface (AUTOSAR BSW module) |
EthTrcv |
Ethernet Transceiver Driver (AUTOSAR BSW module) |
ISR |
Interrupt Service Routine |
MCG |
Module Configuration Generator |
MII |
Media Independent Interface (standardized Interface provided by Ethernet controllers to access Ethernet transceivers) |
TCP |
Transmission Control Protocol |
UDP |
User Datagram Protocol |
4.8.5. Functional Overview¶
4.8.5.1. Brief Overview¶
This document describes the functionality, API, and configuration of the AUTOSAR BSW module Ethernet. The Ethernet driver is a hardware abstraction layer with a standardized interface to the Ethernet Interface layer.
Supported AUTOSAR Release |
4.3.1 |
Supported Configuration Variants |
Pre-Compile time, Link-time, post-build time |
Vendor ID |
ETH_VENDOR_ID (44) |
Module ID |
ETH_MODULE_ID (88) |
Supported Platform |
AM273x |
The Ethernet module initializes and controls the Ethernet CPSW subsystem. It provides services to configure all transmit / receive resources of Ethernet controller to enable transfer of Ethernet frames. It supports polling and the interrupt modes. It provides configurations for.
Initialization of Ethernet controller.
Configure receive/transmit and error interrupts.
Enable 10/100 Mbps transfer.
Configuration of PHYs through MDIO functions.
4.8.5.1.1. ETHERNET Driver Architecture¶
The following figure shows where the ETHERNET is located in the AUTOSAR architecture.
Figure 1: Ethernet in AUTOSAR architecture
Below figure shows Ethernet driver in Ethernet stack module.
Figure 2: Ethernet stack module overview
4.8.5.1.2. Initialization¶
Eth_Init() has to be called to initialize the Ethernet driver.
4.8.5.1.3. States and Modes¶
The states and modes of the Ethernet driver define whether the Ethernet driver is operational or not. There are two states in which the Ethernet hardware/driver can be in.
ETH_STATE_UNINIT: This is the state when the Driver is not yet configured.
ETH_STATE_INIT: This is the state when the Driver is configured and initialization was successful.
There are 2 modes in which the Ethernet driver can be in.
ETH_MODE_DOWN: This is the mode when the driver/controller is disabled.
ETH_MODE_ACTIVE: This is the mode when the driver/controller is enabled.
The states and modes coexist. Whenever the ETH_STATE_ACTIVE is reached by the driver then the mode of the driver also changes to ETH_MODE_ACTIVE. The modes of the driver can be changed by the API Eth_SetControllerMode.
4.8.5.1.4. Frame Transmission¶
Ethernet driver for frame transmission uses multiple receive/transmit related APIs. As mentioned in the MCAL Ethernet spec a proper sequence should be followed to initiate receive/transmit operations. Buffer management is part of Ethernet driver. User application gives predefined number of receive and transmit buffers to driver during initialization. These are used by driver during its lifetime. Transmit buffers are immediately freed but in case of receive buffers as there are no way to identify if buffer is used by application and if it can be freed, driver just waits for buffer underflow to occur and reuses oldest buffer. Application has to make sure to use buffer before it is reused by driver. For transmit purpose application needs to get buffer from driver beforehand.
4.8.5.1.5. MDIO interface support¶
Ethernet controller driver supports MDIO functions to access Ethernet transceivers (also called PHYs) to enable them and put it into desired mode. Function Eth_ReadMII and Eth_WriteMII are used for this purpose. As per AutoSar Both APIs are asynchronous and use MDIO_USERINT interrupt for command completion. Implementation supports Synchronous MDIO read/write operation as well by disabling EthUsrMdioInterruptEnable configuration parameter. Ethernet transceiver who calls these APIs would wait for command completion from these APIs. For proper functioning of ETH TRCV driver these are necessary APIs and should be enabled through configuration option ETH_ENABLE_MII_API.
4.8.5.1.6. Statistics¶
The Ethernet driver supports statistics information which is controller recorded events associated with frame traffic on selected ports. Ethernet controller records list of values according to IETF RFC 2819. API Eth_GetCounterValues, Eth_GetRxStats, Eth_GetTxStats and Eth_GetTxErrorCounterValues map information stored by controller to information requested as per standard. Statistics recording is enabled by default by driver and statistics interrupt is used when statistic overflow occurs. ETH_GET_DROPCOUNT_API, ETH_GETETHERSTATS_API, ETH_GETTX_STATS_API & ETH_GETTXERROR_COUNTERVALUES_API configuration should be enabled to use these APIs.
4.8.5.1.7. MAC address-Based Filtering¶
For Ethernet traffic control MAC address-based filtering is supported. The Ethernet controller on AM27x device have internal filter for filtering MAC frames which does not follow rules. Below are APIs used for using MAC based filtering:
Eth_UpdatePhysAddrFilter – change MAC address of port.
Eth_GetPhysAddr – get current MAC address.
Eth_SetPhysAddr – set MAC address toport.
Different configurations are possible for filtering Ethernet frames.
4.8.5.2. Features Supported and Not Supported¶
ETH IP Features supported |
Autosar Features Supported |
Not Supported |
|---|---|---|
|
The below Autosar Api’s supported
|
ETH Features not supported in Hardware
Supported in Hardware but not supported by Software
|
4.8.5.3. Assumptions¶
The Ethernet BSW stack is intended to be used wherever high data rates are required but no hard real-time is required. Of course, it can also be used for less demanding use cases, i.e. for low data rates.
4.8.5.4. Limitations¶
The Ethernet Driver module is only able to handle a single thread of execution. The execution must not be pre-empted by itself.
It is not possible to transmit data which exceeds the available buffer size of the used controller. Longer data has to be transmitted using the Internet Protocol (IP) or Transmission Control Protocol (TCP).
4.8.5.5. Design overview (Link to the Architecture document and Design Document)¶
Will be updated in future release.
4.8.5.6. File Structure¶
Description of static files is provided below:
Static source and header files |
Description |
|---|---|
Eth.h |
Contains the APIs of the ETH driver to be used by. |
Eth_Irq.h |
Contains ISR function declaration. |
Eth.c |
Contains the implementation of the ETH driver to be used by. |
Eth_Irq.c |
Eth Interrupt service routines. |
Eth_Priv.c Cpsw.c cpsw_ale.c cpsw_mdio.c |
Contains module private functions used by main APIs. |
Eth_Priv.h Cpsw.h cpsw_ale.h cpsw_cpts.h cpsw_mdio.h cpsw_priv.h cpsw_stats.h |
Internal header files. |
hw_cpsw_ale.h hw_cpsw_cpdma.h hw_cpsw_cpts.h hw_cpsw_mdio.h hw_cpsw_port.h hw_cpsw_ss.h hw_cpsw_stats.h |
Contains Register address and operational macros. |
Description of generated files is provided below:
Plugin Files |
Descriptions |
|---|---|
Eth_Cfg.h |
Contains the pre-complier switches. |
Eth_PBcfg.c |
Contains all channels Post-Build Configured parameters. |
Eth_Cfg.c |
Contains all channels Pre-Compile Configured parameters. |
Eth_Lcfg.c |
Contains all channels Link time Configured parameters. |
Figure 4: Eth header file include structure
4.8.6. Deviations to requirements (Requirement Traceability)¶
4.8.6.1. Module Requirements¶
Will be updated in future release.
4.8.6.2. Deviation of requirements against AUTOSAR specification requirements¶
Will be updated in future release.
4.8.7. Integration Details¶
4.8.7.1. Dependency on Other Software Modules¶
4.8.7.1.1. MCU¶
The module MCU powers up the microcontrollers peripherals at startup time and initializes the PLL and the internal clock domains which go to the Ethernet unit. Interrupt crossbar configuration and mapping of interrupts to core also taken care by MCU.
4.8.7.1.2. PORT¶
For PORT (IO PAD) configuration of Ethernet module PORT driver is used. Multiple configurations are available depending on Ethernet port used and mode of operation (like MII, RMII and RGMII).
4.8.7.1.3. OSEK / AUTOSAR OS (Optional)¶
An operating system can be used for task scheduling, interrupt handling, global suspend and restore of interrupts and creating of the Interrupt Vector Table. The Ethernet module may use OSEK/AUTOSAR OS to suspend and restore global interrupts.
Apart from AUTOSAR OS module OS Counter Id can be configured from the Eth configuration.
4.8.7.1.4. Error Handling module¶
4.8.7.1.5. DET¶
The module Ethernet depends on the DET (by default) to report development errors. Detection and reporting of development errors can be enabled or disabled by the switch “Enable Development Error Detection” on the tab “General Settings” within the module Ethernet.
The following table represents the service IDs:
Service ID |
Service |
|---|---|
0x01 |
Eth_Init |
0x03 |
Eth_SetControllerMode |
0x04 |
Eth_GetControllerMode |
0x05 |
Eth_WriteMii |
0x06 |
Eth_ReadMii |
0x08 |
Eth_GetPhysAddr |
0x09 |
Eth_ProvideTxBuffer |
0x0A |
Eth_Transmit |
0x0B |
Eth_Receive |
0x0C |
Eth_TxConfirmation |
0x0D |
Eth_GetVersionInfo |
0x12 |
Eth_UpdatePhysAddrFilter |
0x13 |
Eth_SetPhysAddr |
0x14 |
Eth_GetCounterValues |
0x15 |
Eth_GetRxStats |
0x16 |
Eth_GetCurrentTime |
0x17 |
Eth_EnableEgressTimeStamp |
0x18 |
Eth_GetEgressTimeStamp |
0x19 |
Eth_GetIngressTimeStamp |
0x1C |
Eth_GetTxStats |
0x1D |
Eth_GetTxErrorCounterValues |
0x20 |
Eth_MainFunction |
The errors reported to DET module are described in the following table:
Type of Error |
Relevance |
Related Error code |
Value (Hex) |
|---|---|---|---|
API service called with wrong controller index |
Development |
ETH_E_INV_CTRL_IDX |
[0x1] |
API service called when controller is not initialized |
Development |
ETH_E_UNINIT |
[0x2] |
API is called with wrong pointer value (e.g., NULL pointer) |
Development |
ETH_E_PARAM_POINTER |
[0x3] |
API service called with wrong / inconsistent parameter(s) |
Development |
ETH_E_INV_PARAM |
[0x4] |
API service called with wrong / inconsistent controller mode |
Development |
ETH_E_INV_MODE |
[0x5] |
The following table shows which parameter checks are performed on which services:
Services |
ETH_E_UNINIT |
ETH_E_INV_CTRL_IDX |
ETH_E_INV_PARAM |
ETH_E_PARAM_POINTER |
ETH_E_INIT_FAILED |
ETH_E_INV_MODE |
|---|---|---|---|---|---|---|
Eth_Init |
x |
x |
||||
Eth_SetControllerMode |
x |
x |
||||
Eth_GetControllerMode |
x |
x |
x |
|||
Eth_GetPhysAddr |
x |
x |
x |
|||
Eth_SetPhysAddr |
x |
x |
x |
|||
Eth_UpdatePhysAddrFilter |
x |
x |
x |
|||
Eth_WriteMii |
x |
x |
||||
Eth_ReadMii |
x |
x |
||||
Eth_GetCounterValues |
x |
x |
x |
|||
Eth_GetRxStats |
x |
x |
x |
|||
Eth_GetTxStats |
x |
x |
x |
|||
Eth_GetTxErrorCounterValues |
x |
x |
x |
|||
Eth_GetCurrentTime |
x |
x |
x |
|||
Eth_EnableEgressTimeStamp |
x |
x |
x |
|||
Eth_GetEgressTimeStamp |
x |
x |
x |
|||
Eth_GetIngressTimeStamp |
x |
x |
x |
|||
Eth_ProvideTxBuffer |
x |
x |
x |
|||
Eth_Transmit |
x |
x |
x |
x |
x |
x |
Eth_Receive |
x |
x |
x |
x |
||
Eth_TxConfirmation |
x |
x |
x |
|||
Eth_MainFunction |
x |
|||||
Eth_GetVersionInfo |
x |
4.8.7.1.6. Runtime Errors¶
There are no runtime errors.
4.8.7.1.7. DEM¶
By default, production code related errors are reported to the DEM using the service Dem_SetEventStatus().
The errors reported to DEM are described in the following table:
Error Code |
Description |
|
|---|---|---|
Assigned by DEM |
ETH_E_ACCESS |
This error is raised when monitoring the access to the Ethernet Controller fails. |
Assigned by DEM |
ETH_E_RX_FRAMES_LOST |
This error is raised when the loss of Ethernet frames during reception is detected. |
Assigned by DEM |
ETH_E_CRC |
This error is raised when the invalid Ethernet frames during reception is detected. |
Assigned by DEM |
ETH_E_UNDERSIZEFRAME |
This error is raised when the undersized Ethernet frames during reception is detected. |
Assigned by DEM |
ETH_E_OVERSIZEFRAME |
This error is raised when the oversized Ethernet frames during reception is detected. |
Assigned by DEM |
ETH_E_ALIGNMENT |
This error is raised when the misaligned Ethernet frames during reception is detected. |
Assigned by DEM |
ETH_E_SINGLECOLLISION |
This error is raised when the single Ethernet frame collision is detected. |
Assigned by DEM |
ETH_E_MULTIPLECOLLISION |
This error is raised when the multiple Ethernet frames collision is detected. |
Assigned by DEM |
ETH_E_LATECOLLISION |
This error is raised when the Ethernet frames late collision is detected. |
4.8.7.1.8. Callback Functions¶
The Ethernet driver does not provide any call back functions.
4.8.7.2. Hardware - Software - ISR API name mapping¶
Four interrupt routines are provided by the Ethernet driver. Basically, the ISR’s are in the Eth_Irq.c. User might edit it for adapting for the suitable OS. The current support is for the NON-OS Interrupts structure. The integrator has to map the interrupt service routines to the interrupt sources of the respective ETHERNET unit interrupt.
Following are ISRs for each hardware unit:
HW Interrupt |
HW Interrupt ID |
SW ISR for ETH module |
Description |
|---|---|---|---|
MSS_CPSW_TH_TRSH_INT
|
72
|
Eth_RxThreshIrqHdlr_0 |
THost (from Ethernet to host) non-paced pulse interrupt. |
MSS_CPSW_TH_INT
|
73
|
Eth_RxIrqHdlr_0 |
THost (from Ethernet to host) paced pulse interrupt. |
MSS_CPSW_FH_INT
|
74
|
Eth_TxIrqHdlr_0 |
FHost (from host to Ethernet) paced pulse interrupt. |
MSS_CPSW_MISC_INT
|
75
|
Eth_MiscIrqHdlr_0 |
Miscellaneous (statistics, host error and MDIO interrupts) non-paced pulse interrupt. |
4.8.7.3. Scheduling Strategy¶
4.8.7.3.1. SchM¶
Beside the OS the BSW Scheduler provides functions that module Ethernet calls at begin and end of critical sections.
4.8.7.3.2. Critical Sections¶
There is only one kind of critical sections in this driver. Within these sections all read /modify/write accesses to internal Ethernet status variables must be protected. Therefore, switching to tasks that also access Ethernet has to be avoided and all Ethernet interrupts have to be suspended.
4.8.8. API Description¶
4.8.8.1. Description of the API’s (Can be referred to Api Guide spec)¶
Will be updated in future release
4.8.8.2. List of API’s¶
The following table presents the list of API’s:
Service ID |
Autosar API’s Supported |
Comments |
|---|---|---|
0x01 |
Eth_Init |
|
0x03 |
Eth_SetControllerMode |
|
0x04 |
Eth_GetControllerMode |
|
0x05 |
Eth_WriteMii |
|
0x06 |
Eth_ReadMii |
|
0x08 |
Eth_GetPhysAddr |
|
0x09 |
Eth_ProvideTxBuffer |
Priority/QoS option not supported. |
0x0A |
Eth_Transmit |
|
0x0B |
Eth_Receive |
Priority/QoS option not supported. |
0x0C |
Eth_TxConfirmation |
|
0x0D |
Eth_GetVersionInfo |
|
0x12 |
Eth_UpdatePhysAddrFilter |
|
0x13 |
Eth_SetPhysAddr |
|
0x14 |
Eth_GetCounterValues |
|
0x15 |
Eth_GetRxStats |
|
0x16 |
Eth_GetCurrentTime |
|
0x17 |
Eth_EnableEgressTimeStamp |
|
0x18 |
Eth_GetEgressTimeStamp |
|
0x19 |
Eth_GetIngressTimeStamp |
|
0x1C |
Eth_GetTxStats |
|
0x1D |
Eth_GetTxErrorCounterValues |
|
0x20 |
Eth_MainFunction |
Refer Autosar SWS for API description mentioned in above table.
4.8.8.3. Description on Non Standard API’s¶
Not Applicable.
4.8.9. Configuration Description¶
4.8.9.1. Configuration Variants¶
The ETH is configured through GUI in Post-Build, Pre-Compile and Link-Time Variants.
Variants
|
Configured Files
|
|---|---|
PostBuild |
Eth_PBcfg.c , Eth_Cfg.h |
Pre-Compile |
Eth_Cfg.c , Eth_Cfg.h |
Link-Compile |
Eth_Lcfg.c , Eth_Cfg.h |
4.8.9.2. Parameter Description¶
4.8.9.2.1. Standard Configuration¶
Standard Parameters |
Description |
Default Value |
Range |
Unit / Datatype |
|---|---|---|---|---|
EthCtrlEnableMii |
Enables / Disables Media Independent Interface (MII) for transceiver access |
FALSE |
TRUE FALSE |
Boolean |
EthCtrlEnableRxInterrupt |
Enables / Disables receive interrupt |
TRUE |
TRUE FALSE |
Boolean |
EthCtrlEnableTxInterrupt |
Enables / Disables transmit interrupt |
TRUE |
TRUE FALSE |
Boolean |
EthCtrlIdx |
Specifies the instance ID of the configured controller |
0 |
0..1 |
INTEGER |
EthCtrlMacLayerSpeed |
Defines the baud rate of the MAC layer. This Autosar parameter is not used. for configuration use IP specific parameter EthMacConnectionType. |
ETH_MAC_LAYER_SPEED_1G |
ETH_MAC_LAYER_SPEED_100M ETH_MAC_LAYER_SPEED_10G ETH_MAC_LAYER_SPEED_10M ETH_MAC_LAYER_SPEED_1G |
ENUMERATION |
EthCtrlMacLayerSubType |
Defines the MAC layer subtype of a switch port.This Autosar parameter is not used. for configuration use IP specific parameter EthMacConnectionType. |
REDUCED |
REDUCED REVERSED SERIAL STANDARD> UNIVERSAL_SERIAL |
ENUMERATION |
EthCtrlMacLayerType |
Defines the MAC layer type of the ethernet controller.This Autosar parameter is not used. for configuration use IP specific parameter EthMacConnectionType. |
ETH_MAC_LAYER_TYPE_XGMII |
ETH_MAC_LAYER_TYPE_XGMII ETH_MAC_LAYER_TYPE_XMII ETH_MAC_LAYER_TYPE_XXGMII |
ENUMERATION |
EthCtrlPhyAddress |
Specifies the unique 48-bit physical address (MAC address) of the controller in network byte order. |
11-22-33-44-55-66 |
STRING |
|
EthCtrlConfigEgressFifoBufLenByte |
Length of Fifo elements in bytes. This Parameter not used, added for QoS implementation in Future |
1522 |
0..65535 |
INTEGER |
EthCtrlConfigEgressFifoBufTotal |
Fifo buffer count. This Parameter not used, added for QoS implementation in Future |
2 |
0..65535 |
INTEGER |
EthCtrlConfigEgressFifoIdx |
Egress Fifo index.This Parameter not used, added for QoS implementation in Future |
0 |
0..255 |
INTEGER |
EthCtrlConfigEgressFifoPriorityAssignment |
|
0 |
0..7 |
INTEGER |
EthCtrlConfigSchedulerPredecessorOrder |
Defines the order of the scheduler predecessorsThis Parameter not used, added for QoS implementation in Future |
0 |
0..9223372036854775807 |
INTEGER |
EthCtrlConfigShaperIdleSlope |
Defines the increase of credit in bits per second for the AVB shaper.This Parameter not used, added for QoS implementation in Future |
0 |
0..9223372036854775807 |
INTEGER |
EthCtrlConfigIngressFifoBufLenByte |
Length of Fifo elements in bytes.This Parameter not used, added for QoS implementation in Future |
1522 |
0..65535 |
INTEGER |
EthCtrlConfigIngressFifoBufTotal |
Fifo buffer count.This Parameter not used, added for QoS implementation in Future |
0..65536 |
INTEGER |
|
EthCtrlConfigIngressFifoIdx |
Ingress Fifo index.This Parameter not used, added for QoS implementation in Future |
2 |
0..255 |
INTEGER |
EthCtrlConfigIngressFifoPriorityAssignment |
Message ingress prority assignment.This Parameter not used, added for QoS implementation in Future |
0 |
0..7 |
INTEGER |
EthDevErrorDetect |
Switches the development error detection and notification on or off. |
FALSE |
TRUE FALSE |
Boolean |
EthGetDropCountApi |
Enables / Disables Eth_GetCounterValues API. |
FALSE |
TRUE FALSE |
Boolean |
EthGetEtherStatsApi |
Enables / Disables Eth_GetEtherStats API. |
FALSE |
TRUE FALSE |
Boolean |
EthGetTxErrorCounterValuesApi |
Enables/Disables Eth_GetTxErrorCounterValues API |
FALSE |
TRUE FALSE |
Boolean |
EthGetTxStatsApi |
Enables/Disables Eth_GetTxStats API. |
FALSE |
TRUE FALSE |
Boolean |
EthGlobalTimeSupport |
Enables/Disables the GlobalTime APIs used amongst others by Global Time Synchronization over Ethernet. |
FALSE |
TRUE FALSE |
Boolean |
EthIndex |
Specifies the InstanceId of this module instance. If only one instance is present it shall have the Id 0. |
0 |
0..255 |
INTEGER |
EthMainFunctionPeriod |
Specifies the period of main function Eth_MainFunction in seconds. Ethernet driver does not require this information but the BSW scheduler |
0 |
0..infinity |
INTEGER |
EthMaxCtrlsSupported |
Limits the total number of supported controllers. |
1 |
1..255 |
INTEGER |
EthUpdatePhysAddrFilter |
Enables/Disables optional API Eth_UpdatePhysAddrFilter |
FALSE |
TRUE FALSE |
Boolean |
EthVersionInfoApi |
Enables / Disables version info API |
FALSE |
TRUE FALSE |
Boolean |
EthTrafficShapingSupport |
|
TRUE |
TRUE FALSE |
Boolean |
EthCtrlEnableOffloadChecksumICMP |
Enables / Disables hardware offloading for ICMP checksums. |
FALSE |
TRUE FALSE |
Boolean |
EthCtrlEnableOffloadChecksumIPv4 |
Enables / Disables hardware offloading for IPv4 checksums. |
FALSE |
TRUE FALSE |
Boolean |
EthCtrlEnableOffloadChecksumTCP |
Enables / Disables hardware offloading for TCP checksums |
FALSE |
TRUE FALSE |
Boolean |
EthCtrlEnableOffloadChecksumUDP |
Enables / Disables hardware offloading for UDP checksums |
FALSE |
TRUE FALSE |
Boolean |
4.8.9.2.2. IP Specific Configuration¶
Standard Parameters |
Description |
Default Value |
Range |
Unit / Datatype |
|---|---|---|---|---|
EthMacConnectionType |
This parameter can be used to select Mac connection type (including speed and Duplex) |
ETH_MAC_CONN_TYPE_RGMII_DETECT_INBAND |
ETH_MAC_CONN_TYPE_MII_10_HALF ETH_MAC_CONN_TYPE_MII_10_FULL ETH_MAC_CONN_TYPE_MII_100_HALF ETH_MAC_CONN_TYPE_MII_100_FULL ETH_MAC_CONN_TYPE_RMII_10_HALF ETH_MAC_CONN_TYPE_RMII_10_FULL ETH_MAC_CONN_TYPE_RMII_100_HALF ETH_MAC_CONN_TYPE_RMII_100_FULL ETH_MAC_CONN_TYPE_RGMII_FORCE_100_HALF ETH_MAC_CONN_TYPE_RGMII_FORCE_100_FULL ETH_MAC_CONN_TYPE_RGMII_FORCE_1000 ETH_MAC_CONN_TYPE_RGMII_DETECT_INBAND |
Enumeration |
EthPort |
Specifies the port of the Ethernet |
ETH_PORT1 |
ETH_PORT1 |
Enumeration |
EthPacingClkFreq |
Port VID bit |
125000000 |
0 to 4294967295 |
Integer |
EthRxInterruptPacingEnabled |
Enable/Disable Rx interrupt pacing |
TRUE |
TRUE FALSE |
Boolean |
EthRxInterruptPerMsec |
Port VID bit |
0 |
0..4294967295 |
Integer |
EthTxInterruptPerMsec |
Port VID bit |
0 |
0..4294967295 |
Integer |
EthTxInterruptPacingEnabled |
Enable/Disable Rx interrupt pacing |
TRUE |
TRUE FALSE |
Integer |
EthDmaModeFlags |
Port VID bit |
0 |
0..4294967295 |
Integer |
EthRxThresholdCount |
Port VID bit |
0 |
0..4294967295 |
Integer |
EthMdioBusFreq |
Bus frequency for the MII module |
0 |
0..4294967295 |
Integer |
EthMdioClockFreq |
Clock frequency for MDIO link |
0 |
0..4294967295 |
Integer |
EthCptsInputFreq |
CPTS input clock frequency. Default CPTS input frequency is 266MHz. |
0 |
0..4294967295 |
Integer |
EthCptsVlanType |
Time sync HW supports 2 level tagging. Select appropriate level to enable time sync on VLAN tagged packet |
ETH_CPTS_VLAN_TYPE_NONE |
ETH_CPTS_VLAN_TYPE_NONE ETH_CPTS_VLAN_TYPE_SINGLE_TAG ETH_CPTS_VLAN_TYPE_STACKED_TAGS ETH_CPTS_VLAN_TYPE_INVALID |
Enumeration |
EthCptsMessageCfgEnum |
Enumerates CPTS Ethernet Message Types |
ETH_CPTS_MESSAGE_SYNC |
ETH_CPTS_MESSAGE_SYNC ETH_CPTS_MESSAGE_DELAY_REQ ETH_CPTS_MESSAGE_PDELAY_REQ ETH_CPTS_MESSAGE_PDELAY_RESP ETH_CPTS_MESSAGE_FOLLOW_UP ETH_CPTS_MESSAGE_DELAY_RESP ETH_CPTS_MESSAGE_PDELAY_RESP_FOLLOW_UP ETH_CPTS_MESSAGE_ANNOUNCE ETH_CPTS_MESSAGE_SIGNALING ETH_CPTS_MESSAGE_MANAGEMENT ETH_CPTS_MESSAGE_ALL |
Enumeration |
ChannelBandwidth |
Desired bandwidth in Mbps for channel. Supported only in RGMII 1000Mbps mode.This Parameter not used, added for QoS implementation in Future |
30 |
0..1000 |
Integer |
EthCpswRateLimitCfgEnum |
Enumerates CPSW Rate Limit Types.This Parameter not used, added for QoS implementation in Future |
ETH_PORT_RATE_LIMIT_PRI1_ENABLE |
ETH_PORT_RATE_LIMIT_PRI3_ENABLE ETH_PORT_RATE_LIMIT_PRI2_ENABLE ETH_PORT_RATE_LIMIT_PRI1_ENABLE ETH_PORT_RATE_LIMIT_DISABLE |
Enumeration |
EthCpswRateLimitPrioPerc |
|
0 |
0..100 |
Integer |
EthTrafficShapingSupport |
|
TRUE |
TRUE FALSE |
Boolean |
EthUseDefaultMacAddr |
Use default address for MAC ADDR |
TRUE |
TRUE FALSE |
Boolean |
EthIrqType |
Type of Isr function void functionname(void) CAT1 is interrupt void func(void) CAT2 is ISR(func) |
ETH_ISR_CAT1 |
ETH_ISR_VOID ETH_ISR_CAT1 ETH_ISR_CAT2 |
Enumeration |
EthNumTxBuffers |
Number of TX buffers |
256 |
8..1024 |
Integer |
EthNumRxBuffers |
Number of RX buffers |
256 |
8..1025 |
Integer |
EthBufLenByte |
Maximum rx/tx buffer length (frame length) in bytes |
1518 |
0..1518 |
Integer |
EthAutoBuffRotation |
Enable/Disable automatic buffer rotation |
TRUE |
TRUE FALSE |
Boolean |
EthDefaultOSCounterId |
Default Os Counter Id if node reference to OsCounter ref EthOsCounterRef is not set |
0 |
0..16 |
Integer |
EthTimeoutDuration |
ETH timeout - used in ETH busy wait |
3200 |
1..4294967295 |
Integer |
EthStatsInterruptEnable |
Enables/Disables interrupt for ethernet stats |
TRUE |
TRUE FALSE |
Boolean |
EthUsrMdioInterruptEnable |
Enables/Disables interrupt for mdio. |
TRUE |
TRUE FALSE |
Boolean |
EthHostErrorInterruptEnable |
Enables/Disables interrupt for host error |
TRUE |
TRUE FALSE |
Boolean |
EthDeviceVariant |
Select SOC variant .This parameter shall be used by driver to impose device specific constraints. The user guide shall detail the device specific constraints |
AM273x |
AM273x |
Enumeration |
EthEnableCacheOps |
Enable/Disable cache operations in Ethernet Driver |
FALSE |
TRUE/FALSE |
Boolean |
4.8.9.3. Configuration rules and constraints to enable plausibility checks¶
None
4.8.10. Memory Mapping¶
The objects (e.g., variables, functions, constants) are declared by compiler independent definitions – the compiler abstraction definitions. Each compiler abstraction definition is assigned to a memory section. The following table contains the memory section names and the compiler abstraction definitions defined for the Ethernet and illustrate their assignment among each other.
Compiler Abstraction Definitions / Memory Mapping Sections |
ETH_CODE |
ETH_VAR |
ETH_VAR_NOINIT |
ETH_CONST |
ETH_APPL_DATA |
ETH_APPL_CODE |
|---|---|---|---|---|---|---|
ETH_START_SEC_VAR_INIT_UNSPECIFIED (.data) |
x |
|||||
ETH_STOP_SEC_VAR_INIT_UNSPECIFIED |
x |
|||||
ETH_START_SEC_CODE (.text) |
x |
|||||
ETH_STOP_SEC_CODE |
x |
|||||
ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED (.bss) |
x |
|||||
ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED |
x |
|||||
ETH_START_SEC_CONST_UNSPECIFIED (.const) |
x |
|||||
ETH_STOP_SEC_CONST_UNSPECIFIED |
x |
|||||
ETH_START_SEC_ISR_CODE (.text) ETH_STOP_SEC_ISR_CODE |
x |
|||||
For application code used by ETH (like callback functions) |
x |
4.8.11. Memory footprint¶
Please refer Memory Footprint for more details.
4.8.12. Performance¶
Will be updated in future release.
4.8.13. Example Usage¶
4.8.13.1. Steps to build and run example¶
Ethernet example application demonstrating the MCAL ETH driver features is in folder <MCAL_ROOT>/examples/Eth.
This application can be built from the build folder by giving gmake -s eth_app PLATFORM=am273.
By default, in Example code PORT 1 is enabled for Transmit/receive functionality.
Connect CANoe/PC through Ethernet cable to RJ45 of AM273x Board PORT 1.
Flash the eth_app binary (under mcal/binary/eth_app/bin/am273) file on Hardware.
Connect to Serial terminal to see the output.
If CANoe using then speed(100M) should be set accordingly in CANoe settings.
If Wireshark using:
in Auto negotiation no additional settings required.
in Force configuration Speed and duplex should be set as per configuration in PC network settings.
During Receive test the control will be in while loop until the expected frames received.
Here we will send Frames from CANoe/ColaSoft Packet builder software to the EVM. (gAppObj.stats.recvPacketCnt will update if the frame received in EthIf_RxIndication).
During Filter test Frames should send from CANoe/ColaSoft Packet builder with expected destination MAC address to the EVM.
During Time stamp test PTP packets should send from CANoe/ColaSoft Packet builder with expected destination MAC address to the EVM.
During Transmission test: EVM will transmit the frames to CANoe/PC. we can observe the Frames on CANoe/Wireshark.
At the end we can see the Statistics in serial terminal.
4.8.13.2. External set up Information¶
Connect CANoe/PC through Ethernet cable to RJ45 of AM273x EVM PORT.
If CANoe tool is connected to AM273x EVM then we can observe both Tx and Rx frames in CANoe software. If PC is connected to AM273x EVM then use wireshark tool to observe Transmitted frames from EVM, For Receive functionality send frames from Colasoft Packet builder tool to EVM.
If CANoe using then speed(as per configuration:100M) should be set accordingly in CANoe settings. If Wireshark and Packet builder softwares using:
in Auto negotiation mode no additional settings required.
in Force configuration mode Speed and duplex should be set as per Eth and EthTrcv configuration in PC network settings.
4.8.13.3. Configuration used to test this example¶
ETH Configuration:
Build Variant : ETH_VARIANT_POST_BUILD
EthStatsInterruptEnable : True
EthUsrMdioInterruptEnable : True
EthHostErrorInterruptEnable : True
EthCtrlEnableRxInterrupt : True
EthCtrlEnableTxInterrupt : True
Number of TX buffers : 24
Number of RX buffers : 48
EthPort : ETH_PORT1
EthMacConnectionType : ETH_MAC_CONN_TYPE_RGMII_DETECT_INBAND
ETHTRCV Configuration
Build Variant : ETHTRCV_POST_BUILD_VARIANT
EthTrcv1000Mbps_speed : True
EthTrcvAutoNegotiationEnabled : (uint32 ) TRUE
EthTrcvConnNeg : TRCV_CONN_NEG_AUTO
EthTrcvPhyAdvertiseCapability : 10mbps Half_Duplex, 10mbps Full_Duplex, 100mbps Half_Duplex, 100mbps Full_Duplex
EthTrcvLinkPartnerCapability : 0U
EthTrcvGigabitCapabilityEnabled : (uint32 )TRUE
EthTrcvDuplexMode : ETHTRCV_DUPLEX_MODE_FULL
EthTrcvEnableLoopback : (boolean)FALSE
4.8.13.4. Example Logs¶
ETH_APP: Sample Application - STARTS !!!
ETH MCAL Version Info
---------------------
Vendor ID : 44
Module ID : 88
SW Major Version : 9
SW Minor Version : 0
SW Patch Version : 1
ETH TRCV MCAL Version Info
---------------------
Vendor ID : 44
Module ID : 73
SW Major Version : 9
SW Minor Version : 0
SW Patch Version : 1
ETH_APP: EthTrcv Controller mode change - ETHTRCV_MODE_ACTIVE
ETH_APP:ETHTRCV Link up
ETH_APP:ETHTRCV baud rate = 100Mbps
ETH_APP:ETHTRCV in full duplex mode
ETH_APP:ETHTRCV Normal Operation
ETH_APP:ETHTRCV Tx mode Normal
ETH_APP:ETHTRCV PHY(DP83867E) ID is proper. OUI: 0x80028, Model No: 0x23, Revision No: 0x1
ETH_APP:ETHTRCV Cable Diagnostics Ok
ETH_APP:EthTRCV Controller Up
MAC Port 1 Address:
00:01:02:03:04:05
-----------------------------------------------
*********** ETH FILTER TEST *******************
-----------------------------------------------
Adding MAC Address to filter:
0a:0b:0c:0d:0e:0f
Waiting to receive 1000 packets from PC packet player..
Send packets with destination MAC address:
0a:0b:0c:0d:0e:0f
Removing MAC Address from filter:
0a:0b:0c:0d:0e:0f
Multicast address filter test
Adding multicast MAC Address to filter:
01:00:5e:0d:0e:0f
Waiting to receive 1000 packets from PC packet player..
Send packets with destination MAC address:
01:00:5e:0d:0e:0f
Removing MAC Address from filter:
01:00:5e:0d:0e:0f
Opening up filter completely (ALE bypass)
Waiting to receive 1000 packets from PC packet player..
Send packets with any MAC address
ALE Bypass Transmit Test
Transmitting 50000 packets
Expect PC Wireshark to receive 50000 packets..
Max Tx Packet Size Test passed
Disabling filter bypass & adding host address back to filter
Waiting to receive 1000 packets from PC packet player..
Send packets with Controller MAC address
-----------------------------------------------
***********Time Stamping Test*******************
-----------------------------------------------
Get global time after delay upto 1000ms (loop=10)
Curr_Time: [ 0. 5. 104120320] TimeSync_Diff: [ 0. 5. 104120320](32K Cntr Diff 26373)
Curr_Time: [ 0. 8. 933019648] TimeSync_Diff: [ 0. 3. 828899328](32K Cntr Diff 23874)
Curr_Time: [ 0. 9. 536908288] TimeSync_Diff: [ 0. 0. 603888640](32K Cntr Diff 3717)
Curr_Time: [ 0. 12. 150359040] TimeSync_Diff: [ 0. 2. 613450752](32K Cntr Diff 16279)
Curr_Time: [ 0. 12. 444243968] TimeSync_Diff: [ 0. 0. 293884928](32K Cntr Diff 1780)
Curr_Time: [ 0. 15. 617693696] TimeSync_Diff: [ 0. 3. 173449728](32K Cntr Diff 19780)
Curr_Time: [ 0. 15. 706584064] TimeSync_Diff: [ 0. 0. 88890368](32K Cntr Diff 498)
Curr_Time: [ 0. 17. 839599616] TimeSync_Diff: [ 0. 2. 133015552](32K Cntr Diff 13280)
Curr_Time: [ 0. 18. 938488832] TimeSync_Diff: [ 0. 1. 98889216](32K Cntr Diff 6811)
Curr_Time: [ 0. 19. 406938112] TimeSync_Diff: [ 0. 0. 468449280](32K Cntr Diff 2874)
Time Sync Packet Egress Test
--------------------------------
Packet Egress TS:[ 0. 19. 475499008][ ETH_VALID]
Packet Egress TS:[ 0. 0. 0][ETH_INVALID]
Packet Egress TS:[ 0. 19. 575541760][ ETH_VALID]
Packet Egress TS:[ 0. 19. 525523456][ ETH_VALID]
Packet Egress TS:[ 0. 19. 675580416][ ETH_VALID]
Packet Egress TS:[ 0. 19. 625566208][ ETH_VALID]
Packet Egress TS:[ 0. 19. 775621120][ ETH_VALID]
Packet Egress TS:[ 0. 19. 725604864][ ETH_VALID]
Packet Egress TS:[ 0. 0. 0][ETH_INVALID]
Packet Egress TS:[ 0. 19. 825641472][ ETH_VALID]
Packet Egress TS:[ 0. 19. 875655680][ ETH_VALID]
Packet Egress TS:[ 0. 19. 925676032][ ETH_VALID]
Packet Egress TS:[ 0. 19. 975690240][ ETH_VALID]
Packet Egress TS:[ 0. 20. 25710592][ ETH_VALID]
Packet Egress TS:[ 0. 20. 75726848][ ETH_VALID]
Packet Egress TS:[ 0. 20. 125751296][ ETH_VALID]
Packet Egress TS:[ 0. 20. 175765504][ ETH_VALID]
Packet Egress TS:[ 0. 20. 225785856][ ETH_VALID]
Packet Egress TS:[ 0. 20. 275800064][ ETH_VALID]
Packet Egress TS:[ 0. 20. 325820416][ ETH_VALID]
Packet Egress TS:[ 0. 20. 375836672][ ETH_VALID]
Packet Egress TS:[ 0. 20. 425854976][ ETH_VALID]
Packet Egress TS:[ 0. 20. 475871232][ ETH_VALID]
Packet Egress TS:[ 0. 20. 525891584][ ETH_VALID]
Packet Egress TS:[ 0. 20. 575905792][ ETH_VALID]
Packet Egress TS:[ 0. 20. 625926144][ ETH_VALID]
Packet Egress TS:[ 0. 20. 675940352][ ETH_VALID]
Packet Egress TS:[ 0. 20. 725960704][ ETH_VALID]
Packet Egress TS:[ 0. 20. 775974912][ ETH_VALID]
Packet Egress TS:[ 0. 20. 825995264][ ETH_VALID]
Packet Egress TS:[ 0. 20. 876011520][ ETH_VALID]
Packet Egress TS:[ 0. 20. 926029824][ ETH_VALID]
Packet Egress TS:[ 0. 20. 976046080][ ETH_VALID]
Packet Egress TS:[ 0. 21. 26066432][ ETH_VALID]
Packet Egress TS:[ 0. 21. 76080640][ ETH_VALID]
Packet Egress TS:[ 0. 21. 126100992][ ETH_VALID]
Packet Egress TS:[ 0. 21. 176115200][ ETH_VALID]
Packet Egress TS:[ 0. 21. 226135552][ ETH_VALID]
Packet Egress TS:[ 0. 21. 276149760][ ETH_VALID]
Packet Egress TS:[ 0. 21. 326170112][ ETH_VALID]
Packet Egress TS:[ 0. 21. 376186368][ ETH_VALID]
Packet Egress TS:[ 0. 21. 426206720][ ETH_VALID]
Packet Egress TS:[ 0. 0. 1384545][ ETH_VALID]
Packet Egress TS:[ 0. 0. 51404044][ ETH_VALID]
Packet Egress TS:[ 0. 0. 101419792][ ETH_VALID]
Packet Egress TS:[ 0. 0. 151444048][ ETH_VALID]
Packet Egress TS:[ 0. 0. 201459296][ ETH_VALID]
Packet Egress TS:[ 0. 0. 251478752][ ETH_VALID]
Packet Egress TS:[ 0. 0. 301494144][ ETH_VALID]
Packet Egress TS:[ 0. 0. 351514400][ ETH_VALID]
Packet Egress TS:[ 0. 0. 401528800][ ETH_VALID]
Packet Egress TS:[ 0. 0. 451549184][ ETH_VALID]
Packet Egress TS:[ 0. 0. 501564160][ ETH_VALID]
Packet Egress TS:[ 0. 0. 551584192][ ETH_VALID]
Packet Egress TS:[ 0. 0. 601599424][ ETH_VALID]
Packet Egress TS:[ 0. 0. 651618816][ ETH_VALID]
Packet Egress TS:[ 0. 0. 701634368][ ETH_VALID]
Packet Egress TS:[ 0. 0. 751654464][ ETH_VALID]
Packet Egress TS:[ 0. 0. 801668800][ ETH_VALID]
Packet Egress TS:[ 0. 0. 851689408][ ETH_VALID]
Packet Egress TS:[ 0. 0. 901704192][ ETH_VALID]
Packet Egress TS:[ 0. 0. 951724224][ ETH_VALID]
Packet Egress TS:[ 0. 1. 1739200][ ETH_VALID]
Packet Egress TS:[ 0. 1. 51759104][ ETH_VALID]
Packet Egress TS:[ 0. 1. 101773952][ ETH_VALID]
Packet Egress TS:[ 0. 1. 151794432][ ETH_VALID]
Packet Egress TS:[ 0. 1. 201808768][ ETH_VALID]
Packet Egress TS:[ 0. 1. 251829504][ ETH_VALID]
Packet Egress TS:[ 0. 1. 301844096][ ETH_VALID]
Packet Egress TS:[ 0. 1. 351864192][ ETH_VALID]
Packet Egress TS:[ 0. 1. 401879424][ ETH_VALID]
Packet Egress TS:[ 0. 1. 451899136][ ETH_VALID]
Packet Egress TS:[ 0. 1. 501914240][ ETH_VALID]
Packet Egress TS:[ 0. 1. 551934080][ ETH_VALID]
Packet Egress TS:[ 0. 1. 601949312][ ETH_VALID]
Packet Egress TS:[ 0. 1. 651969408][ ETH_VALID]
Packet Egress TS:[ 0. 1. 701984256][ ETH_VALID]
Packet Egress TS:[ 0. 1. 752004096][ ETH_VALID]
Packet Egress TS:[ 0. 1. 802019200][ ETH_VALID]
Packet Egress TS:[ 0. 1. 852038784][ ETH_VALID]
Packet Egress TS:[ 0. 1. 902054016][ ETH_VALID]
Packet Egress TS:[ 0. 1. 952074368][ ETH_VALID]
Packet Egress TS:[ 0. 2. 2089088][ ETH_VALID]
Packet Egress TS:[ 0. 2. 52109568][ ETH_VALID]
Packet Egress TS:[ 0. 2. 102124160][ ETH_VALID]
Packet Egress TS:[ 0. 2. 152143872][ ETH_VALID]
Packet Egress TS:[ 0. 2. 202159104][ ETH_VALID]
Packet Egress TS:[ 0. 2. 252178688][ ETH_VALID]
Packet Egress TS:[ 0. 2. 302193920][ ETH_VALID]
Packet Egress TS:[ 0. 2. 352214528][ ETH_VALID]
Packet Egress TS:[ 0. 2. 402229248][ ETH_VALID]
Packet Egress TS:[ 0. 2. 452248832][ ETH_VALID]
Packet Egress TS:[ 0. 2. 502264320][ ETH_VALID]
Packet Egress TS:[ 0. 2. 552283904][ ETH_VALID]
Packet Egress TS:[ 0. 2. 602299392][ ETH_VALID]
Packet Egress TS:[ 0. 2. 652319232][ ETH_VALID]
Packet Egress TS:[ 0. 2. 702334208][ ETH_VALID]
Packet Egress TS:[ 0. 2. 752354048][ ETH_VALID]
Packet Egress TS:[ 0. 2. 802369024][ ETH_VALID]
Packet Egress TS:[ 0. 2. 852389120][ ETH_VALID]
Packet Egress TS:[ 0. 2. 902404352][ ETH_VALID]
Packet Egress TS:[ 0. 2. 952424448][ ETH_VALID]
Packet Egress TS:[ 0. 3. 2439424][ ETH_VALID]
Packet Egress TS:[ 0. 3. 52459008][ ETH_VALID]
Packet Egress TS:[ 0. 3. 102473984][ ETH_VALID]
Packet Egress TS:[ 0. 3. 152494336][ ETH_VALID]
Packet Egress TS:[ 0. 3. 202508800][ ETH_VALID]
Packet Egress TS:[ 0. 3. 252529152][ ETH_VALID]
Packet Egress TS:[ 0. 3. 302544128][ ETH_VALID]
Packet Egress TS:[ 0. 3. 352563968][ ETH_VALID]
Packet Egress TS:[ 0. 3. 402579200][ ETH_VALID]
Packet Egress TS:[ 0. 3. 452599296][ ETH_VALID]
Packet Egress TS:[ 0. 3. 502614016][ ETH_VALID]
Packet Egress TS:[ 0. 3. 552634368][ ETH_VALID]
Packet Egress TS:[ 0. 3. 602649088][ ETH_VALID]
Packet Egress TS:[ 0. 3. 652669440][ ETH_VALID]
Packet Egress TS:[ 0. 3. 702684416][ ETH_VALID]
Packet Egress TS:[ 0. 3. 752704256][ ETH_VALID]
Packet Egress TS:[ 0. 3. 802719232][ ETH_VALID]
Packet Egress TS:[ 0. 3. 852739072][ ETH_VALID]
Packet Egress TS:[ 0. 3. 902754304][ ETH_VALID]
Packet Egress TS:[ 0. 3. 952774144][ ETH_VALID]
Packet Egress TS:[ 0. 4. 2789120][ ETH_VALID]
Packet Egress TS:[ 0. 4. 52809216][ ETH_VALID]
Packet Egress TS:[ 0. 4. 102824192][ ETH_VALID]
Packet Egress TS:[ 0. 4. 152844032][ ETH_VALID]
Packet Egress TS:[ 0. 4. 202859008][ ETH_VALID]
Packet Egress TS:[ 0. 4. 252879104][ ETH_VALID]
Packet Egress TS:[ 0. 4. 302894080][ ETH_VALID]
Packet Egress TS:[ 0. 4. 352914432][ ETH_VALID]
Packet Egress TS:[ 0. 4. 402928640][ ETH_VALID]
Packet Egress TS:[ 0. 4. 452948992][ ETH_VALID]
Packet Egress TS:[ 0. 4. 502964224][ ETH_VALID]
Packet Egress TS:[ 0. 4. 552984064][ ETH_VALID]
Packet Egress TS:[ 0. 4. 602999296][ ETH_VALID]
Packet Egress TS:[ 0. 4. 653019136][ ETH_VALID]
Packet Egress TS:[ 0. 4. 703034368][ ETH_VALID]
Packet Egress TS:[ 0. 4. 753054208][ ETH_VALID]
Packet Egress TS:[ 0. 4. 803068928][ ETH_VALID]
Packet Egress TS:[ 0. 4. 853089280][ ETH_VALID]
Packet Egress TS:[ 0. 4. 903104512][ ETH_VALID]
Packet Egress TS:[ 0. 4. 953124352][ ETH_VALID]
Packet Egress TS:[ 0. 5. 3139072][ ETH_VALID]
Packet Egress TS:[ 0. 5. 53158912][ ETH_VALID]
Packet Egress TS:[ 0. 5. 103174144][ ETH_VALID]
Packet Egress TS:[ 0. 5. 153194496][ ETH_VALID]
Packet Egress TS:[ 0. 5. 203209216][ ETH_VALID]
Packet Egress TS:[ 0. 5. 253229568][ ETH_VALID]
Packet Egress TS:[ 0. 5. 303244288][ ETH_VALID]
Packet Egress TS:[ 0. 5. 353264128][ ETH_VALID]
Packet Egress TS:[ 0. 5. 403278848][ ETH_VALID]
Packet Egress TS:[ 0. 5. 453298688][ ETH_VALID]
Packet Egress TS:[ 0. 5. 503314432][ ETH_VALID]
Packet Egress TS:[ 0. 5. 553334272][ ETH_VALID]
Packet Egress TS:[ 0. 5. 603349504][ ETH_VALID]
Packet Egress TS:[ 0. 5. 653369344][ ETH_VALID]
Packet Egress TS:[ 0. 5. 703384576][ ETH_VALID]
Packet Egress TS:[ 0. 5. 753403904][ ETH_VALID]
Packet Egress TS:[ 0. 5. 803419648][ ETH_VALID]
Packet Egress TS:[ 0. 5. 853438976][ ETH_VALID]
Packet Egress TS:[ 0. 5. 903454208][ ETH_VALID]
Packet Egress TS:[ 0. 5. 953474560][ ETH_VALID]
Packet Egress TS:[ 0. 6. 3489280][ ETH_VALID]
Packet Egress TS:[ 0. 6. 53509632][ ETH_VALID]
Packet Egress TS:[ 0. 6. 103524352][ ETH_VALID]
Packet Egress TS:[ 0. 6. 153544192][ ETH_VALID]
Packet Egress TS:[ 0. 6. 203558912][ ETH_VALID]
Packet Egress TS:[ 0. 6. 253578752][ ETH_VALID]
Packet Egress TS:[ 0. 6. 303594496][ ETH_VALID]
Packet Egress TS:[ 0. 6. 353614336][ ETH_VALID]
Packet Egress TS:[ 0. 6. 403629056][ ETH_VALID]
Packet Egress TS:[ 0. 6. 453649408][ ETH_VALID]
Packet Egress TS:[ 0. 6. 503664640][ ETH_VALID]
Packet Egress TS:[ 0. 6. 553683968][ ETH_VALID]
Packet Egress TS:[ 0. 6. 603699712][ ETH_VALID]
Packet Egress TS:[ 0. 6. 653719040][ ETH_VALID]
Packet Egress TS:[ 0. 6. 703733760][ ETH_VALID]
Packet Egress TS:[ 0. 6. 753754112][ ETH_VALID]
Packet Egress TS:[ 0. 6. 803768832][ ETH_VALID]
Packet Egress TS:[ 0. 6. 853789184][ ETH_VALID]
Packet Egress TS:[ 0. 6. 903803904][ ETH_VALID]
Packet Egress TS:[ 0. 6. 953824256][ ETH_VALID]
Packet Egress TS:[ 0. 7. 3838976][ ETH_VALID]
Packet Egress TS:[ 0. 7. 53858816][ ETH_VALID]
Packet Egress TS:[ 0. 7. 103874560][ ETH_VALID]
Packet Egress TS:[ 0. 7. 153894400][ ETH_VALID]
Packet Egress TS:[ 0. 7. 203909120][ ETH_VALID]
Packet Egress TS:[ 0. 7. 253929472][ ETH_VALID]
Packet Egress TS:[ 0. 7. 303944192][ ETH_VALID]
Packet Egress TS:[ 0. 7. 353964032][ ETH_VALID]
Packet Egress TS:[ 0. 7. 403979264][ ETH_VALID]
Packet Egress TS:[ 0. 7. 453998592][ ETH_VALID]
Packet Egress TS:[ 0. 7. 504014336][ ETH_VALID]
Packet Egress TS:[ 0. 7. 554034688][ ETH_VALID]
Packet Egress TS:[ 0. 7. 604048896][ ETH_VALID]
Packet Egress TS:[ 0. 7. 654069248][ ETH_VALID]
Packet Egress TS:[ 0. 7. 704084480][ ETH_VALID]
Packet Egress TS:[ 0. 7. 754104320][ ETH_VALID]
Packet Egress TS:[ 0. 7. 804119552][ ETH_VALID]
Packet Egress TS:[ 0. 7. 854138880][ ETH_VALID]
Time Sync Packet Ingress Test
---------------------------------
Send timestamp (0x88F7) packets (100) from PC
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]8832]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]8720]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]9440]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]9808]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]6688]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]7664]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]7744]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]6064]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]6544]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]9120]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]6720]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]5536]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]9536]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]1216]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]3136]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]6272]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]3312]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]0112]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]3472]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]0608]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]3808]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]9968]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]8368]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]4608]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]9984]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]5664]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]7680]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]1456]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]3296]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]1376]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]9376]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]5360]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]1760]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]0512]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]9568]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]5216]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]8336]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]4176]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]8368]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]3696]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]6496]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]6416]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]9424]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]6992]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]5152]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]6240]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]9728]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]6416]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]7616]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]6416]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]9952]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]2512]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]6848]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]9088]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]8848]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]0528]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]1344]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]2784]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]6464]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]4224]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]8640]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]4880]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]4000]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]2880]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]4560]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]9072]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]6096]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]4336]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]2752]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]9232]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]9968]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]0432]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]7872]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]0640]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]1920]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]2400]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]5552]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]7872]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]5232]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]5136]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]2400]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]7248]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]0288]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]5968]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]3856]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]6896]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]9744]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]9504]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]5952]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]2880]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]4448]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]3248]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]0128]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]4624]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]6864]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]4864]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]7600]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]1440]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]8080]
Packet Ingress MessagType- CPTS_MESSAGE_SYNC, SeqID- 0 [ [ ETH_VALID]2880]
----------------------------
Time Stamping Test Completed
----------------------------
---------------------------------------------
***********ETH RECEIVE TEST*******************
---------------------------------------------
Waiting to receive 50000 packets from CANoe/PC packet player
Receive packet statistics:
EXPECTEDETHERTYPE_IPV4 (0x800) = 37
EXPECTEDETHERTYPE_VLAN (0x8100) = 0
UNEXPECTEDETHERTYPE = 53987
-----------------------------------------------
***********ETH TRANSMIT TEST*******************
-----------------------------------------------
Transmitting 50000 packets,
Expect CANoe / PC Wireshark to receive 50000 packets..
Stats: Sent=50000,
Transmitted 50000 packets
----------------------------
Controller 0 Counters
----------------------------
Buffer overruns : 0
CRC errors : 0
Undersize packets : 0
Oversized packets : 0
Alignment errors : 0
Erroneous inbound : 0
Erroneous outbound: 0
Single collision : 0
Multiple collision: 0
Deferred transm : 0
Late collisions : 0
Excessive colls : 0
Carrier loss : 0
----------------------------
Controller 0 Rx Statistics
----------------------------
Rx Drop Events : 354
Rx Octets : 3554190
Rx Packets : 57543
Rx Bcast Packets : 40
Rx Mcast Packets : 2161
Rx CRC/Align Errors : 0
Rx Undersized Packets: 0
Rx Oversized Packets : 0
Rx Fragments : 0
Rx Jabbers : 0
Rx Unicast Packets : 53141
----------------------------
Controller 0 Tx Statistics
----------------------------
Tx Num octets : 151817800
Tx No Unicast Packets : 100200
Tx Unicast Packets : 0
--------------------------------
Controller 0 Tx Error Counters
--------------------------------
Tx Deferred transm : 0
Tx Single collisions : 0
Tx Multiple collisions : 0
Tx Late collisions : 0
Tx Excessive collisions : 0
ETH Test Passed!!!
4.8.14. FAQ’s¶
None
4.8.15. Test Report (Link to test report)¶
Will be updated in future release.
4.8.16. References¶
Autosar SWS 4.3.1 will be updated in future release.
4.8.17. TI Disclaimer¶
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, license, warranty or endorsement thereof.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction o f this information with alteration voids all warranties provided for an associated TI product or service, is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use.
Resale of TI’s products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service, is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use.
Also see: Standard Terms and Conditions of Sale for Semiconductor Products https://www.ti.com/sc/docs/stdterms.htm
Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265
