4.6. CDD_PWM¶
4.6.1. About This Document¶
Document Title |
User Guide of CDD PWM Driver |
Document Version |
Version 1.1 |
Company |
Texas Instruments |
Document Name |
CDD PWM User Guide |
4.6.2. Document Revision History¶
Version |
Date |
Revision History |
Status |
|---|---|---|---|
Version 1.0 |
20 Dec 2023 |
Initial Release. |
Approved |
Version 1.1 |
16 Feb 2024 |
Update on Driver Speicfic API Details |
Approved |
4.6.3. Table of contents¶
4.6.4. Acronyms and Definitions¶
Acronyms and Definitions Used are presented in below table.
Acronyms |
Descriptions |
|---|---|
BSW |
Basic Software |
DET |
Default Error Tracer |
PWM |
Pulse Width Modulation |
MCU |
Micro Controller Unit |
OS |
Operating System |
PLL |
Phase Locked loop |
AUTOSAR |
Automotive Open System Architecture |
CDD |
Complex Device Driver |
HW |
Hardware |
SW |
Software |
DEM |
Diagnostic Event Manager |
DMA |
Direct Memory Access |
MCAL |
Microcontroller Abstraction Layer |
OS |
Operating System |
API |
Application Programming Interface |
4.6.5. Functional Overview¶
4.6.5.1. Brief Overview¶
This document describes the functionality, API and configuration of the AUTOSAR BSW CDD module PWM.
Supported AUTOSAR Release |
4.3.1 |
Supported Configuration Variants |
Pre-Compile, Post-build |
Vendor ID |
CDD_PWM_VENDOR_ID (44) |
Module ID |
CDD_PWM_MODULE_ID (255) |
Supported Platform |
AM263x |
This document describes the functionality and the API of the CDD_PWM (Complex Device Driver_Pulse Width Modulation) driver for the AM263x.
The CDD PWM driver depends on other modules like DET for error handling, OSEK/AUTOSAR OS for interrupt handling, MCU module for system clock settings and SchM module which is BSW Scheduler provides functions that module CDD PWM calls at begin and end of critical sections.
The CDD PWM module generates pulses with variable pulse width, allows the selection of the duty cycle and the signal period time and offers services to,
Start output of a PWM signal.
Stop output of a PWM signal.
Set parameters of a PWM channel’s waveform.
Set compare value for Events.
Enable/disable notifications.
Allows the selection of duty cycle and signal period time.
CDD PWM supports addition of various submodules which have additional features like,
4.6.5.1.1. Time-Base submodule¶
The time-base submodule consists of a dedicated 16-bit counter, along with built-in synchronization logic to allow multiple ePWM modules to work together as a single system.
A clock pre-scaler divides the EPWM clock to the counter and a period register is used to control the frequency and period of the generated waveform.
The period register has a shadow register, which acts like a buffer to allow the register updates to be synchronized with the counter, thus avoiding corruption or spurious operation from the register being modified asynchronously by the software.
The time-base counter operates in three modes: up-count, down-count, and up-down-count.
In up-count mode the time-base counter starts counting from zero and increments until it reaches the period register value, then the time-base counter resets to zero and the count sequence starts again.
In down-count mode the time-base counter starts counting from the period register value and decrements until it reaches zero, then the time-base counter is loaded with the period value and the count sequence starts again.
In up-down-count mode the time-base counter starts counting from zero and increments until it reaches the period register value, then the time base counter decrements until it reaches zero and the count sequence repeats. The up-count and down-count modes are used to generate asymmetrical waveforms, and the up-down-count mode is used to generate symmetrical waveforms.
Figure 1: Time-Base Submodule
4.6.5.1.2. Compare submodule¶
The counter-compare submodule continuously compares the time-base count value to four counter compare registers (CMPA, CMPB, CMPC, and CMPD) and generates four independent compare events (i.e. time-base counter equals a compare register value) which are fed to the action-qualifier and event-trigger submodules.
The counter compare registers are shadowed to prevent corruption or glitches during the active PWM cycle.
Typically CMPA and CMPB are used to control the duty cycle of the generated PWM waveform.
All four compare registers can be used to start an ADC conversion or generate an ePWM interrupt.
For the up-count and down count modes, a counter match occurs only once per cycle, however for the up-down-count mode a counter match occurs twice per cycle since there is a match on the up count and down count.
Figure 2: Compare Submodule
The counter-compare registers CMPA and CMPB each have an associated shadow register. Shadowing provides a way to keep updates to the registers synchronized with the hardware. When shadowing is used,updates to the active registers only occur at strategic points. This prevents corruption or spurious operation due to the register being asynchronously modified by software. The memory address of the active register and the shadow register is identical.
4.6.5.1.3. Action Qualifier submodule¶
The action-qualifier submodule is the key element in the ePWM module which is responsible for constructing and generating the switched PWM waveforms. It utilizes match events from the time-base and counter-compare submodules for performing actions on the EPWMxA and EPWMxB output pins. These first three submodules are the main blocks which are used for generating a basic PWM waveform.
The Action Qualifier actions are setting the pin high, clearing the pin low, toggling the pin, or do nothing to the pin, based independently on count-up and count-down time-base match event.
The match events occur when the time-base counter equals the period register value, the time-base counter is zero, the time-base counter equals CMPA, the time-base counter equals CMPB, or for a Trigger event (T1 and T2) based on a comparator, trip, or sync signal.
Zero and period actions are fixed in time, whereas CMPA and CMPB actions are moveable in time by programming their respective registers. Actions are configured independently for each output using shadowed registers, and any or all events can be configured to generate actions on either output. Also, the output pins can be forced to any action using software.
The next few figures show how the setting of the action qualifier with the compare matches are used to modulate the output pins.
The output pins for EPWMA and EPWMB are completely independent.
In above figure , the EPWMA output is being set high on the zero match and cleared low on the compare A match. The EPWMB output is being set high on the zero match and cleared low on the compare B match.
In the above figure , the EPWMA output is being set high on the compare A match and being cleared low on the compare B match, while the EPWMB output is being toggled on the zero match.
In the above figure , the EPWMA output is being set high on the compare A match and being cleared low on the compare B match, while the EPWMB output is being toggled on the zero match.
Figure 3: Action Qualifier Waveforms using different output actions on the up-count and down count
And finally in the above figure, again using different output actions on the up-count and down count, the EPWMA output is being set high on the compare A up-count match and being cleared low on the compare B down-count match. The EPWMB output is being cleared low on the zero match and being set high on the period match.
Asymmetric and Symmetric Waveform Generation using the ePWM
PWM Switching Frequency
The PWM carrier frequency is determined by the value contained in the time-base period register, and the frequency of the clocking signal. The value needed in the period register is:
Asymmetric PWM
Period register = (switching period/ timer period) -1
Period register = (Tpwm / TTBCLK) -1
Symmetric PWM
Period register = switching period/ 2(timer period)
Period register = Tpwm / (2 * TTBCLK)
Notice that in the symmetric case, the period value is half that of the asymmetric case. This is because for up/down counting, the actual timer period is twice that specified in the period register (i.e. the timer counts up to the period register value, and then counts back down).
PWM Resolution
The PWM compare function resolution can be computed once the period register value is determined. The largest power of 2 that is less than (or close to) the period value is used for the function resolution. As an example, if asymmetric was 1000, and symmetric was 500, then:
Asymmetric PWM: approx. 10 bit resolution since 2^10 = 1024, approximately equal to 1000
Symmetric PWM: approx. 9 bit resolution since 2^9 = 512, approximately equal to 500
PWM Duty Cycle
Duty cycle calculations are used to define where CMP registers are set. These calculations are simple, provided one remembers that the PWM signal is initially inactive during any particular timer period, and becomes active after the (first) compare match occurs. The timer compare register should be loaded with the value as follows:
Asymmetric PWM: CMPX = (100% - duty cycle)*TBPRD
Symmetric PWM: CMPX = (100% - duty cycle)*TBPRD
PWM Computation Example
Determine TBPRD and CMPA for 100 kHz, 25% duty symmetric PWM from a 100 MHz time base clock.
TBPRD = 0.5* (FTBCLK/FPWM) = 0.5 (100 MHz/ 100 kHz) = 500
CMPA = (100% - duty cycle) TBPRD = 0.75*500=375
Determine TBPRD and CMPA for 100 kHz, 25% duty asymmetric PWM from a 100 MHz time base clock.
TBPRD = (FTBCLK/FPWM) -1 = (100 MHz/ 100 kHz) -1 = 999
CMPA = (100% - duty cycle) (TBPRD +1) -1 = 0.75 * (999 + 1) -1 = 749
4.6.5.1.4. Dead-Band submodule¶
The dead-band sub-module provides a means to delay the switching of a gate signal, thereby allowing time for gates to turn off and preventing a short circuit.
This sub-module supports independently programmable rising-edge and falling-edge delays with various options for generating the appropriate signal outputs on EPWMxA and EPWMxB.
The key functions of the dead-band module are:
Generating appropriate signal pairs (EPWMxA and EPWMxB) with dead-band relationship from a single EPWMxA input
Programming signal pairs for:
– Active high (AH)
– Active low (AL)
– Active high complementary (AHC)
– Active low complementary (ALC)
Adding programmable delay to rising edges (RED)
Adding programmable delay to falling edges (FED)
Can be totally bypassed from the signal path
Figure 4: Dead-Band Waveforms for Typical Cases (0% < Duty < 100%)
Dead-band control provides a convenient means of combating current shoot-through problems in a power converter. Shoot-through occurs when both the upper and lower gates in the same phase of a power converter are open simultaneously. This condition shorts the power supply and results in a large current draw. Shoot-through problems occur because transistors open faster than they close, and because high-side and low-side power converter gates are typically switched in a complimentary fashion. Although the duration of the shoot-through current path is finite during PWM cycling, (i.e. the closing gate will eventually shut), even brief periods of a short circuit condition can produce excessive heating and overstress in the power converter and power supply.
4.6.5.1.5. Trip-Zone submodule¶
Trip-Zone has a fast, clock-independent logic path to high-impedance the EPWMxA/B output pins.
Interrupt latency may not protect hardware when responding to over current conditions or short-circuits through ISR software.
It supports:
One-shot trip for major short circuits or over current conditions and
Cycle-by-cycle trip for current limiting operation.
Figure 5: Trip-Zone Submodule
The trip-zone submodule utilizes a fast clock-independent logic mechanism to quickly handle fault conditions by forcing the EPWMxA and EPWMxB outputs to a safe state, such as high, low, or high-impedance.
The trip-zone signals can be generated externally from any GPIO pin which is mapped through the Input X-Bar (TZ1 – TZ3), internally from an inverted eQEP error signal (TZ4), system clock failure (TZ5), or from an emulation stop output from the CPU (TZ6). Additionally, numerous trip-zone source signals can be generated from the digital-compare subsystem.
4.6.5.1.6. Chopper submodule¶
The PWM chopper submodule is used with pulse transformer-based gate drives to control the power switching devices.
This submodule modulates a high-frequency carrier signal with the PWM waveform that is generated by the action-qualifier and dead-band submodules. The key functions of the PWM chopper submodule are:
Programmable chopping (carrier) frequency
Programmable pulse width of first pulse
Programmable duty cycle of second and subsequent pulses
Can be fully bypassed if not required.
Programmable options are available to support the magnetic properties and characteristics of the transformer and associated circuitry.
Shown in the figure below, a high-frequency carrier signal is ANDed with the ePWM outputs. Also, this circuit provides an option to include a larger, one-shot pulse width before the sustaining pulses.
Figure 6: Chopper Submodule
4.6.5.1.7. Event-trigger submodule¶
The event-trigger submodule manages the events generated by the time-base, counter-compare, and digital-compare submodules to generate an interrupt to the CPU and/or a start of conversion pulse to the ADC when a selected event occurs. It provides full visibility of event generation using event counters and flags. The event-trigger submodule also incorporates pre-scaling logic to issue an interrupt request or ADC start of conversion at every event or up to every fifteenth event.
Figure 7: Event Trigger Submodule
These event triggers can occur when the time-base counter equals zero, period, zero or period, the up/down count match of a compare register. It also enable/disable ADC Trigger.
4.6.5.2. Initialization¶
The driver CDD_PWM is initialized by calling Cdd_Pwm_Init() with a pointer to a configuration as parameter. To re-initialize call Cdd_Pwm_DeInit() first and then Cdd_Pwm_Init() with a different configuration.
The below table represents the various states of CDD PWM Channel
States |
Module state |
|---|---|
CDD_PWM driver Status uninitialized |
CDD_PWM_STATUS_UNINIT |
CDD_PWM driver Status Initialized |
CDD_PWM_STATUS_INIT |
CDD_PWM driver Status stopped |
CDD_PWM_STATUS_STOPPED |
CDD_PWM driver Status running |
CDD_PWM_STATUS_RUNNING |
4.6.6. Driver Architecture¶
The following figure shows where the CDD is located in the AUTOSAR architecture.
Figure 8: CDD in AUTOSAR architecture
The AUTOSAR Architecture distinguishes on the highest abstraction level between three software layers Application, Runtime Environment and Basic Software which run on a Microcontroller.
CDD PWM Driver: The Cdd_Pwm driver is part of the Complex Device Driver layer (CDD). The driver provides special functions and features with direct access to the microcontroller using specific interrupts and/or complex microcontroller peripherals, external devices to fulfill the special functional and timing requirements.
4.6.6.1. Supported and Not Supported Features¶
The features listed in this chapter cover the complete functionality specified
IP Supported Features |
AUTOSAR Supported Features |
Not Supported |
|---|---|---|
Dedicated 16-bit time-base counter with period and frequency control |
Provide services to start and stop the output of pulse-width- modulated wave forms/signal. |
APIs related to the power state and API for getting current PWM state |
Time-base counter three modes of operation (i)Up-Down Count Mode (ii)Up-Count Mode (iii)Down-Count Mode |
Changing of frequency and duty cycle for a PWM channel at runtime besides the default configuration. |
Asynchronous override control of PWM signals through software. |
Generates events based on programmable time stamps using the CMPA, CMPB, CMPC, and CMPD registers(Counter Compare) |
Enable/disable notifications. Allows the selection of duty cycle and signal period time. |
Programmable phase-control support for lag or lead operation relative to other ePWM modules |
Two PWM outputs (EPWMxA and EPWMxB) that can be used in the following configurations – Two independent PWM outputs with single edge operation. – Two independent PWM outputs with dual- edge symmetric operation. |
There are a number of waveforms, which are supported by the PWM driver. The most widely used is standard PWM. Each period begins with an active state and changes to idle after the duty cycle has ended. Idle output is configurable allowing high or low for idle state according to requirement. |
Hardware-locked (synchronized) phase relationship on a cycle-by-cycle basis |
All events can trigger both CPU interrupts and ADC start of conversion. (SOC). |
Minimum dead band block which provides the ability to configure the minimum dead band duration between a complimentary set of PWMs. |
|
Programmable trip zone allocation of both cycle-by-cycle trip and one-shot trip on fault conditions. |
Illegal Combo Logic |
|
A trip condition can force either high, low,or high-impedance state logic levels at PWM outputs. |
Diode Emulation which provides hardware features and the necessary hooks into other IPs to implement robust diode mode sense and control in noisy environment. |
|
Dead-band generation with independent rising and falling edge delay control. |
Digital Compare |
|
PWM chopping by high-frequency carrier signal, useful for pulse transformer gate drives. |
Programmable event prescaling minimizes CPU overhead on interrupts |
|
The HRPWM is based on micro edge positioner(MEP) technology. |
||
HRPWM feature should use the TI-supplied MEP scale factor optimizer (SFO) software function.The SFO function helps to dynamically determine the number of MEP steps per SYSCLKOUT period. |
Figure 9: Standard alignment left and right, expressed by high and low priority level
4.6.6.2. Assumptions¶
None
4.6.6.3. Limitations¶
Note
CDD PWM module and MCAL PWM module shall not use same EPWM channel.
4.6.6.4. Design overview¶
Will be updated in future release
4.6.6.5. File Structure¶
Static source C File Structure is defined below in the table.
Static source C File Structure |
Description |
|---|---|
Cdd_Pwm.c |
Implementation of the API’s for CDD_PWM driver. |
Cdd_Pwm.h |
Contains the API’s of the CDD_PWM driver to be used by upper layers |
Cdd_Pwm_Priv.c |
Contains Internal Functions Definitions. |
Cdd_Pwm_Priv.h |
Contains data structures and Internal function declarations |
Cdd_Pwm_Irq.c |
Contains ISR function definitions. |
Cdd_Pwm_Irq.h |
Contains ISR function declaration |
Cdd_Pwm_Platform.h |
Contains the platform dependent Macros and structure declaration. |
Cdd_Pwm_Platform.h |
Contains the platform dependent Macros and structure declaration. |
Cdd_Pwm_Sfo.c |
Contains the SFO functionality. |
Cdd_Pwm_Sfo.h |
Contains the header file for SFO functionality. |
Cdd_Pwm_Types.h |
Contains the data tyeps of CDD PWM. |
Plugin file structure is defined below in the table.
Plugin Structure |
Descriptions |
|---|---|
Cdd_Pwm_Cfg.h |
Contains the base addresses, Precompile switches, Macros for channels, counters etc. |
Cdd_Pwm_PBcfg.c |
Contains all channels Post-Build Configuration parameters |
Cdd_Pwm_Cfg.c |
Contains all channels Pre-Compile Configuration parameters |
The below diagram shows the files structure for the PWM driver.Similarly is the strcuture for CDD PWM
Figure 10: Reference : Header file structure of the PWM driver
4.6.7. Deviations to requirements(Requirement Traceability)¶
4.6.7.1. Module Requirements¶
Please refer Software Product Specification document provided as part of CSP.
4.6.7.2. Deviation of requirements against AUTOSAR specification requirements¶
Will be updated in future release
4.6.8. Integration Details¶
4.6.8.1. Dependency on Other Software Modules¶
4.6.8.1.1. OSEK / AUTOSAR OS (Optional)¶
An operating system can be used fortask scheduling, interrupt handling, global suspend and restore of interrupts and creating of the Interrupt Vector Table. The CDD_PWM module may use OSEK/AUTOSAR OS to suspend and restore global interrupts.
4.6.8.1.2. MCU¶
The module MCU powers up the microcontroller’s peripherals at startup time and initializes the PLL(not directly) and the internal clock domains.
The CDD_PWM module depends on MCU module for enabling CDD_PWM clock for channel and crossbar interrupt mapping of CDD_PWM interrupts depending on the CDD_PWM channel configured.
Suppose the CDD_PWM channel 0 is configured for CDD_PWM module, Then, the MCU module container McuCddPwmConfiguration should also be configured.
Similarly, the crossbar interrupts also need to be mapped in MCU module according to CDD_PWM channel configured. The CDD_PWM interrupts needs to be mapped to the corresponding cross bar interrupt.
4.6.8.1.3. PORT¶
Module PORT configures the port pins that are used for output of CDD_PWM signal. For details see Technical Reference of Port.
4.6.8.1.4. DET¶
The module CDD_PWM depends on the DET (by default) in order to report development errors. Detection and reporting of development errors can be enabled or disabled by the switch.
“Enable Development Error Detection”.
The DET can be replaced optionally by an equivalent component which is responsible to recognize development errors, if no DET component is available.
4.6.8.1.5. Error Handling¶
Development Error Reporting
By default, development errors are reported to the Development Error Tracer (DET) using the service Det_ReportError() if detection and reporting of development errors is enabled in the configuration tool. If another module is used for development error reporting, the function name for reporting the error can be configured by the integrator, but must have the same signature as the service Det_ReportError().
AUTOSAR requires that API functions shall check the validity of their respective parameters.
Type of Error |
Relevance |
Related Error Code |
Value |
|---|---|---|---|
API service used without module initialization. |
Development |
CDD_PWM_E_UNINIT |
0x02U |
API Cdd_Pwm_Init service called with wrong parameter. |
Development |
CDD_PWM_E_INIT_FAILED |
0x0BU |
API service used with an invalid channel Identifier. |
Development |
CDD_PWM_E_PARAM_INVALID_CHANNEL |
0x03U |
API Cdd_Pwm_SetPinAction() called with an invalid pin action. |
Development |
CDD_PWM_E_PARAM_INVALID_ACTION |
0x05U |
Usage of Cdd_Pwm_DisableNotification() or Cdd_Pwm_EnableNotification on a channel where a NULL pointer is configured as the notification function. |
Development |
CDD_PWM_E_NO_VALID_NOTIF |
0x06U |
API Cdd_Pwm_Init() called while the CDD_PWM driver has already been initialized. |
Development |
CDD_PWM_E_ALREADY_INITIALIZED |
0x07U |
API Cdd_Pwm_GetVersionInfo() is called with a NULL parameter. |
Development |
CDD_PWM_E_PARAM_POINTER |
0x08U |
Cdd_Pwm_StartChannelCounter() called on a channel that is in state RUNNING. |
Development |
CDD_PWM_E_BUSY |
0x09U |
Cdd_Pwm_SetPinAction() called for a channel that doesn’t have an associated output pin. |
Development |
CDD_PWM_E_PARAM_NO_PIN |
0x0AU |
Cdd_Pwm_SetRelativeThreshold() called for with a compare match parameter greater than maximum |
Development |
CDD_PWM_E_PARAM_INVALID_VALUE |
0x1AU |
Invalid Channel parameter |
Development |
CDD_PWM_E_PARAM_CHANNEL |
0x1BU |
4.6.8.1.6. Error Handling: Runtime Errors¶
None
4.6.8.1.7. Callback Notification¶
The Cdd_Pwm driver provide configured notification call back for each interrupt occurred and Trip Zone notification.
4.6.8.2. Hardware - Software - ISR API name mapping¶
For each of the configured hardware units, one interrupt service routine has to be mapped. The Integrator has to map the interrupt service routines to the interrupt sources of the respective CDD_PWM unit interrupt. The supported ISR’s are part of the Cdd_Pwm_Irq.h file.
For interrupt notification, ISR’s are provided in CDD PWM driver. There is one ISR for each CDD PWM hardware unit. Depending on hardware unit configured, it will call group notify function. The interrupt service routines shall be mapped to the interrupt sources of the respective cross bar interrupt. There are 4 Groups and each has 32 Channels:
ISR for PWM Interrupt:
Cdd_Pwm_<GROUP>_Ch<n>Isr
Here, <GROUP> represents the GROUP number, which can be G0, G1, G2, G3.
<n> represents the EPWM Channel number, which can be from 0 to 31.
ISR for PWM Trip Zone:
Cdd_Pwm_<GROUP>_TzCh<n>Isr
Here, <GROUP> represents the GROUP number, which can be G0, G1, G2, G3.
<n> represents the EPWM Channel number, which can be from 0 to 31.
4.6.8.3. Scheduling Strategy¶
4.6.8.3.1. SchM (Optional)¶
Beside the OSEK / AUTOSAR OS the BSW Scheduler provides functions that module CDD PWM calls at begin and end of critical sections. There is only one kind of critical sections in this driver. Within these sections all read /modify / write accesses to internal CDD PWM status variables must be protected. This is handled internally in the CDD PWM driver by invoking SchM_Enter_Cdd_Pwm_PWM_EXCLUSIVE_AREA_0/ SchM_Exit_Cdd_Pwm_PWM_EXCLUSIVE_AREA_0()
4.6.9. API Description¶
4.6.9.1. Description of the API’s¶
4.6.9.1.1. Cdd_Pwm_Init¶
Cdd_Pwm_Init shall initialize all internals variables and the used CDD PWM structure of the microcontroller according to the parameters specified in ConfigPtr.
Input Parameters : ConfigPtr - It is the Pointer to Driver configuration.
Output Parameters : void
4.6.9.1.2. Cdd_Pwm_DeInit¶
Cdd_Pwm_DeInit shall de-initialize CDD_PWM.
Input Parameters : None
Output Parameters : void
4.6.9.1.3. Cdd_Pwm_StartChannelCounter¶
Cdd_Pwm_StartChannelCounter shall start a CDD PWM channel.
Input Parameters : Cdd_Pwm_ChannelType ChannelNumber
Output Parameters : void
4.6.9.1.4. Cdd_Pwm_StopChannelCounter¶
Cdd_Pwm_StopChannelCounter shall stop a CDD PWM channel.
Input Parameters : Cdd_Pwm_ChannelType ChannelNumber
Output Parameters : void
4.6.9.1.5. Cdd_Pwm_GetCounter¶
Cdd_Pwm_GetCounter reads the current value of the counter.
Input Parameters : Cdd_Pwm_ChannelType ChannelNumber
Output Parameters : Cdd_Pwm_ValueType
4.6.9.1.6. Cdd_Pwm_SetPinAction¶
Cdd_Pwm_SetPinAction indicate the driver what shall be done automatically by hardware (if supported) upon compare match.
Input Parameters : Cdd_Pwm_ChannelType ChannelNumber, Cdd_Pwm_PinActionType PinAction
Output Parameters : void
PinAction can take following values:
– CDD_PWM_SET_HIGH - The channel pin will be set HIGH upon compare match
–CDD_PWM_SET_LOW - The channel pin will be set LOW upon compare match
–CDD_PWM_TOGGLE - The channel pin will be set to the opposite of its current level HIGH upon compare match
–CDD_PWM_DISABLE - The channel pin will remain at its current level upon compare match
4.6.9.1.7. Cdd_Pwm_SetRelativeThreshold¶
Cdd_Pwm_SetRelativeThreshold set the value of the channel threshold relative to the current value of the counter.
Input Parameters : Cdd_Pwm_ChannelType ChannelNumber, Cdd_Pwm_ValueType RelativeValue – The Value to be updated on the counter.
Output Parameters : Cdd_Pwm_ReturnType
Cdd_Pwm_ReturnType can take following values:
–CDD_PWM_CM_IN_REF_INTERVAL : The compare match will occur inside the current Reference Interval.
–CDD_PWM_CM_OUT_REF_INTERVAL: The compare match will not occur inside the current Reference
4.6.9.1.8. Cdd_Pwm_GetCounterStatus¶
Cdd_Pwm_GetCounterStatus gets the timer base status as indicated by the tbStatusMask parameter.
Input Parameters : uint32 Channel, tbStatusMask
Output Parameters : uint16
tbStatusMask can take following values:
-CDD_PWM_TB_STS_CTR_MAX : Time-Base Counter Max Latched Status,
-CDD_PWM_TB_STS_SYNCI : Input Synchronization Latched Status,
-CDD_PWM_TB_STS_CTR_DIR : Time-Base Counter Direction Status
4.6.9.1.9. Cdd_Pwm_ClearCounterStatus¶
Cdd_Pwm_ClearCounterStatus clears the Time base status bits indicated by the tbStatusClrMask parameter.
Input Parameters : uint32 Channel, tbStatusClrMask
Output Parameters : Std_ReturnType : E_OK or E_NOT_OK
tbStatusClrMask can take following values:
-CDD_PWM_TB_STS_CTR_MAX : Time-Base Counter Max Latched Status,
-CDD_PWM_TB_STS_SYNCI : Input Synchronization Latched Status
4.6.9.1.10. Cdd_Pwm_DisableNotification¶
Cdd_Pwm_DisableNotification disables the interrupts for channel.
Input Parameters : Cdd_Pwm_ChannelType ChannelNumber
Output Parameters : void
4.6.9.1.11. Cdd_Pwm_EnableNotification¶
Cdd_Pwm_EnableNotification enables the interrupts for channel.
Input Parameters : Cdd_Pwm_ChannelType ChannelParameter, Cdd_Pwm_InterruptType EdgeInterruptSource
Output Parameters : void
Cdd_Pwm_InterruptType Data type consists of the elements:
-Cdd_Pwm_EdgeNotificationType EdgeSource;
-uint32 interruptSource;
-uint32 mixedInterruptSource;
Cdd_Pwm_EdgeNotificationType EdgeSource – The Element represents the edge trigger for the channel notification. The Parameter value can be :
-CDD_PWM_RISING_EDGE,
-CDD_PWM_FALLING_EDGE,
-CDD_PWM_BOTH_EDGES
uint32 interrupt Source – The element represents the CDD PWM interrupt source. The Parameter value can be :
-CDD_PWM_INT_TBCTR_ZERO
-CDD_PWM_INT_TBCTR_PERIOD
-CDD_PWM_INT_TBCTR_ETINTMIX
-CDD_PWM_INT_TBCTR_U_CMPA
-CDD_PWM_INT_TBCTR_U_CMPC
-CDD_PWM_INT_TBCTR_D_CMPA
-CDD_PWM_INT_TBCTR_D_CMPC
-CDD_PWM_INT_TBCTR_U_CMPB
-CDD_PWM_INT_TBCTR_U_CMPD
-CDD_PWM_INT_TBCTR_D_CMPB
-CDD_PWM_INT_TBCTR_D_CMPD
mixed Interrupt Source - The Parameter shall be used when , the interrupt Source is CDD_PWM_INT_TBCTR_ETINTMIX. Incase of mixedsource we can enable two interrupt sources parallelly to occur. The Parameter value can be :
-CDD_PWM_INT_MIX_TBCTR_ZERO
-CDD_PWM_INT_MIX_TBCTR_PERIOD
-CDD_PWM_INT_MIX_DCAEVT1
-CDD_PWM_INT_MIX_TBCTR_U_CMPA
-CDD_PWM_INT_MIX_TBCTR_D_CMPA
-CDD_PWM_INT_MIX_TBCTR_U_CMPB
-CDD_PWM_INT_MIX_TBCTR_D_CMPB
-CDD_PWM_INT_MIX_TBCTR_U_CMPC
-CDD_PWM_INT_MIX_TBCTR_D_CMPC
-CDD_PWM_INT_MIX_TBCTR_U_CMPD
-CDD_PWM_INT_MIX_TBCTR_D_CMPD
4.6.9.1.12. Cdd_Pwm_EtIntrStatus¶
Cdd_Pwm_EtIntrStatus returns the CDD PWM event interrupt status.
Input Parameters : uint32 Channel
Output Parameters : uint16 : status of the event interrupt
4.6.9.1.13. Cdd_Pwm_EtIntrClear¶
Cdd_Pwm_EtIntrClear clears the interrupt. This will clear the interrupt flag bit and enable further interrupts pulses to be generated.
Input Parameters : uint32 Channel
Output Parameters : Std_ReturnType : E_OK or E_NOT_OK
4.6.9.1.14. Cdd_Pwm_EtGetEventCount¶
Cdd_Pwm_EtGetEventCount returns the number of events occurred.
Input Parameters : uint32 Channel
Output Parameters : uint16 – event count
4.6.9.1.15. Cdd_Pwm_SetPeriodDutyPhase¶
Cdd_Pwm_SetPeriodDutyPhase sets the period, dutyCycle and Phase of a PWM channel. The Same API shall be reused to generate the HR PWM signal.
Input Parameters : Cdd_Pwm_channelParametertype ChannelParameter
Output Parameters : void
Cdd_Pwm_channelParametertype consists of
-Cdd_Pwm_ChannelType ChannelNumber
-Cdd_Pwm_ValueType Period : Time Period Count Value
-uint32 DutyCycle : DutyCycle Count Value
-uint16 Phase : Phase Count Value
-Cdd_Pwm_OutputChType Output Output Channel(CDD_PWM_OUTPUT_CH_A, CDD_PWM_OUTPUT_CH_B, CDD_PWM_OUTPUT_CH_BOTH_A_AND_B)
4.6.9.1.16. Cdd_Pwm_SetOutputToIdle¶
Cdd_Pwm_SetOutputToIdle sets the PWM output to Idle state.
Input Parameters : Cdd_Pwm_ChannelType ChannelNumber
Output Parameters : void
4.6.9.1.17. Cdd_Pwm_RegisterReadback¶
Cdd_Pwm_RegisterReadback reads the important registers of the hardware unit and returns the value in the structure.
Input Parameters : Cdd_Pwm_ChannelType Cdd_PwmChannel, RegRbPtr : Pointer to Cdd_Pwm_RegisterReadbackType structure
Output Parameters : Std_ReturnType : E_OK or E_NOT_OK
4.6.9.1.18. Cdd_Pwm_GetVersionInfo¶
Cdd_Pwm_GetVersionInfo returns the version information of this module.
Input Parameters : VersionInfoPtr : Pointer to where to store the version information of this module.
Output Parameters : void
4.6.9.1.19. Cdd_Pwm_HrSetPeriodDutyPhase¶
Cdd_Pwm_HrSetPeriodDutyPhase sets the period, dutyCycle and Phase of a CDD PWM channel in the HR mode.
Input Parameters : Cdd_Pwm_channelParametertype ChannelParameter
Output Parameters : void
Cdd_Pwm_channelParametertype consists of
-Cdd_Pwm_ChannelType ChannelNumber
-Cdd_Pwm_ValueType Period : Time Period Count Value
-uint32 DutyCycle : DutyCycle Count Value
-uint16 Phase : Phase Count Value
-Cdd_Pwm_OutputChType Output Output Channel(CDD_PWM_OUTPUT_CH_A, CDD_PWM_OUTPUT_CH_B, CDD_PWM_OUTPUT_CH_BOTH_A_AND_B)
4.6.9.1.20. Cdd_Pwm_HrSfoCalibration¶
Cdd_Pwm_HrSfoCalibration sets the HRPWM SFO calibration.
Input Parameters : Cdd_Pwm_channelParametertype ChannelParameter
Output Parameters : void
Cdd_Pwm_channelParametertype consists of
-Cdd_Pwm_ChannelType ChannelNumber
-Cdd_Pwm_ValueType Period : Time Period Count Value
-uint32 DutyCycle : DutyCycle Count Value
-uint16 Phase : Phase Count Value
-Cdd_Pwm_OutputChType Output Output Channel(CDD_PWM_OUTPUT_CH_A, CDD_PWM_OUTPUT_CH_B, CDD_PWM_OUTPUT_CH_BOTH_A_AND_B)
4.6.9.1.21. Cdd_Pwm_HrSfoStatus¶
Cdd_Pwm_HrSfoStatus checks HRPWM SFO Calibration Status.
Input Parameters : uint32 ChannelNumber
Output Parameters : uint32
4.6.9.1.22. Cdd_Pwm_SetAdcTrigger¶
Cdd_Pwm_SetAdcTrigger shall enable or disable the ADC Trigger generated from CDD PWM module.
Input Parameters : uint32 Channel, Cdd_Pwm_AdcSocType adcSoc
Output Parameters : Std_ReturnType : E_OK or E_NOT_OK
Cdd_Pwm_AdcSocType consists of
-boolean channelEnable(Enable or Disable the ADC trigger source.)
-CDD_PWM_ADCStartOfConversionType adcSocSource (ADC SOC Source CDD_PWM_SOC_A / CDD_PWM_SOC_B)
-uint32 adcInterruptSource – The element represents the CDD ADC interrupt source. The Parameter value can be:
-CDD_PWM_SOC_DCxEVT1
-CDD_PWM_SOC_TBCTR_ZERO
-CDD_PWM_SOC_TBCTR_PERIOD
-CDD_PWM_SOC_TBCTR_MIXED_EVENT
-CDD_PWM_SOC_TBCTR_U_CMPA
-CDD_PWM_SOC_TBCTR_U_CMPC
-CDD_PWM_SOC_TBCTR_D_CMPA
-CDD_PWM_SOC_TBCTR_D_CMPC
-CDD_PWM_SOC_TBCTR_U_CMPB
-CDD_PWM_SOC_TBCTR_U_CMPD
-CDD_PWM_SOC_TBCTR_D_CMPB
-CDD_PWM_SOC_TBCTR_D_CMPD
-mixed Interrupt Source - The Parameter shall be used when , the adcInterruptSource is CDD_PWM_SOC_TBCTR_MIXED_EVENT
Incase of mixedsource we can enable two interrupt sources parallelly to occur. The Parameter value can be :
-CDD_PWM_INT_MIX_TBCTR_ZERO
-CDD_PWM_INT_MIX_TBCTR_PERIOD
-CDD_PWM_INT_MIX_DCAEVT1
-CDD_PWM_INT_MIX_TBCTR_U_CMPA
-CDD_PWM_INT_MIX_TBCTR_D_CMPA
-CDD_PWM_INT_MIX_TBCTR_U_CMPB
-CDD_PWM_INT_MIX_TBCTR_D_CMPB
-CDD_PWM_INT_MIX_TBCTR_U_CMPC
-CDD_PWM_INT_MIX_TBCTR_D_CMPC
-CDD_PWM_INT_MIX_TBCTR_U_CMPD
-CDD_PWM_INT_MIX_TBCTR_D_CMPD
4.6.9.1.23. Cdd_Pwm_SyncEnable¶
Cdd_Pwm_SyncEnable enables the synchronization of time base sub-module and configures the phase count value to be loaded after sync event, counter direction after sync event.
Input Parameters : uint32 Channel,uint32 tbPhsValue(Phase value to be reloaded after sync), uint32 counterDir(Counter directions after sync event)
Output Parameters : Std_ReturnType : E_OK or E_NOT_OK
counterDir values can be:
-CDD_PWM_TB_CNT_DIR_AFT_SYNC_DOWN : Count down after the synchronization event
-CDD_PWM_TB_CNT_DIR_AFT_SYNC_UP : Count up after the synchronization event.
4.6.9.1.24. Cdd_Pwm_SyncDisable¶
Cdd_Pwm_SyncDisable disables the synchronization. Even if sync-in event occurs the count value will not be reloaded.
Input Parameters : uint32 Channel
Output Parameters : Std_ReturnType : E_OK or E_NOT_OK
4.6.9.1.25. Cdd_Pwm_CounterComparatorCfg¶
Cdd_Pwm_CounterComparatorCfg configures the counter comparator and loads the comparator value. When Counter comparator value equals the counter value, then an event is generated both in the up direction and down direction.
Input Parameters : uint32 Channel, Cdd_Pwm_OutputChType cmpType, uint32 cmpVal(Comparator value that needs to be loaded in counter), uint32 shadowToActiveLoadTrigger, uint32 overwriteShadow(Enable or Disable the overwriteShadow)
Output Parameters : Std_ReturnType : E_OK or E_NOT_OK
Cdd_Pwm_OutputChType cmpType - Determines the Comparator Type, the parameter values can be
-CDD_PWM_OUTPUT_CH_A
-CDD_PWM_OUTPUT_CH_B
-CDD_PWM_OUTPUT_CH_BOTH_A_AND_B
uint32 shadowToActiveLoadTrigger – Shadow to active register load mode .
-CDD_PWM_CC_CMP_LOAD_MODE_CNT_EQ_ZERO : Load on CTR = 0: Time-base counter equal to zero.
-CDD_PWM_CC_CMP_LOAD_MODE_CNT_EQ_PRD: Load on CTR = PRD: Time-base counter equal to period.
-CDD_PWM_CC_CMP_LOAD_MODE_CNT_EQ_ZERO_OR_PRD: Load on either CTR = 0 or CTR = PRD.
-CDD_PWM_CC_CMP_LOAD_MODE_NO_LOAD : Freeze (no loads possible).
4.6.9.1.26. Cdd_Pwm_DeadbandCfg¶
Cdd_Pwm_DeadbandCfg performs the configuration of the dead band sub-module. This API configures the input source, output mode, polarity, rising and falling edge delays.
Input Parameters : uint32 Channel, pCfg (pointer to Dead band Configuration)
Output Parameters : Std_ReturnType : E_OK or E_NOT_OK
CDD_PWM_DeadbandCfgType consists of :
-uint32 inputMode
-uint32 outputMode
-uint32 polaritySelect
-uint32 risingEdgeDelay
-uint32 fallingEdgeDelay
4.6.9.1.27. Cdd_Pwm_DeadbandBypass¶
Cdd_Pwm_DeadbandBypass bypasses the Dead-band sub-module.
Input Parameters : uint32 Channel
Output Parameters : Std_ReturnType : E_OK or E_NOT_OK
4.6.9.1.28. Cdd_Pwm_ChopperCfg¶
Cdd_Pwm_ChopperCfg performs the configuration of the chopper sub-module. This API configures chopping clock duty cycle, chopping clock frequency and pulse width of first pulse of chopping clock.
Input Parameters : uint32 Channel, CDD_PWM_ChopperCfgType pCfg - pointer to Chopper Cfg
Output Parameters : Std_ReturnType : E_OK or E_NOT_OK
CDD_PWM_ChopperCfgType consists of :
-uint32 dutyCycle
-uint32 clkFrequency
-uint32 polaritySelect
-uint32 oneShotPulseWidth
4.6.9.1.29. Cdd_Pwm_ChopperEnable¶
Cdd_Pwm_ChopperEnable controls the enabling or disabling of chopper sub-module.
Input Parameters : uint32 Channel, uint32 enableChopper(TRUE - Enable chopper, FALSE - Disable chopper)
Output Parameters : Std_ReturnType : E_OK or E_NOT_OK
4.6.9.1.30. Cdd_Pwm_TzTripEventEnable¶
Cdd_Pwm_TzTripEventEnable enables the trip event.
Input Parameters : uint32 Channel, uint32 tzEventType
Output Parameters : Std_ReturnType : E_OK or E_NOT_OK
tzEventType can have following values:
CDD_PWM_TZ_EVENT_ONE_SHOT: One shot trip zone event,
CDD_PWM_TZ_EVENT_CYCLE_BY_CYCLE: Cycle by cycle trip zone event,
CDD_PWM_TZ_INTERRUPT_DCAEVT1,
CDD_PWM_TZ_INTERRUPT_DCAEVT2,
CDD_PWM_TZ_INTERRUPT_DCBEVT1,
CDD_PWM_TZ_INTERRUPT_DCBEVT2
4.6.9.1.31. Cdd_Pwm_TzTripEventDisable¶
Cdd_Pwm_TzTripEventDisable disables the trip event.
Input Parameters : uint32 Channel, uint32 tzEventType
Output Parameters : Std_ReturnType : E_OK or E_NOT_OK
tzEventType can have following values:
CDD_PWM_TZ_EVENT_ONE_SHOT: One shot trip zone event,
CDD_PWM_TZ_EVENT_CYCLE_BY_CYCLE: Cycle by cycle trip zone event,
CDD_PWM_TZ_INTERRUPT_DCAEVT1,
CDD_PWM_TZ_INTERRUPT_DCAEVT2,
CDD_PWM_TZ_INTERRUPT_DCBEVT1,
CDD_PWM_TZ_INTERRUPT_DCBEVT2
4.6.9.1.32. Cdd_Pwm_TzIntrEnable¶
Cdd_Pwm_TzIntrEnable enables the trip interrupt. When trip event occurs, the sub-module can be configured to interrupt CPU
Input Parameters : uint32 Channel, uint32 tzEventType
Output Parameters : Std_ReturnType : E_OK or E_NOT_OK
tzEventType can have following values:
CDD_PWM_TZ_EVENT_ONE_SHOT: One shot trip zone event,
CDD_PWM_TZ_EVENT_CYCLE_BY_CYCLE: Cycle by cycle trip zone event,
CDD_PWM_TZ_INTERRUPT_DCAEVT1,
CDD_PWM_TZ_INTERRUPT_DCAEVT2,
CDD_PWM_TZ_INTERRUPT_DCBEVT1,
CDD_PWM_TZ_INTERRUPT_DCBEVT2
4.6.9.1.33. Cdd_Pwm_TzIntrDisable¶
Cdd_Pwm_TzIntrEnable disables the trip interrupt.
Input Parameters : uint32 Channel, uint32 tzEventType
Output Parameters : Std_ReturnType : E_OK or E_NOT_OK
tzEventType can have following values:
CDD_PWM_TZ_EVENT_ONE_SHOT: One shot trip zone event,
CDD_PWM_TZ_EVENT_CYCLE_BY_CYCLE: Cycle by cycle trip zone event,
CDD_PWM_TZ_INTERRUPT_DCAEVT1,
CDD_PWM_TZ_INTERRUPT_DCAEVT2,
CDD_PWM_TZ_INTERRUPT_DCBEVT1,
CDD_PWM_TZ_INTERRUPT_DCBEVT2
4.6.9.1.34. Cdd_Pwm_TzGetEventStatus¶
Cdd_Pwm_tzGetEventStatus returns the selected trip zone event status.
Input Parameters : uint32 Channel, uint32 eventMask
Output Parameters : boolean
eventMask can have following values:
CDD_PWM_TZ_STS_FLG_OST: Latched Status Flag for A One-Shot Trip Event,
CDD_PWM_TZ_STS_FLG_CBC : Latched Status Flag for Cycle-By-Cycle Trip Event ,
CDD_PWM_TZ_STS_FLG_INT: Latched status for Trip Interrupt
4.6.9.1.35. Cdd_Pwm_TzEventStatusClear¶
Cdd_Pwm_TzEventStatusClear clears the selected trip zone event status.
Input Parameters : uint32 Channel, uint32 eventMask, uint32 tzFlags
Output Parameters : boolean
eventMask can have following values:
CDD_PWM_TZ_STS_FLG_OST: Latched Status Flag for A One-Shot Trip Event,
CDD_PWM_TZ_STS_FLG_CBC : Latched Status Flag for Cycle-By-Cycle Trip Event ,
CDD_PWM_TZ_STS_FLG_INT: Latched status for Trip Interrupt
4.6.9.2. API’s with Service ID¶
The following table presents the service IDs and the related services:
Service ID |
Service |
|---|---|
0x0U |
Cdd_Pwm_Init |
0x1U |
Cdd_Pwm_DeInit |
0x2U |
Cdd_Pwm_StartChannelCounter |
0x3U |
Cdd_Pwm_StopChannelCounter |
0x5U |
Cdd_Pwm_SetPinAction |
0x6U |
Cdd_Pwm_GetCounter |
0x8U |
Cdd_Pwm_SetRelativeThreshold |
0x4U |
Cdd_Pwm_GetCounterStatus |
0x15U |
Cdd_Pwm_ClearCounterStatus |
0x2CU |
Cdd_Pwm_CounterComparatorCfg |
0x09U |
Cdd_Pwm_DisableNotification |
0x0AU |
Cdd_Pwm_EnableNotification |
0x16U |
Cdd_Pwm_EtIntrStatus |
0x17U |
Cdd_Pwm_EtIntrClear |
0x18U |
Cdd_Pwm_EtGetEventCount |
0x19U |
Cdd_Pwm_SetAdcTrigger |
0x1BU |
Cdd_Pwm_TzTripEventEnable |
0x1CU |
Cdd_Pwm_TzTripEventDisable |
0x1DU |
Cdd_Pwm_TzIntrEnable |
0x1EU |
Cdd_Pwm_TzIntrDisable |
0x1FU |
Cdd_Pwm_TzGetEventStatus |
0x20U |
Cdd_Pwm_TzEventStatusClear |
0xEU |
Cdd_Pwm_SetPeriodDutyPhase |
0xFU |
Cdd_Pwm_SetOutputToIdle |
0x2AU |
Cdd_Pwm_SyncEnable |
0x2BU |
Cdd_Pwm_SyncDisable |
0x10U |
Cdd_Pwm_DeadbandCfg |
0x11U |
Cdd_Pwm_DeadbandBypass |
0x12U |
Cdd_Pwm_ChopperCfg |
0x13U |
Cdd_Pwm_ChopperEnable |
0xDU |
Cdd_Pwm_RegisterReadback |
0xBU |
Cdd_Pwm_GetVersionInfo |
0x21U |
Cdd_Pwm_HrSetPeriodDutyPhase |
0x22U |
Cdd_Pwm_HrSfoCalibration |
0x23U |
Cdd_Pwm_HrSfoStatus |
4.6.10. Configuration Description¶
4.6.10.1. Configuration Variants¶
The PWM is configured through GUI in Post-Build and Pre-Compile Variants.
Variants |
Configured Files |
|---|---|
PostBuild |
Cdd_Pwm_PBcfg.c, Cdd_Pwm_Cfg.c, Cdd_Pwm_Cfg.h |
Pre-Compile |
Cdd_Pwm_Cfg.c, Cdd_Pwm_Cfg.h |
4.6.10.2. Parameter Description¶
4.6.10.2.1. Standard Configuration¶
Will be updated in future release
4.6.10.2.2. IP Specific Configuration¶
Will be updated in future release
4.6.10.3. Symbolic Names deviations¶
None
4.6.10.4. Configuration rules and constraints to enable plausibility checks¶
Will be updated in future release
4.6.11. Memory Mapping¶
Will be updated in future release
4.6.12. Memory footprint¶
Please refer Memory Footprint for more details.
4.6.13. Performance¶
Will be updated in future release
4.6.14. Example Usage¶
Cdd_Pwm example applications demonstrating the MCAL CDD PWM driver features is in folder <MCAL_ROOT>/examples/Epwm.
These application can be built from the build folder by giving :
“gmake -s epwm_app PLATFORM= am263”
“gmake -s epwm_app_tz PLATFORM= am263”
4.6.14.1. CDD PWM Signal verification Application¶
Module is tested in AM263-CC board.
Oscilloscope is used to monitor CDD PWM dutycycle and frequency Variation
The CDD PWM module example is configured with channel ID 0 and 1 , which is mapped to physical channel EPWM0 and EPWM1
Connect EPWM output pin of 0 and 1st channel to Oscilloscope and check the output in CRO
Example code is tested for:
Frequency and DutyCycle Variation.
PWM Interrupt Verification.
PWM module triggering ADC module.
4.6.14.2. Trip- Zone Application¶
Trip Zone Signal is tested on GPIO 122 Pin.
4.6.14.3. Example Logs CDD PWM Signal¶
CDD_PWM_APP: Sample Application - STARTS !!!
CDD PWM MCAL Version Info
---------------------
Vendor ID : 44
Module ID : 255
SW Major Version : 9
SW Minor Version : 1
SW Patch Version : 0
PWM Signal is generated with default configured parameters.
PWM Signal is generated with below parameters on Channel A and B Pins.
: PERIOD 2500 : FREQUENCY 10000 : DUTYCYCLE in percentage 75 : DUTYCYCLE in Count 49152 :
PWM Signal is generated with below parameters on Channel A.
: PERIOD 5000 : FREQUENCY 5000 : DUTYCYCLE in percentage 50 : DUTYCYCLE in Count 32768 :
PWM Signal is generated with below parameters on Channel B.
: PERIOD 5000 : FREQUENCY 5000 : DUTYCYCLE in percentage 25 : DUTYCYCLE in Count 16384 :
ADC Test Application In Progress.
ADC Test Application Passed.
Edge Interrupt is enable.
Wait till interrupt is recived.
Interrupts Recieved are : 40480
CDD_PWM_APP: Sample Application - DONE !!!
CDD Stack Usage: 960 bytes
All tests have passed
4.6.14.4. Tripzone Application Testing¶
CDD_PWM_APP: Sample Application - STARTS !!!
CDD PWM MCAL Version Info
---------------------
Vendor ID : 44
Module ID : 255
SW Major Version : 9
SW Minor Version : 1
SW Patch Version : 0
Keep the GPIO 122 to High State.
PWM Signal is generated with default configured parameters.
Wait for sometime and Change the GPIO 122 to Low State from High State.
Trip zone signal occurred
new GPIO122 state : 1
PWM Signal is generated with below parameters on Channel A and B Pins.
: PERIOD 2500 : FREQUENCY 10000 : DUTYCYCLE in percentage 75 : DUTYCYCLE in Count 49152 :
Wait for sometime and Change the GPIO 122 to Low State from High State.
Trip zone signal occurred
PWM Signal is generated with below parameters on Channel A and B Pins.
: PERIOD 25000 : FREQUENCY 1000 : DUTYCYCLE in percentage 50 : DUTYCYCLE in Count 32768 :
CDD_PWM_APP: Sample Application - DONE !!!
CDD Stack Usage: 792 bytes
All tests have passed
4.6.15. FAQ’s¶
Will be updated in future release
4.6.16. Test Report(Link to test report)¶
Will be updated in future release
4.6.17. References¶
4.6.18. TI Disclaimer¶
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