AM65x MCU+ SDK  09.01.00
tisci_clocks.h File Reference

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Macros

#define TISCI_DEV_DCC4_BUS_DCC_INPUT00_CLK   0
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#define TISCI_DEV_DCC4_BUS_DCC_CLKSRC7_CLK   1
 
#define TISCI_DEV_DCC4_BUS_DCC_CLKSRC4_CLK   2
 
#define TISCI_DEV_DCC4_BUS_DCC_CLKSRC3_CLK   3
 
#define TISCI_DEV_DCC4_BUS_VBUS_CLK   4
 
#define TISCI_DEV_DCC4_BUS_DCC_INPUT01_CLK   5
 
#define TISCI_DEV_DCC4_BUS_DCC_CLKSRC5_CLK   6
 
#define TISCI_DEV_DCC4_BUS_DCC_INPUT02_CLK   7
 
#define TISCI_DEV_DCC4_BUS_DCC_CLKSRC0_CLK   8
 
#define TISCI_DEV_DCC4_BUS_DCC_CLKSRC6_CLK   9
 
#define TISCI_DEV_DCC4_BUS_DCC_INPUT10_CLK   10
 
#define TISCI_DEV_DCC4_BUS_DCC_CLKSRC2_CLK   11
 
#define TISCI_DEV_DCC6_BUS_DCC_INPUT00_CLK   0
 
#define TISCI_DEV_DCC6_BUS_DCC_CLKSRC7_CLK   1
 
#define TISCI_DEV_DCC6_BUS_DCC_CLKSRC4_CLK   2
 
#define TISCI_DEV_DCC6_BUS_DCC_CLKSRC3_CLK   3
 
#define TISCI_DEV_DCC6_BUS_VBUS_CLK   4
 
#define TISCI_DEV_DCC6_BUS_DCC_CLKSRC1_CLK   5
 
#define TISCI_DEV_DCC6_BUS_DCC_INPUT01_CLK   6
 
#define TISCI_DEV_DCC6_BUS_DCC_CLKSRC5_CLK   7
 
#define TISCI_DEV_DCC6_BUS_DCC_INPUT02_CLK   8
 
#define TISCI_DEV_DCC6_BUS_DCC_CLKSRC0_CLK   9
 
#define TISCI_DEV_DCC6_BUS_DCC_CLKSRC6_CLK   10
 
#define TISCI_DEV_DCC6_BUS_DCC_INPUT10_CLK   11
 
#define TISCI_DEV_DCC6_BUS_DCC_CLKSRC2_CLK   12
 
#define TISCI_DEV_DCC0_BUS_DCC_INPUT00_CLK   0
 
#define TISCI_DEV_DCC0_BUS_DCC_CLKSRC4_CLK   1
 
#define TISCI_DEV_DCC0_BUS_DCC_CLKSRC3_CLK   2
 
#define TISCI_DEV_DCC0_BUS_VBUS_CLK   3
 
#define TISCI_DEV_DCC0_BUS_DCC_CLKSRC1_CLK   4
 
#define TISCI_DEV_DCC0_BUS_DCC_INPUT01_CLK   5
 
#define TISCI_DEV_DCC0_BUS_DCC_CLKSRC5_CLK   6
 
#define TISCI_DEV_DCC0_BUS_DCC_INPUT02_CLK   7
 
#define TISCI_DEV_DCC0_BUS_DCC_CLKSRC0_CLK   8
 
#define TISCI_DEV_DCC0_BUS_DCC_CLKSRC6_CLK   9
 
#define TISCI_DEV_DCC0_BUS_DCC_INPUT10_CLK   10
 
#define TISCI_DEV_DCC0_BUS_DCC_CLKSRC2_CLK   11
 
#define TISCI_DEV_MCU_DCC2_BUS_DCC_INPUT00_CLK   0
 
#define TISCI_DEV_MCU_DCC2_BUS_DCC_CLKSRC7_CLK   1
 
#define TISCI_DEV_MCU_DCC2_BUS_DCC_CLKSRC4_CLK   2
 
#define TISCI_DEV_MCU_DCC2_BUS_DCC_CLKSRC3_CLK   3
 
#define TISCI_DEV_MCU_DCC2_BUS_VBUS_CLK   4
 
#define TISCI_DEV_MCU_DCC2_BUS_DCC_CLKSRC1_CLK   5
 
#define TISCI_DEV_MCU_DCC2_BUS_DCC_INPUT01_CLK   6
 
#define TISCI_DEV_MCU_DCC2_BUS_DCC_CLKSRC5_CLK   7
 
#define TISCI_DEV_MCU_DCC2_BUS_DCC_INPUT02_CLK   8
 
#define TISCI_DEV_MCU_DCC2_BUS_DCC_CLKSRC0_CLK   9
 
#define TISCI_DEV_MCU_DCC2_BUS_DCC_CLKSRC6_CLK   10
 
#define TISCI_DEV_MCU_DCC2_BUS_DCC_INPUT10_CLK   11
 
#define TISCI_DEV_MCU_DCC2_BUS_DCC_CLKSRC2_CLK   12
 
#define TISCI_DEV_DCC5_BUS_DCC_INPUT00_CLK   0
 
#define TISCI_DEV_DCC5_BUS_DCC_CLKSRC7_CLK   1
 
#define TISCI_DEV_DCC5_BUS_DCC_CLKSRC4_CLK   2
 
#define TISCI_DEV_DCC5_BUS_DCC_CLKSRC3_CLK   3
 
#define TISCI_DEV_DCC5_BUS_VBUS_CLK   4
 
#define TISCI_DEV_DCC5_BUS_DCC_CLKSRC1_CLK   5
 
#define TISCI_DEV_DCC5_BUS_DCC_INPUT01_CLK   6
 
#define TISCI_DEV_DCC5_BUS_DCC_CLKSRC5_CLK   7
 
#define TISCI_DEV_DCC5_BUS_DCC_INPUT02_CLK   8
 
#define TISCI_DEV_DCC5_BUS_DCC_CLKSRC0_CLK   9
 
#define TISCI_DEV_DCC5_BUS_DCC_CLKSRC6_CLK   10
 
#define TISCI_DEV_DCC5_BUS_DCC_INPUT10_CLK   11
 
#define TISCI_DEV_DCC5_BUS_DCC_CLKSRC2_CLK   12
 
#define TISCI_DEV_MCU_DCC0_BUS_DCC_INPUT00_CLK   0
 
#define TISCI_DEV_MCU_DCC0_BUS_DCC_CLKSRC7_CLK   1
 
#define TISCI_DEV_MCU_DCC0_BUS_DCC_CLKSRC4_CLK   2
 
#define TISCI_DEV_MCU_DCC0_BUS_DCC_CLKSRC3_CLK   3
 
#define TISCI_DEV_MCU_DCC0_BUS_VBUS_CLK   4
 
#define TISCI_DEV_MCU_DCC0_BUS_DCC_CLKSRC1_CLK   5
 
#define TISCI_DEV_MCU_DCC0_BUS_DCC_INPUT01_CLK   6
 
#define TISCI_DEV_MCU_DCC0_BUS_DCC_CLKSRC5_CLK   7
 
#define TISCI_DEV_MCU_DCC0_BUS_DCC_INPUT02_CLK   8
 
#define TISCI_DEV_MCU_DCC0_BUS_DCC_CLKSRC0_CLK   9
 
#define TISCI_DEV_MCU_DCC0_BUS_DCC_CLKSRC6_CLK   10
 
#define TISCI_DEV_MCU_DCC0_BUS_DCC_INPUT10_CLK   11
 
#define TISCI_DEV_MCU_DCC0_BUS_DCC_CLKSRC2_CLK   12
 
#define TISCI_DEV_MCU_DCC1_BUS_DCC_INPUT00_CLK   0
 
#define TISCI_DEV_MCU_DCC1_BUS_DCC_CLKSRC7_CLK   1
 
#define TISCI_DEV_MCU_DCC1_BUS_DCC_CLKSRC4_CLK   2
 
#define TISCI_DEV_MCU_DCC1_BUS_DCC_CLKSRC3_CLK   3
 
#define TISCI_DEV_MCU_DCC1_BUS_VBUS_CLK   4
 
#define TISCI_DEV_MCU_DCC1_BUS_DCC_CLKSRC1_CLK   5
 
#define TISCI_DEV_MCU_DCC1_BUS_DCC_INPUT01_CLK   6
 
#define TISCI_DEV_MCU_DCC1_BUS_DCC_CLKSRC5_CLK   7
 
#define TISCI_DEV_MCU_DCC1_BUS_DCC_INPUT02_CLK   8
 
#define TISCI_DEV_MCU_DCC1_BUS_DCC_CLKSRC0_CLK   9
 
#define TISCI_DEV_MCU_DCC1_BUS_DCC_CLKSRC6_CLK   10
 
#define TISCI_DEV_MCU_DCC1_BUS_DCC_INPUT10_CLK   11
 
#define TISCI_DEV_MCU_DCC1_BUS_DCC_CLKSRC2_CLK   12
 
#define TISCI_DEV_DCC1_BUS_DCC_INPUT00_CLK   0
 
#define TISCI_DEV_DCC1_BUS_DCC_CLKSRC7_CLK   1
 
#define TISCI_DEV_DCC1_BUS_DCC_CLKSRC4_CLK   2
 
#define TISCI_DEV_DCC1_BUS_DCC_CLKSRC3_CLK   3
 
#define TISCI_DEV_DCC1_BUS_VBUS_CLK   4
 
#define TISCI_DEV_DCC1_BUS_DCC_CLKSRC1_CLK   5
 
#define TISCI_DEV_DCC1_BUS_DCC_INPUT01_CLK   6
 
#define TISCI_DEV_DCC1_BUS_DCC_CLKSRC5_CLK   7
 
#define TISCI_DEV_DCC1_BUS_DCC_INPUT02_CLK   8
 
#define TISCI_DEV_DCC1_BUS_DCC_CLKSRC0_CLK   9
 
#define TISCI_DEV_DCC1_BUS_DCC_CLKSRC6_CLK   10
 
#define TISCI_DEV_DCC1_BUS_DCC_INPUT10_CLK   11
 
#define TISCI_DEV_DCC1_BUS_DCC_CLKSRC2_CLK   12
 
#define TISCI_DEV_DCC3_BUS_DCC_INPUT00_CLK   0
 
#define TISCI_DEV_DCC3_BUS_DCC_CLKSRC7_CLK   1
 
#define TISCI_DEV_DCC3_BUS_DCC_CLKSRC4_CLK   2
 
#define TISCI_DEV_DCC3_BUS_DCC_CLKSRC3_CLK   3
 
#define TISCI_DEV_DCC3_BUS_VBUS_CLK   4
 
#define TISCI_DEV_DCC3_BUS_DCC_CLKSRC1_CLK   5
 
#define TISCI_DEV_DCC3_BUS_DCC_INPUT01_CLK   6
 
#define TISCI_DEV_DCC3_BUS_DCC_CLKSRC5_CLK   7
 
#define TISCI_DEV_DCC3_BUS_DCC_INPUT02_CLK   8
 
#define TISCI_DEV_DCC3_BUS_DCC_CLKSRC0_CLK   9
 
#define TISCI_DEV_DCC3_BUS_DCC_INPUT10_CLK   10
 
#define TISCI_DEV_DCC3_BUS_DCC_CLKSRC2_CLK   11
 
#define TISCI_DEV_DCC7_BUS_DCC_INPUT00_CLK   0
 
#define TISCI_DEV_DCC7_BUS_DCC_CLKSRC7_CLK   1
 
#define TISCI_DEV_DCC7_BUS_DCC_CLKSRC4_CLK   2
 
#define TISCI_DEV_DCC7_BUS_DCC_CLKSRC3_CLK   3
 
#define TISCI_DEV_DCC7_BUS_VBUS_CLK   4
 
#define TISCI_DEV_DCC7_BUS_DCC_CLKSRC1_CLK   5
 
#define TISCI_DEV_DCC7_BUS_DCC_INPUT01_CLK   6
 
#define TISCI_DEV_DCC7_BUS_DCC_CLKSRC5_CLK   7
 
#define TISCI_DEV_DCC7_BUS_DCC_INPUT02_CLK   8
 
#define TISCI_DEV_DCC7_BUS_DCC_CLKSRC0_CLK   9
 
#define TISCI_DEV_DCC7_BUS_DCC_CLKSRC6_CLK   10
 
#define TISCI_DEV_DCC7_BUS_DCC_INPUT10_CLK   11
 
#define TISCI_DEV_DCC7_BUS_DCC_CLKSRC2_CLK   12
 
#define TISCI_DEV_DCC2_BUS_DCC_INPUT00_CLK   0
 
#define TISCI_DEV_DCC2_BUS_DCC_CLKSRC7_CLK   1
 
#define TISCI_DEV_DCC2_BUS_DCC_CLKSRC4_CLK   2
 
#define TISCI_DEV_DCC2_BUS_DCC_CLKSRC3_CLK   3
 
#define TISCI_DEV_DCC2_BUS_VBUS_CLK   4
 
#define TISCI_DEV_DCC2_BUS_DCC_CLKSRC1_CLK   5
 
#define TISCI_DEV_DCC2_BUS_DCC_INPUT01_CLK   6
 
#define TISCI_DEV_DCC2_BUS_DCC_CLKSRC5_CLK   7
 
#define TISCI_DEV_DCC2_BUS_DCC_INPUT02_CLK   8
 
#define TISCI_DEV_DCC2_BUS_DCC_CLKSRC0_CLK   9
 
#define TISCI_DEV_DCC2_BUS_DCC_CLKSRC6_CLK   10
 
#define TISCI_DEV_DCC2_BUS_DCC_INPUT10_CLK   11
 
#define TISCI_DEV_DCC2_BUS_DCC_CLKSRC2_CLK   12
 
#define TISCI_DEV_MCU_I2C0_BUS_CLK   0
 
#define TISCI_DEV_MCU_I2C0_BUS_PISYS_CLK   1
 
#define TISCI_DEV_MCU_I2C0_BUS_PISCL   2
 
#define TISCI_DEV_I2C3_BUS_CLK   0
 
#define TISCI_DEV_I2C3_BUS_PISYS_CLK   1
 
#define TISCI_DEV_I2C3_BUS_PISCL   2
 
#define TISCI_DEV_I2C2_BUS_CLK   0
 
#define TISCI_DEV_I2C2_BUS_PISYS_CLK   1
 
#define TISCI_DEV_I2C2_BUS_PISCL   2
 
#define TISCI_DEV_WKUP_I2C0_BUS_CLK   0
 
#define TISCI_DEV_WKUP_I2C0_BUS_PISYS_CLK   1
 
#define TISCI_DEV_WKUP_I2C0_BUS_PISYS_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK   2
 
#define TISCI_DEV_WKUP_I2C0_BUS_PISYS_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   3
 
#define TISCI_DEV_WKUP_I2C0_BUS_PISCL   4
 
#define TISCI_DEV_I2C0_BUS_CLK   0
 
#define TISCI_DEV_I2C0_BUS_PISYS_CLK   1
 
#define TISCI_DEV_I2C0_BUS_PISCL   2
 
#define TISCI_DEV_I2C1_BUS_CLK   0
 
#define TISCI_DEV_I2C1_BUS_PISYS_CLK   1
 
#define TISCI_DEV_I2C1_BUS_PISCL   2
 
#define TISCI_DEV_TIMER5_BUS_TIMER_TCLK_CLK   0
 
#define TISCI_DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   1
 
#define TISCI_DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT   2
 
#define TISCI_DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK   3
 
#define TISCI_DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK   4
 
#define TISCI_DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK   5
 
#define TISCI_DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT   6
 
#define TISCI_DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT   7
 
#define TISCI_DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT   8
 
#define TISCI_DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT   9
 
#define TISCI_DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK   10
 
#define TISCI_DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5   11
 
#define TISCI_DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK   12
 
#define TISCI_DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0   13
 
#define TISCI_DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0   14
 
#define TISCI_DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0   15
 
#define TISCI_DEV_TIMER5_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0   16
 
#define TISCI_DEV_TIMER5_BUS_TIMER_HCLK_CLK   17
 
#define TISCI_DEV_TIMER6_BUS_TIMER_TCLK_CLK   0
 
#define TISCI_DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   1
 
#define TISCI_DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT   2
 
#define TISCI_DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK   3
 
#define TISCI_DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK   4
 
#define TISCI_DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK   5
 
#define TISCI_DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT   6
 
#define TISCI_DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT   7
 
#define TISCI_DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT   8
 
#define TISCI_DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT   9
 
#define TISCI_DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK   10
 
#define TISCI_DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5   11
 
#define TISCI_DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK   12
 
#define TISCI_DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0   13
 
#define TISCI_DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0   14
 
#define TISCI_DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0   15
 
#define TISCI_DEV_TIMER6_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0   16
 
#define TISCI_DEV_TIMER6_BUS_TIMER_HCLK_CLK   17
 
#define TISCI_DEV_TIMER7_BUS_TIMER_TCLK_CLK   0
 
#define TISCI_DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   1
 
#define TISCI_DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT   2
 
#define TISCI_DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK   3
 
#define TISCI_DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK   4
 
#define TISCI_DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK   5
 
#define TISCI_DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT   6
 
#define TISCI_DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT   7
 
#define TISCI_DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT   8
 
#define TISCI_DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT   9
 
#define TISCI_DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK   10
 
#define TISCI_DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5   11
 
#define TISCI_DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK   12
 
#define TISCI_DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0   13
 
#define TISCI_DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0   14
 
#define TISCI_DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0   15
 
#define TISCI_DEV_TIMER7_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0   16
 
#define TISCI_DEV_TIMER7_BUS_TIMER_HCLK_CLK   17
 
#define TISCI_DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK   0
 
#define TISCI_DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   1
 
#define TISCI_DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2   2
 
#define TISCI_DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK   3
 
#define TISCI_DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK   4
 
#define TISCI_DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT   5
 
#define TISCI_DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT   6
 
#define TISCI_DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_BUS_CPTS_GENF0_0   7
 
#define TISCI_DEV_MCU_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK   8
 
#define TISCI_DEV_MCU_TIMER0_BUS_TIMER_HCLK_CLK   9
 
#define TISCI_DEV_TIMER8_BUS_TIMER_TCLK_CLK   0
 
#define TISCI_DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   1
 
#define TISCI_DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT   2
 
#define TISCI_DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK   3
 
#define TISCI_DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK   4
 
#define TISCI_DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK   5
 
#define TISCI_DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT   6
 
#define TISCI_DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT   7
 
#define TISCI_DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT   8
 
#define TISCI_DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT   9
 
#define TISCI_DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK   10
 
#define TISCI_DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5   11
 
#define TISCI_DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK   12
 
#define TISCI_DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0   13
 
#define TISCI_DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0   14
 
#define TISCI_DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0   15
 
#define TISCI_DEV_TIMER8_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0   16
 
#define TISCI_DEV_TIMER8_BUS_TIMER_HCLK_CLK   17
 
#define TISCI_DEV_TIMER2_BUS_TIMER_TCLK_CLK   0
 
#define TISCI_DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   1
 
#define TISCI_DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT   2
 
#define TISCI_DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK   3
 
#define TISCI_DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK   4
 
#define TISCI_DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK   5
 
#define TISCI_DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT   6
 
#define TISCI_DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT   7
 
#define TISCI_DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT   8
 
#define TISCI_DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT   9
 
#define TISCI_DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK   10
 
#define TISCI_DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5   11
 
#define TISCI_DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK   12
 
#define TISCI_DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0   13
 
#define TISCI_DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0   14
 
#define TISCI_DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0   15
 
#define TISCI_DEV_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0   16
 
#define TISCI_DEV_TIMER2_BUS_TIMER_HCLK_CLK   17
 
#define TISCI_DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK   0
 
#define TISCI_DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   1
 
#define TISCI_DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2   2
 
#define TISCI_DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK   3
 
#define TISCI_DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK   4
 
#define TISCI_DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT   5
 
#define TISCI_DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT   6
 
#define TISCI_DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_BUS_CPTS_GENF0_0   7
 
#define TISCI_DEV_MCU_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK   8
 
#define TISCI_DEV_MCU_TIMER1_BUS_TIMER_HCLK_CLK   9
 
#define TISCI_DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK   0
 
#define TISCI_DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   1
 
#define TISCI_DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2   2
 
#define TISCI_DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK   3
 
#define TISCI_DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK   4
 
#define TISCI_DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT   5
 
#define TISCI_DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT   6
 
#define TISCI_DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_BUS_CPTS_GENF0_0   7
 
#define TISCI_DEV_MCU_TIMER2_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK   8
 
#define TISCI_DEV_MCU_TIMER2_BUS_TIMER_HCLK_CLK   9
 
#define TISCI_DEV_TIMER4_BUS_TIMER_TCLK_CLK   0
 
#define TISCI_DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   1
 
#define TISCI_DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT   2
 
#define TISCI_DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK   3
 
#define TISCI_DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK   4
 
#define TISCI_DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK   5
 
#define TISCI_DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT   6
 
#define TISCI_DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT   7
 
#define TISCI_DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT   8
 
#define TISCI_DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT   9
 
#define TISCI_DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK   10
 
#define TISCI_DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5   11
 
#define TISCI_DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK   12
 
#define TISCI_DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0   13
 
#define TISCI_DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0   14
 
#define TISCI_DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0   15
 
#define TISCI_DEV_TIMER4_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0   16
 
#define TISCI_DEV_TIMER4_BUS_TIMER_HCLK_CLK   17
 
#define TISCI_DEV_TIMER3_BUS_TIMER_TCLK_CLK   0
 
#define TISCI_DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   1
 
#define TISCI_DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT   2
 
#define TISCI_DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK   3
 
#define TISCI_DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK   4
 
#define TISCI_DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK   5
 
#define TISCI_DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT   6
 
#define TISCI_DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT   7
 
#define TISCI_DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT   8
 
#define TISCI_DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT   9
 
#define TISCI_DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK   10
 
#define TISCI_DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5   11
 
#define TISCI_DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK   12
 
#define TISCI_DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0   13
 
#define TISCI_DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0   14
 
#define TISCI_DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0   15
 
#define TISCI_DEV_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0   16
 
#define TISCI_DEV_TIMER3_BUS_TIMER_HCLK_CLK   17
 
#define TISCI_DEV_TIMER9_BUS_TIMER_TCLK_CLK   0
 
#define TISCI_DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   1
 
#define TISCI_DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT   2
 
#define TISCI_DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK   3
 
#define TISCI_DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK   4
 
#define TISCI_DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK   5
 
#define TISCI_DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT   6
 
#define TISCI_DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT   7
 
#define TISCI_DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT   8
 
#define TISCI_DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT   9
 
#define TISCI_DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK   10
 
#define TISCI_DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5   11
 
#define TISCI_DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK   12
 
#define TISCI_DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0   13
 
#define TISCI_DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0   14
 
#define TISCI_DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0   15
 
#define TISCI_DEV_TIMER9_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0   16
 
#define TISCI_DEV_TIMER9_BUS_TIMER_HCLK_CLK   17
 
#define TISCI_DEV_TIMER11_BUS_TIMER_TCLK_CLK   0
 
#define TISCI_DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   1
 
#define TISCI_DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT   2
 
#define TISCI_DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK   3
 
#define TISCI_DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK   4
 
#define TISCI_DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK   5
 
#define TISCI_DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT   6
 
#define TISCI_DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT   7
 
#define TISCI_DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT   8
 
#define TISCI_DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT   9
 
#define TISCI_DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK   10
 
#define TISCI_DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5   11
 
#define TISCI_DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK   12
 
#define TISCI_DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0   13
 
#define TISCI_DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0   14
 
#define TISCI_DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0   15
 
#define TISCI_DEV_TIMER11_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0   16
 
#define TISCI_DEV_TIMER11_BUS_TIMER_HCLK_CLK   17
 
#define TISCI_DEV_TIMER10_BUS_TIMER_TCLK_CLK   0
 
#define TISCI_DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   1
 
#define TISCI_DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT   2
 
#define TISCI_DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK   3
 
#define TISCI_DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK   4
 
#define TISCI_DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK   5
 
#define TISCI_DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT   6
 
#define TISCI_DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT   7
 
#define TISCI_DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT   8
 
#define TISCI_DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT   9
 
#define TISCI_DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK   10
 
#define TISCI_DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5   11
 
#define TISCI_DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK   12
 
#define TISCI_DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0   13
 
#define TISCI_DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0   14
 
#define TISCI_DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0   15
 
#define TISCI_DEV_TIMER10_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0   16
 
#define TISCI_DEV_TIMER10_BUS_TIMER_HCLK_CLK   17
 
#define TISCI_DEV_TIMER0_BUS_TIMER_TCLK_CLK   0
 
#define TISCI_DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   1
 
#define TISCI_DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT   2
 
#define TISCI_DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK   3
 
#define TISCI_DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK   4
 
#define TISCI_DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK   5
 
#define TISCI_DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT   6
 
#define TISCI_DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT   7
 
#define TISCI_DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT   8
 
#define TISCI_DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT   9
 
#define TISCI_DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK   10
 
#define TISCI_DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5   11
 
#define TISCI_DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK   12
 
#define TISCI_DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0   13
 
#define TISCI_DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0   14
 
#define TISCI_DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0   15
 
#define TISCI_DEV_TIMER0_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0   16
 
#define TISCI_DEV_TIMER0_BUS_TIMER_HCLK_CLK   17
 
#define TISCI_DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK   0
 
#define TISCI_DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   1
 
#define TISCI_DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2   2
 
#define TISCI_DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK   3
 
#define TISCI_DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK   4
 
#define TISCI_DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT   5
 
#define TISCI_DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT   6
 
#define TISCI_DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_BUS_CPTS_GENF0_0   7
 
#define TISCI_DEV_MCU_TIMER3_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK   8
 
#define TISCI_DEV_MCU_TIMER3_BUS_TIMER_HCLK_CLK   9
 
#define TISCI_DEV_TIMER1_BUS_TIMER_TCLK_CLK   0
 
#define TISCI_DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   1
 
#define TISCI_DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT   2
 
#define TISCI_DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK   3
 
#define TISCI_DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK   4
 
#define TISCI_DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK   5
 
#define TISCI_DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT   6
 
#define TISCI_DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT   7
 
#define TISCI_DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT   8
 
#define TISCI_DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT   9
 
#define TISCI_DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK   10
 
#define TISCI_DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5   11
 
#define TISCI_DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK   12
 
#define TISCI_DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0   13
 
#define TISCI_DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0   14
 
#define TISCI_DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0   15
 
#define TISCI_DEV_TIMER1_BUS_TIMER_TCLK_CLK_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0   16
 
#define TISCI_DEV_TIMER1_BUS_TIMER_HCLK_CLK   17
 
#define TISCI_DEV_WKUP_PSC0_BUS_CLK   0
 
#define TISCI_DEV_WKUP_PSC0_BUS_SLOW_CLK   1
 
#define TISCI_DEV_CBASS0_BUS_MAIN_SYSCLK0_2_CLK   0
 
#define TISCI_DEV_CBASS0_BUS_MAIN_SYSCLK0_4_CLK   1
 
#define TISCI_DEV_PLL_MMR0_BUS_VBUSP_CLK   0
 
#define TISCI_DEV_MCU_CPT2_AGGR0_BUS_VCLK_CLK   0
 
#define TISCI_DEV_CPT2_AGGR0_BUS_VCLK_CLK   0
 
#define TISCI_DEV_DEBUGSS0_BUS_ATB1_CLK   0
 
#define TISCI_DEV_DEBUGSS0_BUS_ATB5_CLK   1
 
#define TISCI_DEV_DEBUGSS0_BUS_ATB0_CLK   2
 
#define TISCI_DEV_DEBUGSS0_BUS_SYS_CLK   3
 
#define TISCI_DEV_DEBUGSS0_BUS_ATB4_CLK   4
 
#define TISCI_DEV_DEBUGSS0_BUS_CFG_CLK   5
 
#define TISCI_DEV_DEBUGSS0_BUS_ATB2_CLK   6
 
#define TISCI_DEV_DEBUGSS0_BUS_DBG_CLK   7
 
#define TISCI_DEV_DEBUGSS0_BUS_ATB3_CLK   8
 
#define TISCI_DEV_EHRPWM4_BUS_VBUSP_CLK   0
 
#define TISCI_DEV_EHRPWM1_BUS_VBUSP_CLK   0
 
#define TISCI_DEV_EHRPWM0_BUS_VBUSP_CLK   0
 
#define TISCI_DEV_EHRPWM3_BUS_VBUSP_CLK   0
 
#define TISCI_DEV_EHRPWM5_BUS_VBUSP_CLK   0
 
#define TISCI_DEV_EHRPWM2_BUS_VBUSP_CLK   0
 
#define TISCI_DEV_ELM0_BUS_VBUSP_CLK   0
 
#define TISCI_DEV_MCU_UART0_BUS_FCLK_CLK   0
 
#define TISCI_DEV_MCU_UART0_BUS_FCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK   1
 
#define TISCI_DEV_MCU_UART0_BUS_FCLK_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK5   2
 
#define TISCI_DEV_MCU_UART0_BUS_VBUSP_CLK   3
 
#define TISCI_DEV_WKUP_UART0_BUS_FCLK_CLK   0
 
#define TISCI_DEV_WKUP_UART0_BUS_FCLK_CLK_PARENT_CLOCKMUX_WKUPUSART_CLK_SEL_BUS_OUT0   1
 
#define TISCI_DEV_WKUP_UART0_BUS_FCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   2
 
#define TISCI_DEV_WKUP_UART0_BUS_VBUSP_CLK   3
 
#define TISCI_DEV_UART1_BUS_FCLK_CLK   0
 
#define TISCI_DEV_UART1_BUS_VBUSP_CLK   1
 
#define TISCI_DEV_UART0_BUS_FCLK_CLK   0
 
#define TISCI_DEV_UART0_BUS_VBUSP_CLK   1
 
#define TISCI_DEV_UART2_BUS_FCLK_CLK   0
 
#define TISCI_DEV_UART2_BUS_VBUSP_CLK   1
 
#define TISCI_DEV_SA2_UL0_BUS_PKA_IN_CLK   0
 
#define TISCI_DEV_SA2_UL0_BUS_X1_CLK   1
 
#define TISCI_DEV_SA2_UL0_BUS_X2_CLK   2
 
#define TISCI_DEV_CAL0_BUS_CLK   0
 
#define TISCI_DEV_CAL0_BUS_CP_C_CLK   1
 
#define TISCI_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4_BUS_VBUS_CLK   0
 
#define TISCI_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4_BUS_PROBE_CLK   1
 
#define TISCI_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3_BUS_VBUS_CLK   0
 
#define TISCI_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3_BUS_PROBE_CLK   1
 
#define TISCI_DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0_BUS_VBUS_CLK   0
 
#define TISCI_DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0_BUS_PROBE_CLK   1
 
#define TISCI_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3_BUS_VBUS_CLK   0
 
#define TISCI_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3_BUS_PROBE_CLK   1
 
#define TISCI_DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1_BUS_VBUS_CLK   0
 
#define TISCI_DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1_BUS_PROBE_CLK   1
 
#define TISCI_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5_BUS_VBUS_CLK   0
 
#define TISCI_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5_BUS_PROBE_CLK   1
 
#define TISCI_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6_BUS_VBUS_CLK   0
 
#define TISCI_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6_BUS_PROBE_CLK   1
 
#define TISCI_DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0_BUS_VBUS_CLK   0
 
#define TISCI_DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0_BUS_PROBE_CLK   1
 
#define TISCI_DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2_BUS_VBUS_CLK   0
 
#define TISCI_DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2_BUS_PROBE_CLK   1
 
#define TISCI_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2_BUS_VBUS_CLK   0
 
#define TISCI_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2_BUS_PROBE_CLK   1
 
#define TISCI_DEV_PBIST0_BUS_CLK1_CLK   0
 
#define TISCI_DEV_PBIST0_BUS_CLK4_CLK   1
 
#define TISCI_DEV_PBIST0_BUS_CLK2_CLK   2
 
#define TISCI_DEV_PBIST1_BUS_CLK1_CLK   0
 
#define TISCI_DEV_PBIST1_BUS_CLK4_CLK   1
 
#define TISCI_DEV_PBIST1_BUS_CLK2_CLK   2
 
#define TISCI_DEV_MCU_PBIST0_BUS_CLK1_CLK   0
 
#define TISCI_DEV_MCU_PBIST0_BUS_CLK4_CLK   1
 
#define TISCI_DEV_MCU_PBIST0_BUS_CLK2_CLK   2
 
#define TISCI_DEV_NAVSS0_BUS_UDMASS_VD2CLK   0
 
#define TISCI_DEV_NAVSS0_BUS_ICSS_G2CLK   1
 
#define TISCI_DEV_NAVSS0_BUS_ICSS_G0CLK   2
 
#define TISCI_DEV_NAVSS0_BUS_RCLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK_OUT   3
 
#define TISCI_DEV_NAVSS0_BUS_MSMC0CLK   4
 
#define TISCI_DEV_NAVSS0_BUS_RCLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK   5
 
#define TISCI_DEV_NAVSS0_BUS_RCLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT   6
 
#define TISCI_DEV_NAVSS0_BUS_MODSS_VD2CLK   7
 
#define TISCI_DEV_NAVSS0_BUS_RCLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT   8
 
#define TISCI_DEV_NAVSS0_BUS_PDMA_MAIN1CLK   9
 
#define TISCI_DEV_NAVSS0_BUS_NBSS_VCLK   10
 
#define TISCI_DEV_NAVSS0_BUS_RCLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK   11
 
#define TISCI_DEV_NAVSS0_BUS_NBSS_VD2CLK   12
 
#define TISCI_DEV_NAVSS0_BUS_ICSS_G1CLK   13
 
#define TISCI_DEV_NAVSS0_BUS_RCLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1_OUT   14
 
#define TISCI_DEV_NAVSS0_BUS_CPTS0_GENF4_0   15
 
#define TISCI_DEV_NAVSS0_BUS_CPTS0_GENF5_0   16
 
#define TISCI_DEV_NAVSS0_BUS_CPTS0_GENF2_0   17
 
#define TISCI_DEV_NAVSS0_BUS_CPTS0_GENF3_0   18
 
#define TISCI_DEV_DSS0_BUS_DPI_0_IN_CLK_BUS_IN1_CLOCKDIVIDER_DSS_BUS_OUT0   0
 
#define TISCI_DEV_DSS0_BUS_DSS_FUNC_CLK   1
 
#define TISCI_DEV_DSS0_BUS_DPI_1_IN_CLK   2
 
#define TISCI_DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_CLOCKDIVIDER_DSS_BUS_OUT07   3
 
#define TISCI_DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_BOARD_0_BUS_DSS0EXTPCLKIN_OUT   4
 
#define TISCI_DEV_DSS0_BUS_DPI_1_IN_CLK_PARENT_CLOCKDIVIDER_DSS_BUS_OUT1   5
 
#define TISCI_DEV_DSS0_BUS_DPI_0_IN_CLK_BUS_IN0_CLOCKDIVIDER_DSS_BUS_OUT0   6
 
#define TISCI_DEV_DSS0_BUS_DPI_1_OUT_CLK   7
 
#define TISCI_DEV_GPMC0_BUS_FUNC_CLK   0
 
#define TISCI_DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK   1
 
#define TISCI_DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK3   2
 
#define TISCI_DEV_GPMC0_BUS_FUNC_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK2   3
 
#define TISCI_DEV_GPMC0_BUS_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_BUS_CHIP_DIV1_CLK_CLK4   4
 
#define TISCI_DEV_GPMC0_BUS_PI_GPMC_RET_CLK   5
 
#define TISCI_DEV_GPMC0_BUS_VBUSP_CLK   6
 
#define TISCI_DEV_GPMC0_BUS_PO_GPMC_DEV_CLK   7
 
#define TISCI_DEV_MMCSD1_BUS_EMMCSDSS_VBUS_CLK   0
 
#define TISCI_DEV_MMCSD1_BUS_EMMCSDSS_XIN_CLK   1
 
#define TISCI_DEV_WKUP_PLLCTRL0_BUS_VBUS_SLV_REFCLK_CLK   0
 
#define TISCI_DEV_WKUP_PLLCTRL0_BUS_PLL_CLKOUT_CLK   1
 
#define TISCI_DEV_WKUP_PLLCTRL0_BUS_PLL_REFCLK_CLK   2
 
#define TISCI_DEV_PLLCTRL0_BUS_VBUS_SLV_REFCLK_CLK   0
 
#define TISCI_DEV_PLLCTRL0_BUS_PLL_CLKOUT_CLK   1
 
#define TISCI_DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK   2
 
#define TISCI_DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   3
 
#define TISCI_DEV_PLLCTRL0_BUS_PLL_REFCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT   4
 
#define TISCI_DEV_USB3SS1_BUS_SUSP_CLK   0
 
#define TISCI_DEV_USB3SS1_BUS_PHY2_REFCLK960M_CLK   1
 
#define TISCI_DEV_USB3SS1_BUS_REF_CLK   2
 
#define TISCI_DEV_USB3SS1_BUS_REF_CLK_PARENT_CLOCKMUX_HFOSC_SEL_BUS_OUT0   3
 
#define TISCI_DEV_USB3SS1_BUS_REF_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK48   4
 
#define TISCI_DEV_USB3SS1_BUS_HSIC_CLK_CLK   5
 
#define TISCI_DEV_USB3SS1_BUS_BUS_CLK   6
 
#define TISCI_DEV_USB3SS1_BUS_PIPE3_TXB_CLK   7
 
#define TISCI_DEV_USB3SS1_BUS_UTMI_CLK_CLK   8
 
#define TISCI_DEV_USB3SS0_BUS_SUSP_CLK   0
 
#define TISCI_DEV_USB3SS0_BUS_PHY2_REFCLK960M_CLK   1
 
#define TISCI_DEV_USB3SS0_BUS_REF_CLK   2
 
#define TISCI_DEV_USB3SS0_BUS_REF_CLK_PARENT_CLOCKMUX_HFOSC_SEL_BUS_OUT0   3
 
#define TISCI_DEV_USB3SS0_BUS_REF_CLK_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK48   4
 
#define TISCI_DEV_USB3SS0_BUS_HSIC_CLK_CLK   5
 
#define TISCI_DEV_USB3SS0_BUS_BUS_CLK   6
 
#define TISCI_DEV_USB3SS0_BUS_PIPE3_TXB_CLK   7
 
#define TISCI_DEV_USB3SS0_BUS_PIPE3_TXB_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK   8
 
#define TISCI_DEV_USB3SS0_BUS_PIPE3_TXB_CLK_PARENT_CLOCKMUX_USB0_PIPE3_CLK_SEL_DIV_BUS_WKUP_RCOSC_12P5M_CLK   9
 
#define TISCI_DEV_USB3SS0_BUS_UTMI_CLK_CLK   10
 
#define TISCI_DEV_MCU_MCSPI0_BUS_IO_CLKSPII_CLK   0
 
#define TISCI_DEV_MCU_MCSPI0_BUS_CLKSPIREF_CLK   1
 
#define TISCI_DEV_MCU_MCSPI0_BUS_VBUSP_CLK   2
 
#define TISCI_DEV_MCU_MCSPI0_BUS_IO_CLKSPIO_CLK   3
 
#define TISCI_DEV_MCSPI2_BUS_IO_CLKSPII_CLK   0
 
#define TISCI_DEV_MCSPI2_BUS_CLKSPIREF_CLK   1
 
#define TISCI_DEV_MCSPI2_BUS_VBUSP_CLK   2
 
#define TISCI_DEV_MCSPI2_BUS_IO_CLKSPIO_CLK   3
 
#define TISCI_DEV_MCU_MCSPI2_BUS_CLKSPIREF_CLK   0
 
#define TISCI_DEV_MCU_MCSPI2_BUS_VBUSP_CLK   1
 
#define TISCI_DEV_MCSPI0_BUS_IO_CLKSPII_CLK   0
 
#define TISCI_DEV_MCSPI0_BUS_CLKSPIREF_CLK   1
 
#define TISCI_DEV_MCSPI0_BUS_VBUSP_CLK   2
 
#define TISCI_DEV_MCSPI0_BUS_IO_CLKSPIO_CLK   3
 
#define TISCI_DEV_MCSPI1_BUS_IO_CLKSPII_CLK   0
 
#define TISCI_DEV_MCSPI1_BUS_CLKSPIREF_CLK   1
 
#define TISCI_DEV_MCSPI1_BUS_VBUSP_CLK   2
 
#define TISCI_DEV_MCSPI1_BUS_IO_CLKSPIO_CLK   3
 
#define TISCI_DEV_MCSPI4_BUS_CLKSPIREF_CLK   0
 
#define TISCI_DEV_MCSPI4_BUS_VBUSP_CLK   1
 
#define TISCI_DEV_MCSPI3_BUS_IO_CLKSPII_CLK   0
 
#define TISCI_DEV_MCSPI3_BUS_CLKSPIREF_CLK   1
 
#define TISCI_DEV_MCSPI3_BUS_VBUSP_CLK   2
 
#define TISCI_DEV_MCSPI3_BUS_IO_CLKSPIO_CLK   3
 
#define TISCI_DEV_MCU_MCSPI1_BUS_IO_CLKSPII_CLK   0
 
#define TISCI_DEV_MCU_MCSPI1_BUS_CLKSPIREF_CLK   1
 
#define TISCI_DEV_MCU_MCSPI1_BUS_VBUSP_CLK   2
 
#define TISCI_DEV_MCU_MCSPI1_BUS_IO_CLKSPIO_CLK   3
 
#define TISCI_DEV_DEBUGSS_WRAP0_BUS_JTAG_TCK   0
 
#define TISCI_DEV_DEBUGSS_WRAP0_BUS_ATB_CLK   1
 
#define TISCI_DEV_DEBUGSS_WRAP0_BUS_TREXPT_CLK   2
 
#define TISCI_DEV_DEBUGSS_WRAP0_BUS_CORE_CLK   3
 
#define TISCI_DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK   0
 
#define TISCI_DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK   1
 
#define TISCI_DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK   2
 
#define TISCI_DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT   3
 
#define TISCI_DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT   4
 
#define TISCI_DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT   5
 
#define TISCI_DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT   6
 
#define TISCI_DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK   7
 
#define TISCI_DEV_CBASS_INFRA0_BUS_GTC_CLOCK_1_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK   8
 
#define TISCI_DEV_CBASS_INFRA0_BUS_MAIN_SYSCLK0_2_CLK   9
 
#define TISCI_DEV_CBASS_INFRA0_BUS_MAIN_SYSCLK0_4_CLK   10
 
#define TISCI_DEV_STM0_BUS_CORE_CLK   0
 
#define TISCI_DEV_STM0_BUS_ATB_CLK   1
 
#define TISCI_DEV_STM0_BUS_VBUSP_CLK   2
 
#define TISCI_DEV_MCU_RTI1_BUS_RTI_CLK   0
 
#define TISCI_DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   1
 
#define TISCI_DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT   2
 
#define TISCI_DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK   3
 
#define TISCI_DEV_MCU_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK   4
 
#define TISCI_DEV_MCU_RTI1_BUS_VBUSP_CLK   5
 
#define TISCI_DEV_RTI0_BUS_RTI_CLK   0
 
#define TISCI_DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   1
 
#define TISCI_DEV_RTI0_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT   2
 
#define TISCI_DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK   3
 
#define TISCI_DEV_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK   4
 
#define TISCI_DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT   5
 
#define TISCI_DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0   6
 
#define TISCI_DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1   7
 
#define TISCI_DEV_RTI0_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2   8
 
#define TISCI_DEV_RTI0_BUS_VBUSP_CLK   9
 
#define TISCI_DEV_RTI3_BUS_RTI_CLK   0
 
#define TISCI_DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   1
 
#define TISCI_DEV_RTI3_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT   2
 
#define TISCI_DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK   3
 
#define TISCI_DEV_RTI3_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK   4
 
#define TISCI_DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT   5
 
#define TISCI_DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0   6
 
#define TISCI_DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1   7
 
#define TISCI_DEV_RTI3_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2   8
 
#define TISCI_DEV_RTI3_BUS_VBUSP_CLK   9
 
#define TISCI_DEV_RTI1_BUS_RTI_CLK   0
 
#define TISCI_DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   1
 
#define TISCI_DEV_RTI1_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT   2
 
#define TISCI_DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK   3
 
#define TISCI_DEV_RTI1_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK   4
 
#define TISCI_DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT   5
 
#define TISCI_DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0   6
 
#define TISCI_DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1   7
 
#define TISCI_DEV_RTI1_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2   8
 
#define TISCI_DEV_RTI1_BUS_VBUSP_CLK   9
 
#define TISCI_DEV_MCU_RTI0_BUS_RTI_CLK   0
 
#define TISCI_DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   1
 
#define TISCI_DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT   2
 
#define TISCI_DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK   3
 
#define TISCI_DEV_MCU_RTI0_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK   4
 
#define TISCI_DEV_MCU_RTI0_BUS_VBUSP_CLK   5
 
#define TISCI_DEV_RTI2_BUS_RTI_CLK   0
 
#define TISCI_DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   1
 
#define TISCI_DEV_RTI2_BUS_RTI_CLK_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT   2
 
#define TISCI_DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK   3
 
#define TISCI_DEV_RTI2_BUS_RTI_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK   4
 
#define TISCI_DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT   5
 
#define TISCI_DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0   6
 
#define TISCI_DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1   7
 
#define TISCI_DEV_RTI2_BUS_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2   8
 
#define TISCI_DEV_RTI2_BUS_VBUSP_CLK   9
 
#define TISCI_DEV_PSRAMECC0_BUS_CLK_CLK   0
 
#define TISCI_DEV_EFUSE0_BUS_VBUSP_PLL_CLK_CLK   0
 
#define TISCI_DEV_EFUSE0_BUS_EFC1_CTL_FCLK   1
 
#define TISCI_DEV_EFUSE0_BUS_EFC0_CTL_FCLK   2
 
#define TISCI_DEV_MCASP0_BUS_AUX_CLK   0
 
#define TISCI_DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT   1
 
#define TISCI_DEV_MCASP0_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   2
 
#define TISCI_DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT   3
 
#define TISCI_DEV_MCASP0_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK   4
 
#define TISCI_DEV_MCASP0_BUS_AUX_CLK_PARENT_CLOCKDIVIDER_MCASP_ARM1_PLL_DIV_BUS_OUT0   5
 
#define TISCI_DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT   6
 
#define TISCI_DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0   7
 
#define TISCI_DEV_MCASP0_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1   8
 
#define TISCI_DEV_MCASP0_BUS_VBUSP_CLK   9
 
#define TISCI_DEV_MCASP0_BUS_MCASP_AHCLKX_PIN   10
 
#define TISCI_DEV_MCASP0_BUS_MCASP_AHCLKR_PIN   11
 
#define TISCI_DEV_MCASP1_BUS_AUX_CLK   0
 
#define TISCI_DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT   1
 
#define TISCI_DEV_MCASP1_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   2
 
#define TISCI_DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT   3
 
#define TISCI_DEV_MCASP1_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK   4
 
#define TISCI_DEV_MCASP1_BUS_AUX_CLK_PARENT_CLOCKDIVIDER_MCASP_ARM1_PLL_DIV_BUS_OUT1   5
 
#define TISCI_DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT   6
 
#define TISCI_DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0   7
 
#define TISCI_DEV_MCASP1_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1   8
 
#define TISCI_DEV_MCASP1_BUS_VBUSP_CLK   9
 
#define TISCI_DEV_MCASP1_BUS_MCASP_AHCLKX_PIN   10
 
#define TISCI_DEV_MCASP1_BUS_MCASP_AHCLKR_PIN   11
 
#define TISCI_DEV_MCASP2_BUS_AUX_CLK   0
 
#define TISCI_DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT   1
 
#define TISCI_DEV_MCASP2_BUS_AUX_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   2
 
#define TISCI_DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT   3
 
#define TISCI_DEV_MCASP2_BUS_AUX_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT2_CLK   4
 
#define TISCI_DEV_MCASP2_BUS_AUX_CLK_PARENT_CLOCKDIVIDER_MCASP_ARM1_PLL_DIV_BUS_OUT2   5
 
#define TISCI_DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT   6
 
#define TISCI_DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0   7
 
#define TISCI_DEV_MCASP2_BUS_AUX_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1   8
 
#define TISCI_DEV_MCASP2_BUS_VBUSP_CLK   9
 
#define TISCI_DEV_MCASP2_BUS_MCASP_AHCLKX_PIN   10
 
#define TISCI_DEV_MCASP2_BUS_MCASP_AHCLKR_PIN   11
 
#define TISCI_DEV_MCU_ARMSS0_BUS_INTERFACE_CLK   0
 
#define TISCI_DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_CLK   0
 
#define TISCI_DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE   1
 
#define TISCI_DEV_MCU_ARMSS0_CPU0_BUS_INTERFACE_PHASE_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2   2
 
#define TISCI_DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK   3
 
#define TISCI_DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK   4
 
#define TISCI_DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2   5
 
#define TISCI_DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_CLK   0
 
#define TISCI_DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE   1
 
#define TISCI_DEV_MCU_ARMSS0_CPU1_BUS_INTERFACE_PHASE_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2   2
 
#define TISCI_DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK   3
 
#define TISCI_DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK   4
 
#define TISCI_DEV_MCU_ARMSS0_CPU1_BUS_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK2   5
 
#define TISCI_DEV_CCDEBUGSS0_BUS_ATB1_CLK   0
 
#define TISCI_DEV_CCDEBUGSS0_BUS_ATB0_CLK   1
 
#define TISCI_DEV_CCDEBUGSS0_BUS_SYS_CLK   2
 
#define TISCI_DEV_CCDEBUGSS0_BUS_DBG_CLK   3
 
#define TISCI_DEV_CCDEBUGSS0_BUS_CFG_CLK   4
 
#define TISCI_DEV_WKUP_CTRL_MMR0_BUS_VBUSP_CLK   0
 
#define TISCI_DEV_MCU_CBASS_FW0_BUS_MCU_SYSCLK0_4_CLK   0
 
#define TISCI_DEV_MCU_CBASS_FW0_BUS_MCU_SYSCLK0_2_CLK   1
 
#define TISCI_DEV_MCU_CPSW0_BUS_GMII1_MR_CLK   0
 
#define TISCI_DEV_MCU_CPSW0_BUS_RGMII_MHZ_250_CLK   1
 
#define TISCI_DEV_MCU_CPSW0_BUS_CPTS_RFT_CLK   2
 
#define TISCI_DEV_MCU_CPSW0_BUS_GMII1_MT_CLK   3
 
#define TISCI_DEV_MCU_CPSW0_BUS_RGMII_MHZ_5_CLK   4
 
#define TISCI_DEV_MCU_CPSW0_BUS_RGMII_MHZ_50_CLK   5
 
#define TISCI_DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK   6
 
#define TISCI_DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK5   7
 
#define TISCI_DEV_MCU_CPSW0_BUS_RMII_MHZ_50_CLK_PARENT_BOARD_0_BUS_MCU_RMII1_REFCLK_OUT   8
 
#define TISCI_DEV_MCU_CPSW0_BUS_GMII_RFT_CLK   9
 
#define TISCI_DEV_MCU_CPSW0_BUS_CPPI_CLK_CLK   10
 
#define TISCI_DEV_MCU_CPSW0_BUS_CPTS_GENF0_0   11
 
#define TISCI_DEV_SERDES0_BUS_IP3_LN0_TXRCLK   0
 
#define TISCI_DEV_SERDES0_BUS_REFCLKPP   1
 
#define TISCI_DEV_SERDES0_BUS_CLK   2
 
#define TISCI_DEV_SERDES0_BUS_IP2_LN0_TXRCLK   3
 
#define TISCI_DEV_SERDES0_BUS_LI_REFCLK   4
 
#define TISCI_DEV_SERDES0_BUS_LI_REFCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   5
 
#define TISCI_DEV_SERDES0_BUS_LI_REFCLK_PARENT_BOARD_0_HFOSC1_CLK_OUT   6
 
#define TISCI_DEV_SERDES0_BUS_LI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK   7
 
#define TISCI_DEV_SERDES0_BUS_LI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK   8
 
#define TISCI_DEV_SERDES0_BUS_REFCLKPN   9
 
#define TISCI_DEV_SERDES0_BUS_LN0_TXCLK   10
 
#define TISCI_DEV_SERDES0_BUS_LN0_RXCLK   11
 
#define TISCI_DEV_SERDES1_BUS_IP3_LN0_TXRCLK   0
 
#define TISCI_DEV_SERDES1_BUS_REFCLKPP   1
 
#define TISCI_DEV_SERDES1_BUS_CLK   2
 
#define TISCI_DEV_SERDES1_BUS_IP1_LN0_TXRCLK   3
 
#define TISCI_DEV_SERDES1_BUS_IP2_LN0_TXRCLK   4
 
#define TISCI_DEV_SERDES1_BUS_RI_REFCLK   5
 
#define TISCI_DEV_SERDES1_BUS_RI_REFCLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   6
 
#define TISCI_DEV_SERDES1_BUS_RI_REFCLK_PARENT_BOARD_0_HFOSC1_CLK_OUT   7
 
#define TISCI_DEV_SERDES1_BUS_RI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK   8
 
#define TISCI_DEV_SERDES1_BUS_RI_REFCLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK   9
 
#define TISCI_DEV_SERDES1_BUS_REFCLKPN   10
 
#define TISCI_DEV_SERDES1_BUS_LN0_TXCLK   11
 
#define TISCI_DEV_SERDES1_BUS_LN0_RXCLK   12
 
#define TISCI_DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_PLL_CLK   0
 
#define TISCI_DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_0_FWD_P_CLK_BUS_IN1_CLOCKDIVIDER_DSS_BUS_OUT0   1
 
#define TISCI_DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_0_FWD_P_CLK_BUS_IN0_CLOCKDIVIDER_DSS_BUS_OUT0   2
 
#define TISCI_DEV_MCU_ADC1_BUS_VBUS_CLK   0
 
#define TISCI_DEV_MCU_ADC1_BUS_SYS_CLK   1
 
#define TISCI_DEV_MCU_ADC1_BUS_ADC_CLK   2
 
#define TISCI_DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   3
 
#define TISCI_DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK   4
 
#define TISCI_DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK   5
 
#define TISCI_DEV_MCU_ADC1_BUS_ADC_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT   6
 
#define TISCI_DEV_MCU_ADC0_BUS_VBUS_CLK   0
 
#define TISCI_DEV_MCU_ADC0_BUS_SYS_CLK   1
 
#define TISCI_DEV_MCU_ADC0_BUS_ADC_CLK   2
 
#define TISCI_DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   3
 
#define TISCI_DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK   4
 
#define TISCI_DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK   5
 
#define TISCI_DEV_MCU_ADC0_BUS_ADC_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT   6
 
#define TISCI_DEV_WKUP_DMSC0_BUS_FUNC_32K_RT_CLK   0
 
#define TISCI_DEV_WKUP_DMSC0_BUS_FUNC_MOSC_CLK   1
 
#define TISCI_DEV_WKUP_DMSC0_BUS_VBUS_CLK   2
 
#define TISCI_DEV_WKUP_DMSC0_BUS_FUNC_32K_RC_CLK   3
 
#define TISCI_DEV_WKUP_DMSC0_BUS_SEC_EFC_FCLK   4
 
#define TISCI_DEV_WKUP_DMSC0_BUS_DAP_CLK   5
 
#define TISCI_DEV_WKUP_DMSC0_BUS_EXT_CLK   6
 
#define TISCI_DEV_MCU_PLL_MMR0_BUS_VBUSP_CLK   0
 
#define TISCI_DEV_MCU_SEC_MMR0_BUS_VBUSP_CLK   0
 
#define TISCI_DEV_GIC0_BUS_VCLK_CLK   0
 
#define TISCI_DEV_MCU_DEBUGSS0_BUS_ATB1_CLK   0
 
#define TISCI_DEV_MCU_DEBUGSS0_BUS_ATB0_CLK   1
 
#define TISCI_DEV_MCU_DEBUGSS0_BUS_SYS_CLK   2
 
#define TISCI_DEV_MCU_DEBUGSS0_BUS_CFG_CLK   3
 
#define TISCI_DEV_MCU_DEBUGSS0_BUS_ATB2_CLK   4
 
#define TISCI_DEV_MCU_DEBUGSS0_BUS_DBG_CLK   5
 
#define TISCI_DEV_MCU_DEBUGSS0_BUS_ATB3_CLK   6
 
#define TISCI_DEV_EQEP0_BUS_VBUS_CLK   0
 
#define TISCI_DEV_EQEP2_BUS_VBUS_CLK   0
 
#define TISCI_DEV_EQEP1_BUS_VBUS_CLK   0
 
#define TISCI_DEV_WKUP_GPIO0_BUS_MMR_CLK   0
 
#define TISCI_DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK4   1
 
#define TISCI_DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_BUS_CHIP_DIV1_CLK_CLK4_DUP0   2
 
#define TISCI_DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK   3
 
#define TISCI_DEV_WKUP_GPIO0_BUS_MMR_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK   4
 
#define TISCI_DEV_GPIO0_BUS_MMR_CLK   0
 
#define TISCI_DEV_GPIO1_BUS_MMR_CLK   0
 
#define TISCI_DEV_COMPUTE_CLUSTER_MSMC0_BUS_TB_SOC_VBUSP_DMSC_CLK   0
 
#define TISCI_DEV_COMPUTE_CLUSTER_MSMC0_BUS_TB_SOC_VBUSP_DBG_CLK   1
 
#define TISCI_DEV_COMPUTE_CLUSTER_MSMC0_BUS_MSMC_CLK   2
 
#define TISCI_DEV_COMPUTE_CLUSTER_MSMC0_BUS_TB_SOC_VBUSP_CFG_CLK   3
 
#define TISCI_DEV_COMPUTE_CLUSTER_MSMC0_BUS_TB_SOC_GIC_CLK   4
 
#define TISCI_DEV_COMPUTE_CLUSTER_CPAC0_BUS_ARM0_CLK   0
 
#define TISCI_DEV_COMPUTE_CLUSTER_CPAC1_BUS_ARM1_CLK   0
 
#define TISCI_DEV_COMPUTE_CLUSTER_A53_0_BUS_ARM0_CLK   0
 
#define TISCI_DEV_COMPUTE_CLUSTER_A53_1_BUS_ARM0_CLK   0
 
#define TISCI_DEV_COMPUTE_CLUSTER_A53_2_BUS_ARM1_CLK   0
 
#define TISCI_DEV_COMPUTE_CLUSTER_A53_3_BUS_ARM1_CLK   0
 
#define TISCI_DEV_WKUP_CBASS0_BUS_WKUP_MCU_PLL_OUT_2_CLK   0
 
#define TISCI_DEV_WKUP_CBASS0_BUS_WKUP_MCU_PLL_OUT_4_CLK   1
 
#define TISCI_DEV_MCU_ROM0_BUS_CLK_CLK   0
 
#define TISCI_DEV_K3_ARM_ATB_FUNNEL_3_32_MCU_0_BUS_DBG_CLK   0
 
#define TISCI_DEV_ESM0_BUS_CLK   0
 
#define TISCI_DEV_PRU_ICSSG2_BUS_RGMII_MHZ_5_CLK   0
 
#define TISCI_DEV_PRU_ICSSG2_BUS_WIZ1_TX_SLV_CLK   1
 
#define TISCI_DEV_PRU_ICSSG2_BUS_WIZ0_RX_SLV_CLK   2
 
#define TISCI_DEV_PRU_ICSSG2_BUS_VCLK_CLK   3
 
#define TISCI_DEV_PRU_ICSSG2_BUS_UCLK_CLK   4
 
#define TISCI_DEV_PRU_ICSSG2_BUS_WIZ0_TX_SLV_CLK   5
 
#define TISCI_DEV_PRU_ICSSG2_BUS_WIZ1_RX_SLV_CLK   6
 
#define TISCI_DEV_PRU_ICSSG2_BUS_PR1_RGMII1_RXC_I   7
 
#define TISCI_DEV_PRU_ICSSG2_BUS_RGMII_MHZ_250_CLK   8
 
#define TISCI_DEV_PRU_ICSSG2_BUS_RGMII_MHZ_50_CLK   9
 
#define TISCI_DEV_PRU_ICSSG2_BUS_IEP_CLK   10
 
#define TISCI_DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK   11
 
#define TISCI_DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK   12
 
#define TISCI_DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT   13
 
#define TISCI_DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT   14
 
#define TISCI_DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT   15
 
#define TISCI_DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT   16
 
#define TISCI_DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK   17
 
#define TISCI_DEV_PRU_ICSSG2_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK   18
 
#define TISCI_DEV_PRU_ICSSG2_BUS_CORE_CLK   19
 
#define TISCI_DEV_PRU_ICSSG2_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK   20
 
#define TISCI_DEV_PRU_ICSSG2_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK   21
 
#define TISCI_DEV_PRU_ICSSG2_BUS_PR1_RGMII0_RXC_I   22
 
#define TISCI_DEV_PRU_ICSSG2_BUS_PR1_RGMII1_TXC_I   23
 
#define TISCI_DEV_PRU_ICSSG2_BUS_PR1_RGMII0_TXC_I   24
 
#define TISCI_DEV_PRU_ICSSG2_BUS_WIZ1_TX_MST_CLK   25
 
#define TISCI_DEV_PRU_ICSSG2_BUS_WIZ0_TX_MST_CLK   26
 
#define TISCI_DEV_PRU_ICSSG0_BUS_RGMII_MHZ_5_CLK   0
 
#define TISCI_DEV_PRU_ICSSG0_BUS_WIZ1_TX_SLV_CLK   1
 
#define TISCI_DEV_PRU_ICSSG0_BUS_WIZ0_RX_SLV_CLK   2
 
#define TISCI_DEV_PRU_ICSSG0_BUS_VCLK_CLK   3
 
#define TISCI_DEV_PRU_ICSSG0_BUS_UCLK_CLK   4
 
#define TISCI_DEV_PRU_ICSSG0_BUS_WIZ0_TX_SLV_CLK   5
 
#define TISCI_DEV_PRU_ICSSG0_BUS_WIZ1_RX_SLV_CLK   6
 
#define TISCI_DEV_PRU_ICSSG0_BUS_PR1_RGMII1_RXC_I   7
 
#define TISCI_DEV_PRU_ICSSG0_BUS_RGMII_MHZ_250_CLK   8
 
#define TISCI_DEV_PRU_ICSSG0_BUS_RGMII_MHZ_50_CLK   9
 
#define TISCI_DEV_PRU_ICSSG0_BUS_IEP_CLK   10
 
#define TISCI_DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK   11
 
#define TISCI_DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK   12
 
#define TISCI_DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT   13
 
#define TISCI_DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT   14
 
#define TISCI_DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT   15
 
#define TISCI_DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT   16
 
#define TISCI_DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK   17
 
#define TISCI_DEV_PRU_ICSSG0_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK   18
 
#define TISCI_DEV_PRU_ICSSG0_BUS_CORE_CLK   19
 
#define TISCI_DEV_PRU_ICSSG0_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK   20
 
#define TISCI_DEV_PRU_ICSSG0_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK   21
 
#define TISCI_DEV_PRU_ICSSG0_BUS_PR1_RGMII0_RXC_I   22
 
#define TISCI_DEV_PRU_ICSSG0_BUS_PR1_RGMII1_TXC_I   23
 
#define TISCI_DEV_PRU_ICSSG0_BUS_PR1_RGMII0_TXC_I   24
 
#define TISCI_DEV_PRU_ICSSG1_BUS_RGMII_MHZ_5_CLK   0
 
#define TISCI_DEV_PRU_ICSSG1_BUS_WIZ1_TX_SLV_CLK   1
 
#define TISCI_DEV_PRU_ICSSG1_BUS_WIZ0_RX_SLV_CLK   2
 
#define TISCI_DEV_PRU_ICSSG1_BUS_VCLK_CLK   3
 
#define TISCI_DEV_PRU_ICSSG1_BUS_UCLK_CLK   4
 
#define TISCI_DEV_PRU_ICSSG1_BUS_WIZ0_TX_SLV_CLK   5
 
#define TISCI_DEV_PRU_ICSSG1_BUS_WIZ1_RX_SLV_CLK   6
 
#define TISCI_DEV_PRU_ICSSG1_BUS_PR1_RGMII1_RXC_I   7
 
#define TISCI_DEV_PRU_ICSSG1_BUS_RGMII_MHZ_250_CLK   8
 
#define TISCI_DEV_PRU_ICSSG1_BUS_RGMII_MHZ_50_CLK   9
 
#define TISCI_DEV_PRU_ICSSG1_BUS_IEP_CLK   10
 
#define TISCI_DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK   11
 
#define TISCI_DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK   12
 
#define TISCI_DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT   13
 
#define TISCI_DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT   14
 
#define TISCI_DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT   15
 
#define TISCI_DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT   16
 
#define TISCI_DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK   17
 
#define TISCI_DEV_PRU_ICSSG1_BUS_IEP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK   18
 
#define TISCI_DEV_PRU_ICSSG1_BUS_CORE_CLK   19
 
#define TISCI_DEV_PRU_ICSSG1_BUS_CORE_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_HSDIV_CLKOUT1_CLK   20
 
#define TISCI_DEV_PRU_ICSSG1_BUS_CORE_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK   21
 
#define TISCI_DEV_PRU_ICSSG1_BUS_PR1_RGMII0_RXC_I   22
 
#define TISCI_DEV_PRU_ICSSG1_BUS_PR1_RGMII1_TXC_I   23
 
#define TISCI_DEV_PRU_ICSSG1_BUS_PR1_RGMII0_TXC_I   24
 
#define TISCI_DEV_MCU_ESM0_BUS_CLK   0
 
#define TISCI_DEV_ECAP0_BUS_VBUS_CLK   0
 
#define TISCI_DEV_WKUP_ESM0_BUS_CLK   0
 
#define TISCI_DEV_MCU_EFUSE0_BUS_VBUSP_CLK_CLK   0
 
#define TISCI_DEV_MCU_EFUSE0_BUS_EFC3_CTL_FCLK   1
 
#define TISCI_DEV_MCU_EFUSE0_BUS_EFC0_CTL_FCLK   2
 
#define TISCI_DEV_MCU_EFUSE0_BUS_EFC1_CTL_FCLK   3
 
#define TISCI_DEV_MCU_EFUSE0_BUS_EFC2_CTL_FCLK   4
 
#define TISCI_DEV_MCU_CTRL_MMR0_BUS_VBUSP_CLK   0
 
#define TISCI_DEV_PSC0_BUS_CLK   0
 
#define TISCI_DEV_PSC0_BUS_SLOW_CLK   1
 
#define TISCI_DEV_CTRL_MMR0_BUS_VBUSP_CLK   0
 
#define TISCI_DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK   0
 
#define TISCI_DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK   1
 
#define TISCI_DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK2   2
 
#define TISCI_DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK2   3
 
#define TISCI_DEV_MCU_MCAN0_BUS_MCANSS_CCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   4
 
#define TISCI_DEV_MCU_MCAN0_BUS_MCANSS_HCLK_CLK   5
 
#define TISCI_DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK   0
 
#define TISCI_DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK   1
 
#define TISCI_DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK2   2
 
#define TISCI_DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK2   3
 
#define TISCI_DEV_MCU_MCAN1_BUS_MCANSS_CCLK_CLK_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   4
 
#define TISCI_DEV_MCU_MCAN1_BUS_MCANSS_HCLK_CLK   5
 
#define TISCI_DEV_DDRSS0_BUS_DDRSS_VBUS_CLK   0
 
#define TISCI_DEV_DDRSS0_BUS_DDRSS_BYP_4X_CLK   1
 
#define TISCI_DEV_DDRSS0_BUS_DDRSS_CTL_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK   2
 
#define TISCI_DEV_DDRSS0_BUS_DDRSS_TCLK   3
 
#define TISCI_DEV_DDRSS0_BUS_DDRSS_PHY_CTL_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK   4
 
#define TISCI_DEV_DDRSS0_BUS_DDRSS_PHY_CTL_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK   5
 
#define TISCI_DEV_DDRSS0_BUS_DDRSS_CFG_CLK   6
 
#define TISCI_DEV_DDRSS0_BUS_DDRSS_CTL_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK   7
 
#define TISCI_DEV_DDRSS0_BUS_DDRSS_BYP_CLK_BUS_IN1_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK   8
 
#define TISCI_DEV_DDRSS0_BUS_DDRSS_BYP_CLK_BUS_IN0_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK   9
 
#define TISCI_DEV_MCU_NAVSS0_BUS_UDMASS_VD2CLK   0
 
#define TISCI_DEV_MCU_NAVSS0_BUS_CPSW0CLK   1
 
#define TISCI_DEV_MCU_NAVSS0_BUS_MODSS_VD2CLK   2
 
#define TISCI_DEV_MCU_NAVSS0_BUS_PDMA_MCU1CLK   3
 
#define TISCI_DEV_MCU_FSS0_HYPERBUS0_BUS_HPB_CLKX1_INV_CLK   0
 
#define TISCI_DEV_MCU_FSS0_HYPERBUS0_BUS_HPB_CLKX1_CLK   1
 
#define TISCI_DEV_MCU_FSS0_HYPERBUS0_BUS_HPB_CLKX2_CLK   2
 
#define TISCI_DEV_MCU_FSS0_HYPERBUS0_BUS_CBA_CLK   3
 
#define TISCI_DEV_MCU_FSS0_HYPERBUS0_BUS_HPB_CLKX2_INV_CLK   4
 
#define TISCI_DEV_MCU_FSS0_HYPERBUS0_HPB_OUT_CLK_N   5
 
#define TISCI_DEV_MCU_FSS0_HYPERBUS0_HPB_OUT_CLK_P   6
 
#define TISCI_DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_RCLK_CLK   0
 
#define TISCI_DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK   1
 
#define TISCI_DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK   2
 
#define TISCI_DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_ICLK_CLK   3
 
#define TISCI_DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_ICLK_CLK_PARENT_BOARD_0_BUS_MCU_OSPI0DQS_OUT   4
 
#define TISCI_DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_BUS_OSPI0_OCLK_CLK   5
 
#define TISCI_DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_PCLK_CLK   6
 
#define TISCI_DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_DQS_CLK   7
 
#define TISCI_DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_HCLK_CLK   8
 
#define TISCI_DEV_MCU_FSS0_OSPI_0_BUS_OSPI0_OCLK_CLK   9
 
#define TISCI_DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_PCLK_CLK   0
 
#define TISCI_DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_ICLK_CLK   1
 
#define TISCI_DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_ICLK_CLK_PARENT_BOARD_0_BUS_MCU_OSPI1DQS_OUT   2
 
#define TISCI_DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_1_BUS_OSPI1_OCLK_CLK   3
 
#define TISCI_DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_HCLK_CLK   4
 
#define TISCI_DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_DQS_CLK   5
 
#define TISCI_DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_RCLK_CLK   6
 
#define TISCI_DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK   7
 
#define TISCI_DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_RCLK_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK   8
 
#define TISCI_DEV_MCU_FSS0_OSPI_1_BUS_OSPI1_OCLK_CLK   9
 
#define TISCI_DEV_DFTSS0_BUS_VBUSP_CLK_CLK   0
 
#define TISCI_DEV_WKUP_GPIOMUX_INTRTR0_BUS_INTR_CLK   0
 
#define TISCI_DEV_GPIOMUX_INTRTR0_BUS_INTR_CLK   0
 
#define TISCI_DEV_MAIN2MCU_LVL_INTRTR0_BUS_INTR_CLK   0
 
#define TISCI_DEV_MAIN2MCU_PLS_INTRTR0_BUS_INTR_CLK   0
 
#define TISCI_DEV_GPU0_BUS_MEM_CLK   0
 
#define TISCI_DEV_GPU0_BUS_HYD_CORE_CLK   1
 
#define TISCI_DEV_GPU0_BUS_SGX_CORE_CLK   2
 
#define TISCI_DEV_GPU0_BUS_SYS_CLK   3
 
#define TISCI_DEV_PDMA_DEBUG0_BUS_VCLK   0
 
#define TISCI_DEV_PDMA0_BUS_VCLK   0
 
#define TISCI_DEV_PDMA1_BUS_VCLK   0
 
#define TISCI_DEV_MCU_PDMA0_BUS_VCLK   0
 
#define TISCI_DEV_MCU_PDMA1_BUS_VCLK   0
 
#define TISCI_DEV_MCU_MSRAM0_BUS_CCLK_CLK   0
 
#define TISCI_DEV_MCU_MSRAM0_BUS_VCLK_CLK   1
 
#define TISCI_DEV_CMPEVENT_INTRTR0_BUS_INTR_CLK   0
 
#define TISCI_DEV_DEBUGSUSPENDRTR0_BUS_INTR_CLK   0
 
#define TISCI_DEV_TIMESYNC_INTRTR0_BUS_INTR_CLK   0
 
#define TISCI_DEV_CBASS_DEBUG0_BUS_MAIN_SYSCLK0_2_CLK   0
 
#define TISCI_DEV_CBASS_DEBUG0_BUS_MAIN_SYSCLK0_4_CLK   1
 
#define TISCI_DEV_CBASS_FW0_BUS_MAIN_SYSCLK0_2_CLK   0
 
#define TISCI_DEV_CBASS_FW0_BUS_MAIN_SYSCLK0_4_CLK   1
 
#define TISCI_DEV_MCU_CBASS_DEBUG0_BUS_MCU_SYSCLK0_2_CLK   0
 
#define TISCI_DEV_WKUP_CBASS_FW0_BUS_WKUP_MCU_PLL_OUT_2_CLK   0
 
#define TISCI_DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1_OUT   0
 
#define TISCI_DEV_PCIE0_BUS_PCIE_CBA_CLK   1
 
#define TISCI_DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK_OUT   2
 
#define TISCI_DEV_PCIE0_BUS_PCIE_TXI0_CLK   3
 
#define TISCI_DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK   4
 
#define TISCI_DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK   5
 
#define TISCI_DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT   6
 
#define TISCI_DEV_PCIE0_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT   7
 
#define TISCI_DEV_PCIE0_BUS_PCIE_TXR1_CLK   8
 
#define TISCI_DEV_PCIE0_BUS_PCIE_TXR0_CLK   9
 
#define TISCI_DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN5_BOARD_0_BUS_EXT_REFCLK1_OUT   0
 
#define TISCI_DEV_PCIE1_BUS_PCIE_CBA_CLK   1
 
#define TISCI_DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN3_BOARD_0_BUS_CPTS_RFT_CLK_OUT   2
 
#define TISCI_DEV_PCIE1_BUS_PCIE_TXI0_CLK   3
 
#define TISCI_DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN1_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK   4
 
#define TISCI_DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN0_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK   5
 
#define TISCI_DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN4_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT   6
 
#define TISCI_DEV_PCIE1_BUS_PCIE_CPTS_RCLK_CLK_BUS_IN2_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT   7
 
#define TISCI_DEV_PCIE1_BUS_PCIE_TXR0_CLK   8
 
#define TISCI_DEV_GTC0_BUS_VBUSP_CLK   0
 
#define TISCI_DEV_GTC0_BUS_VBUSP_CLK_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK   1
 
#define TISCI_DEV_GTC0_BUS_VBUSP_CLK_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT3_CLK   2
 
#define TISCI_DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_MCU_CPTS_RFT_CLK_OUT   3
 
#define TISCI_DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_CPTS_RFT_CLK_OUT   4
 
#define TISCI_DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_MCU_EXT_REFCLK0_OUT   5
 
#define TISCI_DEV_GTC0_BUS_VBUSP_CLK_PARENT_BOARD_0_BUS_EXT_REFCLK1_OUT   6
 
#define TISCI_DEV_GTC0_BUS_VBUSP_CLK_PARENT_WIZ8B2M4VSB_MAIN_0_BUS_LN0_TXCLK   7
 
#define TISCI_DEV_GTC0_BUS_VBUSP_CLK_PARENT_WIZ8B2M4VSB_MAIN_1_BUS_LN0_TXCLK   8
 
#define TISCI_DEV_WKUP_VTM0_BUS_FIX_REF_CLK   0
 
#define TISCI_DEV_WKUP_VTM0_BUS_VBUSP_CLK   1
 
#define TISCI_DEV_MMCSD0_BUS_EMMCSDSS_VBUS_CLK   0
 
#define TISCI_DEV_MMCSD0_BUS_EMMCSDSS_XIN_CLK   1
 
#define TISCI_DEV_MCU_ECC_AGGR0_BUS_AGGR_CLK   0
 
#define TISCI_DEV_ECC_AGGR1_BUS_AGGR_CLK   0
 
#define TISCI_DEV_ECC_AGGR2_BUS_AGGR_CLK   0
 
#define TISCI_DEV_MCU_ECC_AGGR1_BUS_AGGR_CLK   0
 
#define TISCI_DEV_WKUP_ECC_AGGR0_BUS_AGGR_CLK   0
 
#define TISCI_DEV_ECC_AGGR0_BUS_AGGR_CLK   0
 
#define TISCI_DEV_MCU_PSRAM0_BUS_CLK_CLK   0
 
#define TISCI_DEV_GS80PRG_SOC_WRAP_WKUP_0_BUS_OSC_CLK   0
 
#define TISCI_DEV_GS80PRG_SOC_WRAP_WKUP_0_BUS_CLK   1
 
#define TISCI_DEV_GS80PRG_MCU_WRAP_WKUP_0_BUS_OSC_CLK   0
 
#define TISCI_DEV_GS80PRG_MCU_WRAP_WKUP_0_BUS_CLK   1
 
#define TISCI_DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_8_CLK   0
 
#define TISCI_DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_4_CLK   1
 
#define TISCI_DEV_MCU_CBASS0_BUS_MCU_SYSCLK0_2_CLK   2
 
#define TISCI_DEV_MX_EFUSE_MAIN_CHAIN_MAIN_0_BUS_UNDEFINEDCHAIN1_FCLK   0
 
#define TISCI_DEV_MX_EFUSE_MAIN_CHAIN_MAIN_0_BUS_UNDEFINEDCHAIN0_FCLK   1
 
#define TISCI_DEV_MX_EFUSE_MCU_CHAIN_MCU_0_BUS_UNDEFINEDCHAIN1_FCLK   0
 
#define TISCI_DEV_MX_EFUSE_MCU_CHAIN_MCU_0_BUS_UNDEFINEDCHAIN0_FCLK   1
 
#define TISCI_DEV_MX_EFUSE_MCU_CHAIN_MCU_0_BUS_UNDEFINEDCHAIN2_FCLK   2
 
#define TISCI_DEV_BOARD0_BUS_SCL3_IN   0
 
#define TISCI_DEV_BOARD0_BUS_SCL2_IN   1
 
#define TISCI_DEV_BOARD0_BUS_SCL1_IN   2
 
#define TISCI_DEV_BOARD0_BUS_SCL0_IN   3
 
#define TISCI_DEV_BOARD0_BUS_PRG2_RGMII2_TCLK_IN   4
 
#define TISCI_DEV_BOARD0_BUS_MCU_OSPI1CLK_IN   5
 
#define TISCI_DEV_BOARD0_BUS_PRG1_RGMII1_TCLK_IN   6
 
#define TISCI_DEV_BOARD0_BUS_REFCLK1P_IN   7
 
#define TISCI_DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   8
 
#define TISCI_DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT   9
 
#define TISCI_DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK   10
 
#define TISCI_DEV_BOARD0_BUS_REFCLK1P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK   11
 
#define TISCI_DEV_BOARD0_BUS_MCU_OSPI1LBCLKO_IN   12
 
#define TISCI_DEV_BOARD0_BUS_MCU_OBSCLK_IN   13
 
#define TISCI_DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_12P5M_CLK   14
 
#define TISCI_DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   15
 
#define TISCI_DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_CLKOUT_CLK   16
 
#define TISCI_DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_CLKOUT_CLK_DUP0   17
 
#define TISCI_DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT1_CLK   18
 
#define TISCI_DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT2_CLK   19
 
#define TISCI_DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT3_CLK   20
 
#define TISCI_DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_0_BUS_HSDIV_CLKOUT4_CLK   21
 
#define TISCI_DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK   22
 
#define TISCI_DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_RCOSC_32K_CLK   23
 
#define TISCI_DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT1_CLK   24
 
#define TISCI_DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT2_CLK   25
 
#define TISCI_DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT3_CLK   26
 
#define TISCI_DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_HSDIV_CLKOUT4_CLK   27
 
#define TISCI_DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK_DUP0   28
 
#define TISCI_DEV_BOARD0_BUS_MCU_OBSCLK_IN_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT   29
 
#define TISCI_DEV_BOARD0_BUS_PRG2_RGMII1_TCLK_IN   30
 
#define TISCI_DEV_BOARD0_BUS_REFCLK1M_IN   31
 
#define TISCI_DEV_BOARD0_BUS_REFCLK1M_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   32
 
#define TISCI_DEV_BOARD0_BUS_REFCLK1M_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT   33
 
#define TISCI_DEV_BOARD0_BUS_REFCLK1M_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK   34
 
#define TISCI_DEV_BOARD0_BUS_REFCLK1M_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK   35
 
#define TISCI_DEV_BOARD0_BUS_OBSCLK_IN   36
 
#define TISCI_DEV_BOARD0_BUS_OBSCLK_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT   37
 
#define TISCI_DEV_BOARD0_BUS_OBSCLK_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   38
 
#define TISCI_DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK   39
 
#define TISCI_DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_WRAP_MAIN_1_BUS_CLKOUT_CLK   40
 
#define TISCI_DEV_BOARD0_BUS_OBSCLK_IN_PARENT_GLUELOGIC_LFOSC_CLK_BUS_OUT   41
 
#define TISCI_DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_2_BUS_CLKOUT_CLK   42
 
#define TISCI_DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_WRAP_MAIN_4_BUS_CLKOUT_CLK   43
 
#define TISCI_DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLM_WRAP_MAIN_6_BUS_CLKOUT_CLK   44
 
#define TISCI_DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_WRAP_MAIN_3_BUS_CLKOUT_CLK   45
 
#define TISCI_DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK   46
 
#define TISCI_DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT1_CLK   47
 
#define TISCI_DEV_BOARD0_BUS_OBSCLK_IN_PARENT_ADPLLM_WRAP_MAIN_7_BUS_CLKOUT_CLK   48
 
#define TISCI_DEV_BOARD0_BUS_OBSCLK_IN_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF2_0   49
 
#define TISCI_DEV_BOARD0_BUS_OBSCLK_IN_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF3_0   50
 
#define TISCI_DEV_BOARD0_BUS_OBSCLK_IN_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF4_0   51
 
#define TISCI_DEV_BOARD0_BUS_OBSCLK_IN_PARENT_NAVSS256L_MAIN_0_BUS_CPTS0_GENF5_0   52
 
#define TISCI_DEV_BOARD0_BUS_PRG0_RGMII1_TCLK_IN   53
 
#define TISCI_DEV_BOARD0_BUS_MCU_OSPI0CLK_IN   54
 
#define TISCI_DEV_BOARD0_BUS_DSS0PCLK_IN   55
 
#define TISCI_DEV_BOARD0_BUS_PRG0_RGMII2_TCLK_IN   56
 
#define TISCI_DEV_BOARD0_BUS_WKUP_SCL0_IN   57
 
#define TISCI_DEV_BOARD0_BUS_REFCLK0P_IN   58
 
#define TISCI_DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   59
 
#define TISCI_DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT   60
 
#define TISCI_DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK   61
 
#define TISCI_DEV_BOARD0_BUS_REFCLK0P_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK   62
 
#define TISCI_DEV_BOARD0_BUS_REFCLK0M_IN   63
 
#define TISCI_DEV_BOARD0_BUS_REFCLK0M_IN_PARENT_MX_WAKEUP_GS80_WKUP_0_BUS_WKUP_OSC0_CLK   64
 
#define TISCI_DEV_BOARD0_BUS_REFCLK0M_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT   65
 
#define TISCI_DEV_BOARD0_BUS_REFCLK0M_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_CLKOUT_CLK   66
 
#define TISCI_DEV_BOARD0_BUS_REFCLK0M_IN_PARENT_ADPLLLJM_HSDIV_WRAP_MAIN_0_BUS_HSDIV_CLKOUT4_CLK   67
 
#define TISCI_DEV_BOARD0_BUS_MCU_OSPI0LBCLKO_IN   68
 
#define TISCI_DEV_BOARD0_BUS_MCU_CLKOUT_IN   69
 
#define TISCI_DEV_BOARD0_BUS_MCU_CLKOUT_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK5   70
 
#define TISCI_DEV_BOARD0_BUS_MCU_CLKOUT_IN_PARENT_ADPLLM_HSDIV_WRAP_MCU_1_BUS_CLKOUT_CLK10   71
 
#define TISCI_DEV_BOARD0_BUS_MCU_SCL0_IN   72
 
#define TISCI_DEV_BOARD0_BUS_SYSCLKOUT_IN   73
 
#define TISCI_DEV_BOARD0_BUS_MCU_SYSCLKOUT_IN   74
 
#define TISCI_DEV_BOARD0_BUS_PRG1_RGMII1_RCLK_OUT   75
 
#define TISCI_DEV_BOARD0_BUS_PRG1_RGMII2_RCLK_OUT   76
 
#define TISCI_DEV_BOARD0_BUS_GPMCCLK_OUT   77
 
#define TISCI_DEV_BOARD0_BUS_MCASP2AHCLKX_OUT   78
 
#define TISCI_DEV_BOARD0_BUS_MCASP2AHCLKR_OUT   79
 
#define TISCI_DEV_BOARD0_BUS_PRG2_RGMII2_RCLK_OUT   80
 
#define TISCI_DEV_BOARD0_BUS_CPTS_RFT_CLK_OUT   81
 
#define TISCI_DEV_BOARD0_BUS_MCASP0ACLKR_OUT   82
 
#define TISCI_DEV_BOARD0_BUS_MCASP0ACLKX_OUT   83
 
#define TISCI_DEV_BOARD0_BUS_EXT_REFCLK1_OUT   84
 
#define TISCI_DEV_BOARD0_BUS_PRG0_RGMII2_RCLK_OUT   85
 
#define TISCI_DEV_BOARD0_BUS_MCU_OSPI0DQS_OUT   86
 
#define TISCI_DEV_BOARD0_BUS_USB0REFCLKP_OUT   87
 
#define TISCI_DEV_BOARD0_BUS_DSS0EXTPCLKIN_OUT   88
 
#define TISCI_DEV_BOARD0_BUS_SPI1CLK_OUT   89
 
#define TISCI_DEV_BOARD0_BUS_MCASP2ACLKR_OUT   90
 
#define TISCI_DEV_BOARD0_BUS_MCASP1ACLKX_OUT   91
 
#define TISCI_DEV_BOARD0_BUS_MCASP1ACLKR_OUT   92
 
#define TISCI_DEV_BOARD0_BUS_MCASP2ACLKX_OUT   93
 
#define TISCI_DEV_BOARD0_BUS_MCU_RMII1_REFCLK_OUT   94
 
#define TISCI_DEV_BOARD0_BUS_MCU_CPTS_RFT_CLK_OUT   95
 
#define TISCI_DEV_BOARD0_BUS_MCU_RGMII1_TCLK_OUT   96
 
#define TISCI_DEV_BOARD0_BUS_MCU_SPI0CLK_OUT   97
 
#define TISCI_DEV_BOARD0_BUS_MCU_SPI1CLK_OUT   98
 
#define TISCI_DEV_BOARD0_BUS_PRG0_RGMII1_RCLK_OUT   99
 
#define TISCI_DEV_BOARD0_BUS_SPI2CLK_OUT   100
 
#define TISCI_DEV_BOARD0_BUS_WKUP_TCK_OUT   101
 
#define TISCI_DEV_BOARD0_BUS_SPI3CLK_OUT   102
 
#define TISCI_DEV_BOARD0_BUS_USB0REFCLKM_OUT   103
 
#define TISCI_DEV_BOARD0_BUS_MCU_RGMII1_RCLK_OUT   104
 
#define TISCI_DEV_BOARD0_BUS_MCASP0AHCLKR_OUT   105
 
#define TISCI_DEV_BOARD0_BUS_MCU_EXT_REFCLK0_OUT   106
 
#define TISCI_DEV_BOARD0_BUS_MCASP0AHCLKX_OUT   107
 
#define TISCI_DEV_BOARD0_BUS_CCDC0_PCLK_OUT   108
 
#define TISCI_DEV_BOARD0_HFOSC1_CLK_OUT   109
 
#define TISCI_DEV_BOARD0_BUS_MCU_OSPI1DQS_OUT   110
 
#define TISCI_DEV_BOARD0_BUS_MCASP1AHCLKX_OUT   111
 
#define TISCI_DEV_BOARD0_BUS_PCIE1REFCLKM_OUT   112
 
#define TISCI_DEV_BOARD0_BUS_MCASP1AHCLKR_OUT   113
 
#define TISCI_DEV_BOARD0_BUS_PCIE1REFCLKP_OUT   114
 
#define TISCI_DEV_BOARD0_BUS_PRG2_RGMII1_RCLK_OUT   115
 
#define TISCI_DEV_BOARD0_BUS_SPI0CLK_OUT   116
 
#define TISCI_DEV_BOARD0_BUS_MCU_HYPERBUS_CLK_IN   117
 
#define TISCI_DEV_BOARD0_BUS_MCU_HYPERBUS_NCLK_IN   118
 
#define TISCI_DEV_R5FSS0_CORE0_CPU_CLK   0