Introduction

This file contains the definition of all the parameter IDs for PM, RM, Security.

Macros
#define	TISCI_PARAM_UNDEF (0xFFFFFFFFU)

#define	TISCI_MSG_VALUE_RM_NULL_RING_TYPE (0xFFFFu)

#define	TISCI_MSG_VALUE_RM_NULL_RING_INDEX (0xFFFFFFFFu)

#define	TISCI_MSG_VALUE_RM_NULL_RING_ADDR (0xFFFFFFFFu)

#define	TISCI_MSG_VALUE_RM_NULL_RING_COUNT (0xFFFFFFFFu)

#define	TISCI_MSG_VALUE_RM_NULL_RING_MODE (0xFFu)

#define	TISCI_MSG_VALUE_RM_NULL_RING_SIZE (0xFFu)

#define	TISCI_MSG_VALUE_RM_NULL_ORDER_ID (0xFFu)

#define	TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_TYPE (0xFFu)

#define	TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_INDEX (0xFFFFFFFFu)

#define	TISCI_ISC_CC_ID (160U)
	Special ISC ID to refer to compute cluster privid registers. More...

#define	SCICLIENT_ALLOWED_BOARDCFG_BASE_START (CSL_MCU_MSRAM0_RAM_BASE)

#define	SCICLIENT_ALLOWED_BOARDCFG_BASE_END (CSL_MCU_MSRAM0_RAM_BASE + CSL_MCU_MSRAM0_RAM_SIZE)

Sciclient Firmware ABI revisions
ABI revisions for compatibility check.
#define	SCICLIENT_FIRMWARE_ABI_MAJOR (3U)

#define	SCICLIENT_FIRMWARE_ABI_MINOR (1U)

Sciclient Context Ids
Context IDs for Sciclient_ConfigPrms_t .
#define	SCICLIENT_CONTEXT_R5_NONSEC_0 (0U)

#define	SCICLIENT_CONTEXT_R5_SEC_0 (1U)

#define	SCICLIENT_CONTEXT_R5_NONSEC_1 (2U)

#define	SCICLIENT_CONTEXT_R5_SEC_1 (3U)

#define	SCICLIENT_CONTEXT_A53_SEC_0 (4U)

#define	SCICLIENT_CONTEXT_A53_SEC_1 (5U)

#define	SCICLIENT_CONTEXT_A53_NONSEC_0 (6U)

#define	SCICLIENT_CONTEXT_A53_NONSEC_1 (7U)

#define	SCICLIENT_CONTEXT_A53_NONSEC_2 (8U)

#define	SCICLIENT_CONTEXT_A53_NONSEC_3 (9U)

#define	SCICLIENT_CONTEXT_A53_NONSEC_4 (10U)

#define	SCICLIENT_CONTEXT_A53_NONSEC_5 (11U)

#define	SCICLIENT_CONTEXT_GPU_NONSEC_0 (12U)

#define	SCICLIENT_CONTEXT_GPU_NONSEC_1 (13U)

#define	SCICLIENT_CONTEXT_ICSSG_NONSEC_0 (14U)

#define	SCICLIENT_CONTEXT_ICSSG_NONSEC_1 (15U)

#define	SCICLIENT_CONTEXT_ICSSG_NONSEC_2 (16U)

#define	SCICLIENT_CONTEXT_MAX_NUM (17U)

Sciclient Processor Ids
Processor IDs for the Processor Boot Configuration APIs.
#define	SCICLIENT_PROCID_A53_CL0_C0 (0x20U)

#define	SCICLIENT_PROCID_A53_CL0_C1 (0x21U)

#define	SCICLIENT_PROCID_A53_CL1_C0 (0x22U)

#define	SCICLIENT_PROCID_A53_CL1_C1 (0x23U)

#define	SCICLIENT_PROCID_R5_CL0_C0 (0x01U)

#define	SCICLIENT_PROCID_R5_CL0_C1 (0x02U)

IRQ source index start
Start offset of IRQ source index.
#define	TISCI_RINGACC0_OES_IRQ_SRC_IDX_START (0U)

#define	TISCI_RINGACC0_MON_IRQ_SRC_IDX_START (1024U)

#define	TISCI_RINGACC0_EOES_IRQ_SRC_IDX_START (2048U)

#define	TISCI_UDMAP0_TX_OES_IRQ_SRC_IDX_START (0U)

#define	TISCI_UDMAP0_TX_EOES_IRQ_SRC_IDX_START (256U)

#define	TISCI_UDMAP0_RX_OES_IRQ_SRC_IDX_START (512U)

#define	TISCI_UDMAP0_RX_EOES_IRQ_SRC_IDX_START (768U)

#define	TISCI_UDMAP0_RX_FLOW_EOES_IRQ_SRC_IDX_START (1024U)

MCU Pulsar IDs
MCU Device CPU IDs.
#define	SCICLIENT_DEV_MCU_R5FSS0_CORE0 (TISCI_DEV_MCU_ARMSS0_CPU0)

#define	SCICLIENT_DEV_MCU_R5FSS0_CORE1 (TISCI_DEV_MCU_ARMSS0_CPU1)

MCU Pulsar Processor IDs
MCU Device Processor IDs.
#define	SCICLIENT_DEV_MCU_R5FSS0_CORE0_PROCID (SCICLIENT_PROCID_R5_CL0_C0)

#define	SCICLIENT_DEV_MCU_R5FSS0_CORE1_PROCID (SCICLIENT_PROCID_R5_CL0_C1)

Macro Definition Documentation

◆ TISCI_PARAM_UNDEF

#define TISCI_PARAM_UNDEF (0xFFFFFFFFU)

Undefined Param Undefined

◆ SCICLIENT_FIRMWARE_ABI_MAJOR

#define SCICLIENT_FIRMWARE_ABI_MAJOR (3U)

◆ SCICLIENT_FIRMWARE_ABI_MINOR

#define SCICLIENT_FIRMWARE_ABI_MINOR (1U)

◆ SCICLIENT_CONTEXT_R5_NONSEC_0

#define SCICLIENT_CONTEXT_R5_NONSEC_0 (0U)

r5(Non Secure): Cortex R5 Context 0 on MCU island

◆ SCICLIENT_CONTEXT_R5_SEC_0

#define SCICLIENT_CONTEXT_R5_SEC_0 (1U)

r5(Secure): Cortex R5 Context 1 on MCU island(Boot)

◆ SCICLIENT_CONTEXT_R5_NONSEC_1

#define SCICLIENT_CONTEXT_R5_NONSEC_1 (2U)

r5(Non Secure): Cortex R5 Context 2 on MCU island

◆ SCICLIENT_CONTEXT_R5_SEC_1

#define SCICLIENT_CONTEXT_R5_SEC_1 (3U)

r5(Secure): Cortex R5 Context 3 on MCU island

◆ SCICLIENT_CONTEXT_A53_SEC_0

#define SCICLIENT_CONTEXT_A53_SEC_0 (4U)

a53(Secure): Cortex A53 context 0 on Main island

◆ SCICLIENT_CONTEXT_A53_SEC_1

#define SCICLIENT_CONTEXT_A53_SEC_1 (5U)

a53(Secure): Cortex A53 context 1 on Main island

◆ SCICLIENT_CONTEXT_A53_NONSEC_0

#define SCICLIENT_CONTEXT_A53_NONSEC_0 (6U)

a53(Non Secure): Cortex A53 context 2 on Main island

◆ SCICLIENT_CONTEXT_A53_NONSEC_1

#define SCICLIENT_CONTEXT_A53_NONSEC_1 (7U)

a53(Non Secure): Cortex A53 context 3 on Main island

◆ SCICLIENT_CONTEXT_A53_NONSEC_2

#define SCICLIENT_CONTEXT_A53_NONSEC_2 (8U)

a53(Non Secure): Cortex A53 context 4 on Main island

◆ SCICLIENT_CONTEXT_A53_NONSEC_3

#define SCICLIENT_CONTEXT_A53_NONSEC_3 (9U)

a53(Non Secure): Cortex A53 context 5 on Main island

◆ SCICLIENT_CONTEXT_A53_NONSEC_4

#define SCICLIENT_CONTEXT_A53_NONSEC_4 (10U)

a53(Non Secure): Cortex A53 context 6 on Main island

◆ SCICLIENT_CONTEXT_A53_NONSEC_5

#define SCICLIENT_CONTEXT_A53_NONSEC_5 (11U)

a53(Non Secure): Cortex A53 context 7 on Main island

◆ SCICLIENT_CONTEXT_GPU_NONSEC_0

#define SCICLIENT_CONTEXT_GPU_NONSEC_0 (12U)

gpu(Non Secure): SGX544 Context 0 on Main island

◆ SCICLIENT_CONTEXT_GPU_NONSEC_1

#define SCICLIENT_CONTEXT_GPU_NONSEC_1 (13U)

gpu(Non Secure): SGX544 Context 1 on Main island

◆ SCICLIENT_CONTEXT_ICSSG_NONSEC_0

#define SCICLIENT_CONTEXT_ICSSG_NONSEC_0 (14U)

icssg(Non Secure): ICSS Context 0 on Main island

◆ SCICLIENT_CONTEXT_ICSSG_NONSEC_1

#define SCICLIENT_CONTEXT_ICSSG_NONSEC_1 (15U)

icssg(Non Secure): ICSS Context 1 on Main island

◆ SCICLIENT_CONTEXT_ICSSG_NONSEC_2

#define SCICLIENT_CONTEXT_ICSSG_NONSEC_2 (16U)

icssg(Non Secure): ICSS Context 2 on Main island

◆ SCICLIENT_CONTEXT_MAX_NUM

#define SCICLIENT_CONTEXT_MAX_NUM (17U)

Total number of possible contexts for application.

◆ SCICLIENT_PROCID_A53_CL0_C0

#define SCICLIENT_PROCID_A53_CL0_C0 (0x20U)

COMPUTE_CLUSTER_MSMC0: (Cluster 0 Processor 0)

◆ SCICLIENT_PROCID_A53_CL0_C1

#define SCICLIENT_PROCID_A53_CL0_C1 (0x21U)

COMPUTE_CLUSTER_MSMC0: (Cluster 0 Processor 1)

◆ SCICLIENT_PROCID_A53_CL1_C0

#define SCICLIENT_PROCID_A53_CL1_C0 (0x22U)

COMPUTE_CLUSTER_MSMC0: (Cluster 1 Processor 0)

◆ SCICLIENT_PROCID_A53_CL1_C1

#define SCICLIENT_PROCID_A53_CL1_C1 (0x23U)

COMPUTE_CLUSTER_MSMC0: (Cluster 1 Processor 1)

◆ SCICLIENT_PROCID_R5_CL0_C0

#define SCICLIENT_PROCID_R5_CL0_C0 (0x01U)

MCU_SEC_MMR0: (Cluster 0 Processor 0)

◆ SCICLIENT_PROCID_R5_CL0_C1

#define SCICLIENT_PROCID_R5_CL0_C1 (0x02U)

MCU_SEC_MMR0: (Cluster 0 Processor 1)

◆ TISCI_MSG_VALUE_RM_NULL_RING_TYPE

#define TISCI_MSG_VALUE_RM_NULL_RING_TYPE (0xFFFFu)

-----------------— Resource Management Parameters ------------------—

◆ TISCI_MSG_VALUE_RM_NULL_RING_INDEX

#define TISCI_MSG_VALUE_RM_NULL_RING_INDEX (0xFFFFFFFFu)

◆ TISCI_MSG_VALUE_RM_NULL_RING_ADDR

#define TISCI_MSG_VALUE_RM_NULL_RING_ADDR (0xFFFFFFFFu)

◆ TISCI_MSG_VALUE_RM_NULL_RING_COUNT

#define TISCI_MSG_VALUE_RM_NULL_RING_COUNT (0xFFFFFFFFu)

◆ TISCI_MSG_VALUE_RM_NULL_RING_MODE

#define TISCI_MSG_VALUE_RM_NULL_RING_MODE (0xFFu)

The ring mode field of the RING_SIZE register is not modified if this value is used for: tisci_msg_rm_ring_cfg_req::mode

◆ TISCI_MSG_VALUE_RM_NULL_RING_SIZE

#define TISCI_MSG_VALUE_RM_NULL_RING_SIZE (0xFFu)

◆ TISCI_MSG_VALUE_RM_NULL_ORDER_ID

#define TISCI_MSG_VALUE_RM_NULL_ORDER_ID (0xFFu)

◆ TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_TYPE

#define TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_TYPE (0xFFu)

◆ TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_INDEX

#define TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_INDEX (0xFFFFFFFFu)

◆ TISCI_ISC_CC_ID

#define TISCI_ISC_CC_ID (160U)

Special ISC ID to refer to compute cluster privid registers.

◆ TISCI_RINGACC0_OES_IRQ_SRC_IDX_START

#define TISCI_RINGACC0_OES_IRQ_SRC_IDX_START (0U)

◆ TISCI_RINGACC0_MON_IRQ_SRC_IDX_START

#define TISCI_RINGACC0_MON_IRQ_SRC_IDX_START (1024U)

◆ TISCI_RINGACC0_EOES_IRQ_SRC_IDX_START

#define TISCI_RINGACC0_EOES_IRQ_SRC_IDX_START (2048U)

◆ TISCI_UDMAP0_TX_OES_IRQ_SRC_IDX_START

#define TISCI_UDMAP0_TX_OES_IRQ_SRC_IDX_START (0U)

◆ TISCI_UDMAP0_TX_EOES_IRQ_SRC_IDX_START

#define TISCI_UDMAP0_TX_EOES_IRQ_SRC_IDX_START (256U)

◆ TISCI_UDMAP0_RX_OES_IRQ_SRC_IDX_START

#define TISCI_UDMAP0_RX_OES_IRQ_SRC_IDX_START (512U)

◆ TISCI_UDMAP0_RX_EOES_IRQ_SRC_IDX_START

#define TISCI_UDMAP0_RX_EOES_IRQ_SRC_IDX_START (768U)

◆ TISCI_UDMAP0_RX_FLOW_EOES_IRQ_SRC_IDX_START

#define TISCI_UDMAP0_RX_FLOW_EOES_IRQ_SRC_IDX_START (1024U)

◆ SCICLIENT_DEV_MCU_R5FSS0_CORE0

#define SCICLIENT_DEV_MCU_R5FSS0_CORE0 (TISCI_DEV_MCU_ARMSS0_CPU0)

◆ SCICLIENT_DEV_MCU_R5FSS0_CORE1

#define SCICLIENT_DEV_MCU_R5FSS0_CORE1 (TISCI_DEV_MCU_ARMSS0_CPU1)

◆ SCICLIENT_DEV_MCU_R5FSS0_CORE0_PROCID

#define SCICLIENT_DEV_MCU_R5FSS0_CORE0_PROCID (SCICLIENT_PROCID_R5_CL0_C0)

◆ SCICLIENT_DEV_MCU_R5FSS0_CORE1_PROCID

#define SCICLIENT_DEV_MCU_R5FSS0_CORE1_PROCID (SCICLIENT_PROCID_R5_CL0_C1)

◆ SCICLIENT_ALLOWED_BOARDCFG_BASE_START

#define SCICLIENT_ALLOWED_BOARDCFG_BASE_START (CSL_MCU_MSRAM0_RAM_BASE)

Board config Base start address

◆ SCICLIENT_ALLOWED_BOARDCFG_BASE_END

#define SCICLIENT_ALLOWED_BOARDCFG_BASE_END (CSL_MCU_MSRAM0_RAM_BASE + CSL_MCU_MSRAM0_RAM_SIZE)

Board config Base end address