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#define | TISCI_MSG_FLAG_RESERVED0 TISCI_BIT(0) |
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#define | TISCI_MSG_FLAG_AOP TISCI_BIT(1) |
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#define | TISCI_MSG_FLAG_SEC TISCI_BIT(2) |
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#define | TISCI_MSG_FLAG_ACK TISCI_BIT(1) |
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#define | TISCI_MSG_VERSION (0x0002U) |
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#define | TISCI_MSG_BOOT_NOTIFICATION (0x000AU) |
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#define | TISCI_MSG_BOARD_CONFIG (0x000BU) |
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#define | TISCI_MSG_BOARD_CONFIG_RM (0x000CU) |
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#define | TISCI_MSG_BOARD_CONFIG_SECURITY (0x000DU) |
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#define | TISCI_MSG_BOARD_CONFIG_PM (0x000EU) |
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#define | TISCI_MSG_ENABLE_WDT (0x0000U) |
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#define | TISCI_MSG_WAKE_RESET (0x0001U) |
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#define | TISCI_MSG_WAKE_REASON (0x0003U) |
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#define | TISCI_MSG_GOODBYE (0x0004U) |
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#define | TISCI_MSG_SYS_RESET (0x0005U) |
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#define | TISCI_MSG_QUERY_MSMC (0x0020U) |
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#define | TISCI_MSG_GET_TRACE_CONFIG (0x0021U) |
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#define | TISCI_MSG_QUERY_FW_CAPS (0x0022U) |
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#define | TISCI_MSG_SET_CLOCK (0x0100U) |
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#define | TISCI_MSG_GET_CLOCK (0x0101U) |
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#define | TISCI_MSG_SET_CLOCK_PARENT (0x0102U) |
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#define | TISCI_MSG_GET_CLOCK_PARENT (0x0103U) |
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#define | TISCI_MSG_GET_NUM_CLOCK_PARENTS (0x0104U) |
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#define | TISCI_MSG_SET_FREQ (0x010cU) |
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#define | TISCI_MSG_QUERY_FREQ (0x010dU) |
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#define | TISCI_MSG_GET_FREQ (0x010eU) |
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#define | TISCI_MSG_SET_DEVICE (0x0200U) |
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#define | TISCI_MSG_GET_DEVICE (0x0201U) |
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#define | TISCI_MSG_SET_DEVICE_RESETS (0x0202U) |
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#define | TISCI_MSG_DEVICE_DROP_POWERUP_REF (0x0203U) |
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#define | TISCI_MSG_PREPARE_SLEEP (0x0300U) |
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#define | TISCI_MSG_ENTER_SLEEP (0x0301U) |
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#define | TISCI_MSG_SYNC_RESUME (0x0302U) |
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#define | TISCI_MSG_CONTINUE_RESUME (0x0303U) |
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#define | TISCI_MSG_CORE_RESUME (0x0304U) |
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#define | TISCI_MSG_ABORT_ENTER_SLEEP (0x0305U) |
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#define | TISCI_MSG_LPM_WAKE_REASON (0x0306U) |
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#define | TISCI_MSG_SET_IO_ISOLATION (0x0307U) |
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#define | TISCI_MSG_FIRMWARE_LOAD (0x8105U) |
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#define | MSG_FIRMWARE_LOAD_RESULT (0x8805U) |
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#define | TISCI_MSG_SET_FWL_REGION (0x9000U) |
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#define | TISCI_MSG_GET_FWL_REGION (0x9001U) |
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#define | TISCI_MSG_CHANGE_FWL_OWNER (0x9002U) |
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#define | TISCI_MSG_SA2UL_SET_DKEK (0x9003U) |
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#define | TISCI_MSG_SA2UL_RELEASE_DKEK (0x9004U) |
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#define | TISCI_MSG_KEYSTORE_IMPORT_SKEY (0x9005U) |
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#define | TISCI_MSG_KEYSTORE_ERASE_SKEY (0x9006U) |
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#define | TISCI_MSG_SEC_RESERVED_9007 (0x9007U) |
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#define | TISCI_MSG_SEC_RESERVED_9008 (0x9008U) |
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#define | TISCI_MSG_SET_ISC_REGION (0x9009U) |
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#define | TISCI_MSG_GET_ISC_REGION (0x900AU) |
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#define | TISCI_MSG_FWL_EXCP_NOTIFICATION (0x900BU) |
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#define | TISCI_MSG_OPEN_DEBUG_FWLS (0x900CU) |
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#define | TISCI_MSG_KEYSTORE_WRITE (0x900DU) |
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#define | TISCI_MSG_KEYSTORE_EXPORT_ALL (0x900EU) |
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#define | TISCI_MSG_KEYSTORE_IMPORT_ALL (0x900FU) |
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#define | TISCI_MSG_SEC_RESERVED_9010 (0x9010U) |
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#define | TISCI_MSG_SEC_RESERVED_9011 (0x9011U) |
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#define | TISCI_MSG_SEC_RESERVED_9012 (0x9012U) |
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#define | TISCI_MSG_SEC_RESERVED_9013 (0x9013U) |
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#define | TISCI_MSG_SEC_RESERVED_9014 (0x9014U) |
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#define | TISCI_MSG_SEC_RESERVED_9015 (0x9015U) |
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#define | TISCI_MSG_SEC_RESERVED_9016 (0x9016U) |
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#define | TISCI_MSG_SA2UL_AUTH_RES_ACQUIRE (0x9017U) |
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#define | TISCI_MSG_SA2UL_AUTH_RES_RELEASE (0x9018U) |
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#define | TISCI_MSG_SEC_RESERVED_9020 (0x9020U) |
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#define | TISCI_MSG_GET_SOC_UID (0x9021U) |
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#define | TISCI_MSG_READ_OTP_MMR (0x9022U) |
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#define | TISCI_MSG_WRITE_OTP_ROW (0x9023U) |
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#define | TISCI_MSG_LOCK_OTP_ROW (0x9024U) |
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#define | TISCI_MSG_SOFT_LOCK_OTP_WRITE_GLOBAL (0x9025U) |
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#define | TISCI_MSG_GET_OTP_ROW_LOCK_STATUS (0x9026U) |
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#define | TISCI_MSG_RSVD_OTP_1 (0x9027U) |
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#define | TISCI_MSG_RSVD_OTP_2 (0x9028U) |
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#define | TISCI_MSG_SA2UL_GET_DKEK (0x9029U) |
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#define | TISCI_MSG_SEC_HANDOVER (0x9030U) |
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#define | TISCI_MSG_KEY_WRITER (0x9031U) |
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#define | TISCI_MSG_WRITE_SWREV (0x9032U) |
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#define | TISCI_MSG_READ_SWREV (0x9033U) |
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#define | TISCI_MSG_READ_KEYCNT_KEYREV (0x9034U) |
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#define | TISCI_MSG_WRITE_KEYREV (0x9035U) |
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#define | TISCI_MSG_PROC_REQUEST (0xC000U) |
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#define | TISCI_MSG_PROC_RELEASE (0xC001U) |
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#define | TISCI_MSG_PROC_HANDOVER (0xC005U) |
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#define | TISCI_MSG_PROC_SET_CONFIG (0xC100U) |
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#define | TISCI_MSG_PROC_SET_CONTROL (0xC101U) |
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#define | TISCI_MSG_PROC_GET_STATUS (0xC400U) |
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#define | TISCI_MSG_PROC_WAIT_STATUS (0xC401U) |
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#define | TISCI_MSG_PROC_AUTH_BOOT (0xC120U) |
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#define | TISCI_MSG_RM_GET_RESOURCE_RANGE (0x1500U) |
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#define | TISCI_MSG_RM_IRQ_SET (0x1000U) |
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#define | TISCI_MSG_RM_IRQ_RELEASE (0x1001U) |
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#define | TISCI_MSG_RM_RESERVED_1100 (0x1100U) |
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#define | TISCI_MSG_RM_RESERVED_1101 (0x1101U) |
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#define | TISCI_MSG_RM_RESERVED_1102 (0x1102U) |
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#define | TISCI_MSG_RM_RESERVED_1103 (0x1103U) |
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#define | TISCI_MSG_RM_RING_CFG (0x1110U) |
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#define | TISCI_MSG_RM_RESERVED_1111 (0x1111U) |
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#define | TISCI_MSG_RM_RING_MON_CFG (0x1120U) |
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#define | TISCI_MSG_RM_RESERVED_1200 (0x1200U) |
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#define | TISCI_MSG_RM_RESERVED_1201 (0x1201U) |
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#define | TISCI_MSG_RM_UDMAP_TX_CH_CFG (0x1205U) |
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#define | TISCI_MSG_RM_RESERVED_1206 (0x1206U) |
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#define | TISCI_MSG_RM_RESERVED_1210 (0x1210U) |
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#define | TISCI_MSG_RM_RESERVED_1211 (0x1211U) |
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#define | TISCI_MSG_RM_UDMAP_RX_CH_CFG (0x1215U) |
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#define | TISCI_MSG_RM_RESERVED_1216 (0x1216U) |
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#define | TISCI_MSG_RM_RESERVED_1220 (0x1220U) |
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#define | TISCI_MSG_RM_RESERVED_1221 (0x1221U) |
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#define | TISCI_MSG_RM_UDMAP_FLOW_CFG (0x1230U) |
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#define | TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_CFG (0x1231U) |
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#define | TISCI_MSG_RM_RESERVED_1232 (0x1232U) |
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#define | TISCI_MSG_RM_RESERVED_1233 (0x1233U) |
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#define | TISCI_MSG_RM_UDMAP_FLOW_DELEGATE (0x1234U) |
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#define | TISCI_MSG_RM_UDMAP_GCFG_CFG (0x1240U) |
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#define | TISCI_MSG_RM_RESERVED_1241 (0x1241U) |
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#define | TISCI_MSG_RM_PSIL_PAIR (0x1280U) |
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#define | TISCI_MSG_RM_PSIL_UNPAIR (0x1281U) |
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#define | TISCI_MSG_RM_PSIL_READ (0x1282U) |
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#define | TISCI_MSG_RM_PSIL_WRITE (0x1283U) |
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#define | TISCI_MSG_RM_PROXY_CFG (0x1300U) |
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