Macros
#define	CSL_CAL_PER_CNT (1U)
	number of instances of CAL available More...

#define	CSL_CAL_PPI_CNT (2U)
	Defines the total number of PPI available per CAL. More...

#define	CSL_CAL_CMPLXIO_CNT (1U)
	Defines the total number of complex IO available per CAL. More...

#define	CSL_CAL_PIX_PROC_CTX_CNT (4U)
	Defines the total number of pixel processing context available per CAL. More...

#define	CSL_CAL_IRQ_NUM (71U)
	interrupt number for CAL. More...

#define	CSL_UART_PER_CNT (3U)
	Number of UART instances. More...

#define	CSL_MCSPI_PER_CNT (8U)
	Max Number of McSPI instances in a domain. More...

#define	CSL_MCSPI_CHAN_CNT (4U)
	Max Number of McSPI channels per instance. More...

#define	CSL_MCSPI_DOMAIN_CNT (2U)
	Number of domains contating McSPI instances. More...

#define	CSL_MCSPI_MCU_CNT (3U)
	Number of McSPI instances in MCU domain. More...

#define	CSL_MCSPI_MAIN_CNT (8U)
	Number of McSPI instances in MAIN domain. More...

#define	CSL_OSPI_PER_CNT (2U)
	Number of OSPI instances. More...

#define	CSL_OSPI_DOMAIN_CNT (2U)
	Number of domains contating OSPI instances. Second domain is not currently supported but kept as place holder for future use. More...

#define	CSL_EPWM_PER_CNT (9U)
	Number of ePWM instances. More...

#define	MCAN_MSG_RAM_MAX_WORD_COUNT (4352U)
	MCAN Maximum Message RAM words. More...

Core ID's of core or CPUs present on this SOC
Cache line size definitions
#define	CSL_CORE_ID_R5FSS0_0 (0U)

#define	CSL_CORE_ID_R5FSS0_1 (1U)

#define	CSL_CORE_ID_A53SS0_0 (2U)

#define	CSL_CORE_ID_A53SS0_1 (3U)

#define	CSL_CORE_ID_A53SS1_0 (4U)

#define	CSL_CORE_ID_A53SS1_1 (5U)

#define	CSL_CORE_ID_MAX (6U)

R5 Cluster Group IDs

#define	CSL_ARM_R5_CLUSTER_GROUP_ID_0 ((uint32_t) 0x00U)
	R5 Cluster Group ID0. More...

#define	CSL_ARM_R5_CLUSTER_GROUP_ID_1 ((uint32_t) 0x01U)
	R5 Cluster Group ID1. More...

R5 Core IDs

#define	CSL_ARM_R5_CPU_ID_0 ((uint32_t) 0x00U)
	R5 Core ID0. More...

#define	CSL_ARM_R5_CPU_ID_1 ((uint32_t) 0x01U)
	R5 Core ID1. More...

Macro Definition Documentation

◆ CSL_CAL_PER_CNT

#define CSL_CAL_PER_CNT (1U)

number of instances of CAL available

◆ CSL_CAL_PPI_CNT

#define CSL_CAL_PPI_CNT (2U)

Defines the total number of PPI available per CAL.

◆ CSL_CAL_CMPLXIO_CNT

#define CSL_CAL_CMPLXIO_CNT (1U)

Defines the total number of complex IO available per CAL.

◆ CSL_CAL_PIX_PROC_CTX_CNT

#define CSL_CAL_PIX_PROC_CTX_CNT (4U)

Defines the total number of pixel processing context available per CAL.

◆ CSL_CAL_IRQ_NUM

#define CSL_CAL_IRQ_NUM (71U)

interrupt number for CAL.

◆ CSL_UART_PER_CNT

#define CSL_UART_PER_CNT (3U)

Number of UART instances.

◆ CSL_MCSPI_PER_CNT

#define CSL_MCSPI_PER_CNT (8U)

Max Number of McSPI instances in a domain.

◆ CSL_MCSPI_CHAN_CNT

#define CSL_MCSPI_CHAN_CNT (4U)

Max Number of McSPI channels per instance.

◆ CSL_MCSPI_DOMAIN_CNT

#define CSL_MCSPI_DOMAIN_CNT (2U)

Number of domains contating McSPI instances.

◆ CSL_MCSPI_MCU_CNT

#define CSL_MCSPI_MCU_CNT (3U)

Number of McSPI instances in MCU domain.

◆ CSL_MCSPI_MAIN_CNT

#define CSL_MCSPI_MAIN_CNT (8U)

Number of McSPI instances in MAIN domain.

◆ CSL_OSPI_PER_CNT

#define CSL_OSPI_PER_CNT (2U)

Number of OSPI instances.

◆ CSL_OSPI_DOMAIN_CNT

#define CSL_OSPI_DOMAIN_CNT (2U)

Number of domains contating OSPI instances. Second domain is not currently supported but kept as place holder for future use.

◆ CSL_CORE_ID_R5FSS0_0

#define CSL_CORE_ID_R5FSS0_0 (0U)

◆ CSL_CORE_ID_R5FSS0_1

#define CSL_CORE_ID_R5FSS0_1 (1U)

◆ CSL_CORE_ID_A53SS0_0

#define CSL_CORE_ID_A53SS0_0 (2U)

◆ CSL_CORE_ID_A53SS0_1

#define CSL_CORE_ID_A53SS0_1 (3U)

◆ CSL_CORE_ID_A53SS1_0

#define CSL_CORE_ID_A53SS1_0 (4U)

◆ CSL_CORE_ID_A53SS1_1

#define CSL_CORE_ID_A53SS1_1 (5U)

◆ CSL_CORE_ID_MAX

#define CSL_CORE_ID_MAX (6U)

◆ CSL_ARM_R5_CLUSTER_GROUP_ID_0

#define CSL_ARM_R5_CLUSTER_GROUP_ID_0 ((uint32_t) 0x00U)

R5 Cluster Group ID0.

◆ CSL_ARM_R5_CLUSTER_GROUP_ID_1

#define CSL_ARM_R5_CLUSTER_GROUP_ID_1 ((uint32_t) 0x01U)

R5 Cluster Group ID1.

◆ CSL_ARM_R5_CPU_ID_0

#define CSL_ARM_R5_CPU_ID_0 ((uint32_t) 0x00U)

R5 Core ID0.

◆ CSL_ARM_R5_CPU_ID_1

#define CSL_ARM_R5_CPU_ID_1 ((uint32_t) 0x01U)

R5 Core ID1.

◆ CSL_EPWM_PER_CNT

#define CSL_EPWM_PER_CNT (9U)

Number of ePWM instances.

◆ MCAN_MSG_RAM_MAX_WORD_COUNT

#define MCAN_MSG_RAM_MAX_WORD_COUNT (4352U)

MCAN Maximum Message RAM words.

Macros