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AM65x MCU+ SDK
09.01.00
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Go to the documentation of this file.
34 #ifndef CSLR_SOC_DEFINES_H_
35 #define CSLR_SOC_DEFINES_H_
52 #define CSL_CAL_PER_CNT (1U)
54 #define CSL_CAL_PPI_CNT (2U)
56 #define CSL_CAL_CMPLXIO_CNT (1U)
59 #define CSL_CAL_PIX_PROC_CTX_CNT (4U)
62 #define CSL_CAL_IRQ_NUM (71U)
65 #define CSL_UART_PER_CNT (3U)
68 #define CSL_MCSPI_PER_CNT (8U)
71 #define CSL_MCSPI_CHAN_CNT (4U)
74 #define CSL_MCSPI_DOMAIN_CNT (2U)
77 #define CSL_MCSPI_MCU_CNT (3U)
80 #define CSL_MCSPI_MAIN_CNT (8U)
83 #define CSL_OSPI_PER_CNT (2U)
88 #define CSL_OSPI_DOMAIN_CNT (2U)
91 #if defined(__aarch64__)
92 #define CSL_CACHE_L1P_LINESIZE (64U)
93 #define CSL_CACHE_L1D_LINESIZE (64U)
94 #define CSL_CACHE_L2_LINESIZE (64U)
95 #elif (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R')
96 #define CSL_CACHE_L1P_LINESIZE (32U)
97 #define CSL_CACHE_L1D_LINESIZE (32U)
106 #define CSL_CORE_ID_R5FSS0_0 (0U)
107 #define CSL_CORE_ID_R5FSS0_1 (1U)
108 #define CSL_CORE_ID_A53SS0_0 (2U)
109 #define CSL_CORE_ID_A53SS0_1 (3U)
110 #define CSL_CORE_ID_A53SS1_0 (4U)
111 #define CSL_CORE_ID_A53SS1_1 (5U)
112 #define CSL_CORE_ID_MAX (6U)
122 #define CSL_ARM_R5_CLUSTER_GROUP_ID_0 ((uint32_t) 0x00U)
124 #define CSL_ARM_R5_CLUSTER_GROUP_ID_1 ((uint32_t) 0x01U)
134 #define CSL_ARM_R5_CPU_ID_0 ((uint32_t) 0x00U)
136 #define CSL_ARM_R5_CPU_ID_1 ((uint32_t) 0x01U)
140 #define CSL_EPWM_PER_CNT (9U)
145 #define MCAN_MSG_RAM_MAX_WORD_COUNT (4352U)