sciclient_irq_rm.c File Reference

Introduction

File containing the AM64x specific interrupt management data for RM.

Variables
uint8_t	vint_usage_count_DMASS0_INTAGGR_0 [184] = {0}
static struct Sciclient_rmIaUsedMapping	rom_usage_DMASS0_INTAGGR_0 [5U]
struct Sciclient_rmIaInst	gRmIaInstances [SCICLIENT_RM_IA_NUM_INST]
struct Sciclient_rmIrInst	gRmIrInstances [SCICLIENT_RM_IR_NUM_INST]
const struct Sciclient_rmIrqIf	CMP_EVENT_INTROUTER0_outp_0_15_to_GICSS0_spi_48_63
const struct Sciclient_rmIrqIf	CMP_EVENT_INTROUTER0_outp_16_23_to_R5FSS0_CORE0_intr_48_55
const struct Sciclient_rmIrqIf	CMP_EVENT_INTROUTER0_outp_16_23_to_R5FSS0_CORE1_intr_48_55
const struct Sciclient_rmIrqIf	CMP_EVENT_INTROUTER0_outp_24_31_to_R5FSS1_CORE0_intr_48_55
const struct Sciclient_rmIrqIf	CMP_EVENT_INTROUTER0_outp_24_31_to_R5FSS1_CORE1_intr_48_55
const struct Sciclient_rmIrqIf	CMP_EVENT_INTROUTER0_outp_32_39_to_DMASS0_INTAGGR_0_intaggr_levi_pend_0_7
const struct Sciclient_rmIrqIf *const	tisci_if_CMP_EVENT_INTROUTER0 []
static const struct Sciclient_rmIrqNode	tisci_irq_CMP_EVENT_INTROUTER0
const struct Sciclient_rmIrqIf	MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_GICSS0_spi_32_47
const struct Sciclient_rmIrqIf	MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS0_CORE0_intr_32_47
const struct Sciclient_rmIrqIf	MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS0_CORE1_intr_32_47
const struct Sciclient_rmIrqIf	MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS1_CORE0_intr_32_47
const struct Sciclient_rmIrqIf	MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS1_CORE1_intr_32_47
const struct Sciclient_rmIrqIf	MAIN_GPIOMUX_INTROUTER0_outp_30_37_to_DMASS0_INTAGGR_0_intaggr_levi_pend_16_23
const struct Sciclient_rmIrqIf	MAIN_GPIOMUX_INTROUTER0_outp_16_17_to_DMASS0_INTAGGR_0_intaggr_levi_pend_24_25
const struct Sciclient_rmIrqIf	MAIN_GPIOMUX_INTROUTER0_outp_18_23_to_PRU_ICSSG0_pr1_iep0_cap_intr_req_4_9
const struct Sciclient_rmIrqIf	MAIN_GPIOMUX_INTROUTER0_outp_24_29_to_PRU_ICSSG0_pr1_iep1_cap_intr_req_10_15
const struct Sciclient_rmIrqIf	MAIN_GPIOMUX_INTROUTER0_outp_38_45_to_PRU_ICSSG0_pr1_slv_intr_46_53
const struct Sciclient_rmIrqIf	MAIN_GPIOMUX_INTROUTER0_outp_18_23_to_PRU_ICSSG1_pr1_iep0_cap_intr_req_4_9
const struct Sciclient_rmIrqIf	MAIN_GPIOMUX_INTROUTER0_outp_24_29_to_PRU_ICSSG1_pr1_iep1_cap_intr_req_10_15
const struct Sciclient_rmIrqIf	MAIN_GPIOMUX_INTROUTER0_outp_46_53_to_PRU_ICSSG1_pr1_slv_intr_46_53
const struct Sciclient_rmIrqIf *const	tisci_if_MAIN_GPIOMUX_INTROUTER0 []
static const struct Sciclient_rmIrqNode	tisci_irq_MAIN_GPIOMUX_INTROUTER0
const struct Sciclient_rmIrqIf	MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_GICSS0_spi_104_107
const struct Sciclient_rmIrqIf	MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS0_CORE0_intr_104_107
const struct Sciclient_rmIrqIf	MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS0_CORE1_intr_104_107
const struct Sciclient_rmIrqIf	MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS1_CORE0_intr_104_107
const struct Sciclient_rmIrqIf	MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS1_CORE1_intr_104_107
const struct Sciclient_rmIrqIf	MCU_MCU_GPIOMUX_INTROUTER0_outp_4_7_to_MCU_M4FSS0_CORE0_nvic_0_3
const struct Sciclient_rmIrqIf	MCU_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_MCU_ESM0_esm_pls_event0_88_91
const struct Sciclient_rmIrqIf	MCU_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_MCU_ESM0_esm_pls_event1_92_95
const struct Sciclient_rmIrqIf	MCU_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_MCU_ESM0_esm_pls_event2_96_99
const struct Sciclient_rmIrqIf *const	tisci_if_MCU_MCU_GPIOMUX_INTROUTER0 []
static const struct Sciclient_rmIrqNode	tisci_irq_MCU_MCU_GPIOMUX_INTROUTER0
const struct Sciclient_rmIrqIf	TIMESYNC_EVENT_INTROUTER0_outl_0_7_to_DMASS0_INTAGGR_0_intaggr_levi_pend_8_15
const struct Sciclient_rmIrqIf	TIMESYNC_EVENT_INTROUTER0_outl_8_8_to_PRU_ICSSG0_pr1_edc0_latch0_in_0_0
const struct Sciclient_rmIrqIf	TIMESYNC_EVENT_INTROUTER0_outl_9_9_to_PRU_ICSSG0_pr1_edc0_latch1_in_1_1
const struct Sciclient_rmIrqIf	TIMESYNC_EVENT_INTROUTER0_outl_10_10_to_PRU_ICSSG0_pr1_edc1_latch0_in_2_2
const struct Sciclient_rmIrqIf	TIMESYNC_EVENT_INTROUTER0_outl_11_11_to_PRU_ICSSG0_pr1_edc1_latch1_in_3_3
const struct Sciclient_rmIrqIf	TIMESYNC_EVENT_INTROUTER0_outl_12_12_to_PRU_ICSSG1_pr1_edc0_latch0_in_0_0
const struct Sciclient_rmIrqIf	TIMESYNC_EVENT_INTROUTER0_outl_13_13_to_PRU_ICSSG1_pr1_edc0_latch1_in_1_1
const struct Sciclient_rmIrqIf	TIMESYNC_EVENT_INTROUTER0_outl_14_14_to_PRU_ICSSG1_pr1_edc1_latch0_in_2_2
const struct Sciclient_rmIrqIf	TIMESYNC_EVENT_INTROUTER0_outl_15_15_to_PRU_ICSSG1_pr1_edc1_latch1_in_3_3
const struct Sciclient_rmIrqIf	TIMESYNC_EVENT_INTROUTER0_outl_16_16_to_CPTS0_cpts_hw1_push_0_0
const struct Sciclient_rmIrqIf	TIMESYNC_EVENT_INTROUTER0_outl_17_17_to_CPTS0_cpts_hw2_push_1_1
const struct Sciclient_rmIrqIf	TIMESYNC_EVENT_INTROUTER0_outl_18_18_to_CPTS0_cpts_hw3_push_2_2
const struct Sciclient_rmIrqIf	TIMESYNC_EVENT_INTROUTER0_outl_19_19_to_CPTS0_cpts_hw4_push_3_3
const struct Sciclient_rmIrqIf	TIMESYNC_EVENT_INTROUTER0_outl_20_20_to_CPTS0_cpts_hw5_push_4_4
const struct Sciclient_rmIrqIf	TIMESYNC_EVENT_INTROUTER0_outl_21_21_to_CPTS0_cpts_hw6_push_5_5
const struct Sciclient_rmIrqIf	TIMESYNC_EVENT_INTROUTER0_outl_22_22_to_CPTS0_cpts_hw7_push_6_6
const struct Sciclient_rmIrqIf	TIMESYNC_EVENT_INTROUTER0_outl_23_23_to_CPTS0_cpts_hw8_push_7_7
const struct Sciclient_rmIrqIf	TIMESYNC_EVENT_INTROUTER0_outl_29_29_to_PCIE0_pcie_cpts_hw2_push_0_0
const struct Sciclient_rmIrqIf	TIMESYNC_EVENT_INTROUTER0_outl_30_30_to_CPSW0_cpts_hw1_push_0_0
const struct Sciclient_rmIrqIf	TIMESYNC_EVENT_INTROUTER0_outl_31_31_to_CPSW0_cpts_hw2_push_1_1
const struct Sciclient_rmIrqIf	TIMESYNC_EVENT_INTROUTER0_outl_32_32_to_CPSW0_cpts_hw3_push_2_2
const struct Sciclient_rmIrqIf	TIMESYNC_EVENT_INTROUTER0_outl_33_33_to_CPSW0_cpts_hw4_push_3_3
const struct Sciclient_rmIrqIf	TIMESYNC_EVENT_INTROUTER0_outl_34_34_to_CPSW0_cpts_hw5_push_4_4
const struct Sciclient_rmIrqIf	TIMESYNC_EVENT_INTROUTER0_outl_35_35_to_CPSW0_cpts_hw6_push_5_5
const struct Sciclient_rmIrqIf	TIMESYNC_EVENT_INTROUTER0_outl_36_36_to_CPSW0_cpts_hw7_push_6_6
const struct Sciclient_rmIrqIf	TIMESYNC_EVENT_INTROUTER0_outl_37_37_to_CPSW0_cpts_hw8_push_7_7
const struct Sciclient_rmIrqIf *const	tisci_if_TIMESYNC_EVENT_INTROUTER0 []
static const struct Sciclient_rmIrqNode	tisci_irq_TIMESYNC_EVENT_INTROUTER0
const struct Sciclient_rmIrqIf	CPSW0_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_80_80
const struct Sciclient_rmIrqIf	CPSW0_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_21_21
const struct Sciclient_rmIrqIf	CPSW0_cpts_genf1_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_22_22
const struct Sciclient_rmIrqIf	CPSW0_cpts_sync_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_34_34
const struct Sciclient_rmIrqIf *const	tisci_if_CPSW0 []
static const struct Sciclient_rmIrqNode	tisci_irq_CPSW0
const struct Sciclient_rmIrqIf	DMASS0_INTAGGR_0_intaggr_vintr_pend_0_39_to_GICSS0_spi_64_103
const struct Sciclient_rmIrqIf	DMASS0_INTAGGR_0_intaggr_vintr_pend_72_79_to_R5FSS0_CORE0_intr_8_15
const struct Sciclient_rmIrqIf	DMASS0_INTAGGR_0_intaggr_vintr_pend_40_71_to_R5FSS0_CORE0_intr_64_95
const struct Sciclient_rmIrqIf	DMASS0_INTAGGR_0_intaggr_vintr_pend_80_87_to_R5FSS0_CORE1_intr_8_15
const struct Sciclient_rmIrqIf	DMASS0_INTAGGR_0_intaggr_vintr_pend_40_71_to_R5FSS0_CORE1_intr_64_95
const struct Sciclient_rmIrqIf	DMASS0_INTAGGR_0_intaggr_vintr_pend_120_127_to_R5FSS1_CORE0_intr_8_15
const struct Sciclient_rmIrqIf	DMASS0_INTAGGR_0_intaggr_vintr_pend_88_119_to_R5FSS1_CORE0_intr_64_95
const struct Sciclient_rmIrqIf	DMASS0_INTAGGR_0_intaggr_vintr_pend_128_135_to_R5FSS1_CORE1_intr_8_15
const struct Sciclient_rmIrqIf	DMASS0_INTAGGR_0_intaggr_vintr_pend_88_119_to_R5FSS1_CORE1_intr_64_95
const struct Sciclient_rmIrqIf	DMASS0_INTAGGR_0_intaggr_vintr_pend_152_159_to_PRU_ICSSG0_pr1_slv_intr_16_23
const struct Sciclient_rmIrqIf	DMASS0_INTAGGR_0_intaggr_vintr_pend_160_167_to_PRU_ICSSG1_pr1_slv_intr_16_23
const struct Sciclient_rmIrqIf	DMASS0_INTAGGR_0_intaggr_vintr_pend_168_183_to_MCU_M4FSS0_CORE0_nvic_32_47
const struct Sciclient_rmIrqIf *const	tisci_if_DMASS0_INTAGGR_0 []
static const struct Sciclient_rmIrqNode	tisci_irq_DMASS0_INTAGGR_0
const struct Sciclient_rmIrqIf	TIMER0_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_0_0
const struct Sciclient_rmIrqIf *const	tisci_if_TIMER0 []
static const struct Sciclient_rmIrqNode	tisci_irq_TIMER0
const struct Sciclient_rmIrqIf	TIMER1_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_1_1
const struct Sciclient_rmIrqIf *const	tisci_if_TIMER1 []
static const struct Sciclient_rmIrqNode	tisci_irq_TIMER1
const struct Sciclient_rmIrqIf	TIMER2_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_2_2
const struct Sciclient_rmIrqIf *const	tisci_if_TIMER2 []
static const struct Sciclient_rmIrqNode	tisci_irq_TIMER2
const struct Sciclient_rmIrqIf	TIMER3_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_3_3
const struct Sciclient_rmIrqIf *const	tisci_if_TIMER3 []
static const struct Sciclient_rmIrqNode	tisci_irq_TIMER3
const struct Sciclient_rmIrqIf	GTC0_gtc_push_event_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_36_36
const struct Sciclient_rmIrqIf *const	tisci_if_GTC0 []
static const struct Sciclient_rmIrqNode	tisci_irq_GTC0
const struct Sciclient_rmIrqIf	GPIO0_gpio_0_89_to_MAIN_GPIOMUX_INTROUTER0_in_0_89
const struct Sciclient_rmIrqIf	GPIO0_gpio_bank_90_98_to_MAIN_GPIOMUX_INTROUTER0_in_190_198
const struct Sciclient_rmIrqIf *const	tisci_if_GPIO0 []
static const struct Sciclient_rmIrqNode	tisci_irq_GPIO0
const struct Sciclient_rmIrqIf	GPIO1_gpio_0_89_to_MAIN_GPIOMUX_INTROUTER0_in_90_179
const struct Sciclient_rmIrqIf	GPIO1_gpio_bank_90_98_to_MAIN_GPIOMUX_INTROUTER0_in_180_188
const struct Sciclient_rmIrqIf *const	tisci_if_GPIO1 []
static const struct Sciclient_rmIrqNode	tisci_irq_GPIO1
const struct Sciclient_rmIrqIf	MCU_GPIO0_gpio_0_29_to_MCU_MCU_GPIOMUX_INTROUTER0_in_0_29
const struct Sciclient_rmIrqIf	MCU_GPIO0_gpio_bank_30_31_to_MCU_MCU_GPIOMUX_INTROUTER0_in_30_31
const struct Sciclient_rmIrqIf *const	tisci_if_MCU_GPIO0 []
static const struct Sciclient_rmIrqNode	tisci_irq_MCU_GPIO0
const struct Sciclient_rmIrqIf	GPMC0_gpmc_sdmareq_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_29_29
const struct Sciclient_rmIrqIf *const	tisci_if_GPMC0 []
static const struct Sciclient_rmIrqNode	tisci_irq_GPMC0
const struct Sciclient_rmIrqIf	PRU_ICSSG0_pr1_edc0_sync0_out_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_25_25
const struct Sciclient_rmIrqIf	PRU_ICSSG0_pr1_edc0_sync1_out_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_26_26
const struct Sciclient_rmIrqIf	PRU_ICSSG0_pr1_edc1_sync0_out_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_27_27
const struct Sciclient_rmIrqIf	PRU_ICSSG0_pr1_edc1_sync1_out_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_28_28
const struct Sciclient_rmIrqIf	PRU_ICSSG0_pr1_host_intr_req_4_11_to_CMP_EVENT_INTROUTER0_in_0_7
const struct Sciclient_rmIrqIf	PRU_ICSSG0_pr1_iep0_cmp_intr_req_12_27_to_CMP_EVENT_INTROUTER0_in_16_31
const struct Sciclient_rmIrqIf	PRU_ICSSG0_pr1_iep1_cmp_intr_req_28_43_to_CMP_EVENT_INTROUTER0_in_32_47
const struct Sciclient_rmIrqIf *const	tisci_if_PRU_ICSSG0 []
static const struct Sciclient_rmIrqNode	tisci_irq_PRU_ICSSG0
const struct Sciclient_rmIrqIf	PRU_ICSSG1_pr1_edc0_sync0_out_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_29_29
const struct Sciclient_rmIrqIf	PRU_ICSSG1_pr1_edc0_sync1_out_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_30_30
const struct Sciclient_rmIrqIf	PRU_ICSSG1_pr1_edc1_sync0_out_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_31_31
const struct Sciclient_rmIrqIf	PRU_ICSSG1_pr1_edc1_sync1_out_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_32_32
const struct Sciclient_rmIrqIf	PRU_ICSSG1_pr1_host_intr_req_4_11_to_CMP_EVENT_INTROUTER0_in_8_15
const struct Sciclient_rmIrqIf	PRU_ICSSG1_pr1_iep0_cmp_intr_req_12_27_to_CMP_EVENT_INTROUTER0_in_48_63
const struct Sciclient_rmIrqIf	PRU_ICSSG1_pr1_iep1_cmp_intr_req_28_43_to_CMP_EVENT_INTROUTER0_in_64_79
const struct Sciclient_rmIrqIf *const	tisci_if_PRU_ICSSG1 []
static const struct Sciclient_rmIrqNode	tisci_irq_PRU_ICSSG1
const struct Sciclient_rmIrqIf	CPTS0_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_82_82
const struct Sciclient_rmIrqIf	CPTS0_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_16_16
const struct Sciclient_rmIrqIf	CPTS0_cpts_genf1_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_17_17
const struct Sciclient_rmIrqIf	CPTS0_cpts_genf2_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_18_18
const struct Sciclient_rmIrqIf	CPTS0_cpts_genf3_4_4_to_TIMESYNC_EVENT_INTROUTER0_in_19_19
const struct Sciclient_rmIrqIf	CPTS0_cpts_genf4_5_5_to_TIMESYNC_EVENT_INTROUTER0_in_20_20
const struct Sciclient_rmIrqIf	CPTS0_cpts_genf5_6_6_to_TIMESYNC_EVENT_INTROUTER0_in_24_24
const struct Sciclient_rmIrqIf	CPTS0_cpts_sync_7_7_to_TIMESYNC_EVENT_INTROUTER0_in_35_35
const struct Sciclient_rmIrqIf *const	tisci_if_CPTS0 []
static const struct Sciclient_rmIrqNode	tisci_irq_CPTS0
const struct Sciclient_rmIrqIf	EPWM0_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_39_39
const struct Sciclient_rmIrqIf *const	tisci_if_EPWM0 []
static const struct Sciclient_rmIrqNode	tisci_irq_EPWM0
const struct Sciclient_rmIrqIf	EPWM3_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_40_40
const struct Sciclient_rmIrqIf *const	tisci_if_EPWM3 []
static const struct Sciclient_rmIrqNode	tisci_irq_EPWM3
const struct Sciclient_rmIrqIf	EPWM6_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_41_41
const struct Sciclient_rmIrqIf *const	tisci_if_EPWM6 []
static const struct Sciclient_rmIrqNode	tisci_irq_EPWM6
const struct Sciclient_rmIrqIf	PCIE0_pcie_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_81_81
const struct Sciclient_rmIrqIf	PCIE0_pcie_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_23_23
const struct Sciclient_rmIrqIf	PCIE0_pcie_cpts_sync_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_33_33
const struct Sciclient_rmIrqIf	PCIE0_pcie_cpts_hw1_push_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_37_37
const struct Sciclient_rmIrqIf	PCIE0_pcie_ptm_valid_pulse_4_4_to_TIMESYNC_EVENT_INTROUTER0_in_38_38
const struct Sciclient_rmIrqIf *const	tisci_if_PCIE0 []
static const struct Sciclient_rmIrqNode	tisci_irq_PCIE0
const struct Sciclient_rmIrqNode *const	gRmIrqTree []
const uint32_t	gRmIrqTreeCount = sizeof(gRmIrqTree)/sizeof(gRmIrqTree[0])

Variable Documentation

vint_usage_count_DMASS0_INTAGGR_0

uint8_t vint_usage_count_DMASS0_INTAGGR_0[184] = {0}

rom_usage_DMASS0_INTAGGR_0

struct Sciclient_rmIaUsedMapping rom_usage_DMASS0_INTAGGR_0[5U]

static

Initial value:

= {
    {
        .event = 20U,
        .cleared = false,
    },
    {
        .event = 21U,
        .cleared = false,
    },
    {
        .event = 22U,
        .cleared = false,
    },
    {
        .event = 23U,
        .cleared = false,
    },
    {
        .event = 30U,
        .cleared = false,
    },
}

gRmIaInstances

struct Sciclient_rmIaInst gRmIaInstances[SCICLIENT_RM_IA_NUM_INST]

Initial value:

=
{
    {
        .dev_id             = TISCI_DEV_DMASS0_INTAGGR_0,
        .imap               = 0x48100000,
        .sevt_offset        = 0u,
        .n_sevt             = 1536u,
        .n_vint             = 184,
        .vint_usage_count   = &vint_usage_count_DMASS0_INTAGGR_0[0],
        .v0_b0_evt          = SCICLIENT_RM_IA_GENERIC_EVT_RESETVAL,
        .rom_usage          = &rom_usage_DMASS0_INTAGGR_0[0U],
        .n_rom_usage        = 5,
    },
}

gRmIrInstances

struct Sciclient_rmIrInst gRmIrInstances[SCICLIENT_RM_IR_NUM_INST]

CMP_EVENT_INTROUTER0_outp_0_15_to_GICSS0_spi_48_63

const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_0_15_to_GICSS0_spi_48_63

Initial value:

= {
    .lbase = 0,
    .len = 16,
    .rid = TISCI_DEV_GICSS0,
    .rbase = 48,
}

CMP_EVENT_INTROUTER0_outp_16_23_to_R5FSS0_CORE0_intr_48_55

const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_16_23_to_R5FSS0_CORE0_intr_48_55

Initial value:

= {
    .lbase = 16,
    .len = 8,
    .rid = TISCI_DEV_R5FSS0_CORE0,
    .rbase = 48,
}

CMP_EVENT_INTROUTER0_outp_16_23_to_R5FSS0_CORE1_intr_48_55

const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_16_23_to_R5FSS0_CORE1_intr_48_55

Initial value:

= {
    .lbase = 16,
    .len = 8,
    .rid = TISCI_DEV_R5FSS0_CORE1,
    .rbase = 48,
}

CMP_EVENT_INTROUTER0_outp_24_31_to_R5FSS1_CORE0_intr_48_55

const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_24_31_to_R5FSS1_CORE0_intr_48_55

Initial value:

= {
    .lbase = 24,
    .len = 8,
    .rid = TISCI_DEV_R5FSS1_CORE0,
    .rbase = 48,
}

CMP_EVENT_INTROUTER0_outp_24_31_to_R5FSS1_CORE1_intr_48_55

const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_24_31_to_R5FSS1_CORE1_intr_48_55

Initial value:

= {
    .lbase = 24,
    .len = 8,
    .rid = TISCI_DEV_R5FSS1_CORE1,
    .rbase = 48,
}

CMP_EVENT_INTROUTER0_outp_32_39_to_DMASS0_INTAGGR_0_intaggr_levi_pend_0_7

const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_32_39_to_DMASS0_INTAGGR_0_intaggr_levi_pend_0_7

Initial value:

= {
    .lbase = 32,
    .len = 8,
    .rid = TISCI_DEV_DMASS0_INTAGGR_0,
    .rbase = 0,
}

tisci_if_CMP_EVENT_INTROUTER0

const struct Sciclient_rmIrqIf* const tisci_if_CMP_EVENT_INTROUTER0[]

Initial value:

= {
    &CMP_EVENT_INTROUTER0_outp_0_15_to_GICSS0_spi_48_63,
    &CMP_EVENT_INTROUTER0_outp_16_23_to_R5FSS0_CORE0_intr_48_55,
    &CMP_EVENT_INTROUTER0_outp_16_23_to_R5FSS0_CORE1_intr_48_55,
    &CMP_EVENT_INTROUTER0_outp_24_31_to_R5FSS1_CORE0_intr_48_55,
    &CMP_EVENT_INTROUTER0_outp_24_31_to_R5FSS1_CORE1_intr_48_55,
    &CMP_EVENT_INTROUTER0_outp_32_39_to_DMASS0_INTAGGR_0_intaggr_levi_pend_0_7,
}

tisci_irq_CMP_EVENT_INTROUTER0

const struct Sciclient_rmIrqNode tisci_irq_CMP_EVENT_INTROUTER0

static

Initial value:

= {
    .id = TISCI_DEV_CMP_EVENT_INTROUTER0,
    .n_if = 6,
    .p_if = &tisci_if_CMP_EVENT_INTROUTER0[0],
}

MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_GICSS0_spi_32_47

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_GICSS0_spi_32_47

Initial value:

= {
    .lbase = 0,
    .len = 16,
    .rid = TISCI_DEV_GICSS0,
    .rbase = 32,
}

MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS0_CORE0_intr_32_47

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS0_CORE0_intr_32_47

Initial value:

= {
    .lbase = 0,
    .len = 16,
    .rid = TISCI_DEV_R5FSS0_CORE0,
    .rbase = 32,
}

MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS0_CORE1_intr_32_47

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS0_CORE1_intr_32_47

Initial value:

= {
    .lbase = 0,
    .len = 16,
    .rid = TISCI_DEV_R5FSS0_CORE1,
    .rbase = 32,
}

MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS1_CORE0_intr_32_47

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS1_CORE0_intr_32_47

Initial value:

= {
    .lbase = 0,
    .len = 16,
    .rid = TISCI_DEV_R5FSS1_CORE0,
    .rbase = 32,
}

MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS1_CORE1_intr_32_47

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS1_CORE1_intr_32_47

Initial value:

= {
    .lbase = 0,
    .len = 16,
    .rid = TISCI_DEV_R5FSS1_CORE1,
    .rbase = 32,
}

MAIN_GPIOMUX_INTROUTER0_outp_30_37_to_DMASS0_INTAGGR_0_intaggr_levi_pend_16_23

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_30_37_to_DMASS0_INTAGGR_0_intaggr_levi_pend_16_23

Initial value:

= {
    .lbase = 30,
    .len = 8,
    .rid = TISCI_DEV_DMASS0_INTAGGR_0,
    .rbase = 16,
}

MAIN_GPIOMUX_INTROUTER0_outp_16_17_to_DMASS0_INTAGGR_0_intaggr_levi_pend_24_25

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_16_17_to_DMASS0_INTAGGR_0_intaggr_levi_pend_24_25

Initial value:

= {
    .lbase = 16,
    .len = 2,
    .rid = TISCI_DEV_DMASS0_INTAGGR_0,
    .rbase = 24,
}

MAIN_GPIOMUX_INTROUTER0_outp_18_23_to_PRU_ICSSG0_pr1_iep0_cap_intr_req_4_9

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_18_23_to_PRU_ICSSG0_pr1_iep0_cap_intr_req_4_9

Initial value:

= {
    .lbase = 18,
    .len = 6,
    .rid = TISCI_DEV_PRU_ICSSG0,
    .rbase = 4,
}

MAIN_GPIOMUX_INTROUTER0_outp_24_29_to_PRU_ICSSG0_pr1_iep1_cap_intr_req_10_15

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_24_29_to_PRU_ICSSG0_pr1_iep1_cap_intr_req_10_15

Initial value:

= {
    .lbase = 24,
    .len = 6,
    .rid = TISCI_DEV_PRU_ICSSG0,
    .rbase = 10,
}

MAIN_GPIOMUX_INTROUTER0_outp_38_45_to_PRU_ICSSG0_pr1_slv_intr_46_53

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_38_45_to_PRU_ICSSG0_pr1_slv_intr_46_53

Initial value:

= {
    .lbase = 38,
    .len = 8,
    .rid = TISCI_DEV_PRU_ICSSG0,
    .rbase = 46,
}

MAIN_GPIOMUX_INTROUTER0_outp_18_23_to_PRU_ICSSG1_pr1_iep0_cap_intr_req_4_9

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_18_23_to_PRU_ICSSG1_pr1_iep0_cap_intr_req_4_9

Initial value:

= {
    .lbase = 18,
    .len = 6,
    .rid = TISCI_DEV_PRU_ICSSG1,
    .rbase = 4,
}

MAIN_GPIOMUX_INTROUTER0_outp_24_29_to_PRU_ICSSG1_pr1_iep1_cap_intr_req_10_15

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_24_29_to_PRU_ICSSG1_pr1_iep1_cap_intr_req_10_15

Initial value:

= {
    .lbase = 24,
    .len = 6,
    .rid = TISCI_DEV_PRU_ICSSG1,
    .rbase = 10,
}

MAIN_GPIOMUX_INTROUTER0_outp_46_53_to_PRU_ICSSG1_pr1_slv_intr_46_53

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_46_53_to_PRU_ICSSG1_pr1_slv_intr_46_53

Initial value:

= {
    .lbase = 46,
    .len = 8,
    .rid = TISCI_DEV_PRU_ICSSG1,
    .rbase = 46,
}

tisci_if_MAIN_GPIOMUX_INTROUTER0

const struct Sciclient_rmIrqIf* const tisci_if_MAIN_GPIOMUX_INTROUTER0[]

Initial value:

= {
    &MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_GICSS0_spi_32_47,
    &MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS0_CORE0_intr_32_47,
    &MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS0_CORE1_intr_32_47,
    &MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS1_CORE0_intr_32_47,
    &MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS1_CORE1_intr_32_47,
    &MAIN_GPIOMUX_INTROUTER0_outp_30_37_to_DMASS0_INTAGGR_0_intaggr_levi_pend_16_23,
    &MAIN_GPIOMUX_INTROUTER0_outp_16_17_to_DMASS0_INTAGGR_0_intaggr_levi_pend_24_25,
    &MAIN_GPIOMUX_INTROUTER0_outp_18_23_to_PRU_ICSSG0_pr1_iep0_cap_intr_req_4_9,
    &MAIN_GPIOMUX_INTROUTER0_outp_24_29_to_PRU_ICSSG0_pr1_iep1_cap_intr_req_10_15,
    &MAIN_GPIOMUX_INTROUTER0_outp_38_45_to_PRU_ICSSG0_pr1_slv_intr_46_53,
    &MAIN_GPIOMUX_INTROUTER0_outp_18_23_to_PRU_ICSSG1_pr1_iep0_cap_intr_req_4_9,
    &MAIN_GPIOMUX_INTROUTER0_outp_24_29_to_PRU_ICSSG1_pr1_iep1_cap_intr_req_10_15,
    &MAIN_GPIOMUX_INTROUTER0_outp_46_53_to_PRU_ICSSG1_pr1_slv_intr_46_53,
}

tisci_irq_MAIN_GPIOMUX_INTROUTER0

const struct Sciclient_rmIrqNode tisci_irq_MAIN_GPIOMUX_INTROUTER0

static

Initial value:

= {
    .id = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .n_if = 13,
    .p_if = &tisci_if_MAIN_GPIOMUX_INTROUTER0[0],
}

MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_GICSS0_spi_104_107

const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_GICSS0_spi_104_107

Initial value:

= {
    .lbase = 0,
    .len = 4,
    .rid = TISCI_DEV_GICSS0,
    .rbase = 104,
}

MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS0_CORE0_intr_104_107

const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS0_CORE0_intr_104_107

Initial value:

= {
    .lbase = 0,
    .len = 4,
    .rid = TISCI_DEV_R5FSS0_CORE0,
    .rbase = 104,
}

MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS0_CORE1_intr_104_107

const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS0_CORE1_intr_104_107

Initial value:

= {
    .lbase = 0,
    .len = 4,
    .rid = TISCI_DEV_R5FSS0_CORE1,
    .rbase = 104,
}

MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS1_CORE0_intr_104_107

const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS1_CORE0_intr_104_107

Initial value:

= {
    .lbase = 0,
    .len = 4,
    .rid = TISCI_DEV_R5FSS1_CORE0,
    .rbase = 104,
}

MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS1_CORE1_intr_104_107

const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS1_CORE1_intr_104_107

Initial value:

= {
    .lbase = 0,
    .len = 4,
    .rid = TISCI_DEV_R5FSS1_CORE1,
    .rbase = 104,
}

MCU_MCU_GPIOMUX_INTROUTER0_outp_4_7_to_MCU_M4FSS0_CORE0_nvic_0_3

const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_4_7_to_MCU_M4FSS0_CORE0_nvic_0_3

Initial value:

= {
    .lbase = 4,
    .len = 4,
    .rid = TISCI_DEV_MCU_M4FSS0_CORE0,
    .rbase = 0,
}

MCU_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_MCU_ESM0_esm_pls_event0_88_91

const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_MCU_ESM0_esm_pls_event0_88_91

Initial value:

= {
    .lbase = 8,
    .len = 4,
    .rid = TISCI_DEV_MCU_ESM0,
    .rbase = 88,
}

MCU_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_MCU_ESM0_esm_pls_event1_92_95

const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_MCU_ESM0_esm_pls_event1_92_95

Initial value:

= {
    .lbase = 8,
    .len = 4,
    .rid = TISCI_DEV_MCU_ESM0,
    .rbase = 92,
}

MCU_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_MCU_ESM0_esm_pls_event2_96_99

const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_MCU_ESM0_esm_pls_event2_96_99

Initial value:

= {
    .lbase = 8,
    .len = 4,
    .rid = TISCI_DEV_MCU_ESM0,
    .rbase = 96,
}

tisci_if_MCU_MCU_GPIOMUX_INTROUTER0

const struct Sciclient_rmIrqIf* const tisci_if_MCU_MCU_GPIOMUX_INTROUTER0[]

Initial value:

= {
    &MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_GICSS0_spi_104_107,
    &MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS0_CORE0_intr_104_107,
    &MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS0_CORE1_intr_104_107,
    &MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS1_CORE0_intr_104_107,
    &MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS1_CORE1_intr_104_107,
    &MCU_MCU_GPIOMUX_INTROUTER0_outp_4_7_to_MCU_M4FSS0_CORE0_nvic_0_3,
    &MCU_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_MCU_ESM0_esm_pls_event0_88_91,
    &MCU_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_MCU_ESM0_esm_pls_event1_92_95,
    &MCU_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_MCU_ESM0_esm_pls_event2_96_99,
}

tisci_irq_MCU_MCU_GPIOMUX_INTROUTER0

const struct Sciclient_rmIrqNode tisci_irq_MCU_MCU_GPIOMUX_INTROUTER0

static

Initial value:

= {
    .id = TISCI_DEV_MCU_MCU_GPIOMUX_INTROUTER0,
    .n_if = 9,
    .p_if = &tisci_if_MCU_MCU_GPIOMUX_INTROUTER0[0],
}

TIMESYNC_EVENT_INTROUTER0_outl_0_7_to_DMASS0_INTAGGR_0_intaggr_levi_pend_8_15

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_0_7_to_DMASS0_INTAGGR_0_intaggr_levi_pend_8_15

Initial value:

= {
    .lbase = 0,
    .len = 8,
    .rid = TISCI_DEV_DMASS0_INTAGGR_0,
    .rbase = 8,
}

TIMESYNC_EVENT_INTROUTER0_outl_8_8_to_PRU_ICSSG0_pr1_edc0_latch0_in_0_0

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_8_8_to_PRU_ICSSG0_pr1_edc0_latch0_in_0_0

Initial value:

= {
    .lbase = 8,
    .len = 1,
    .rid = TISCI_DEV_PRU_ICSSG0,
    .rbase = 0,
}

TIMESYNC_EVENT_INTROUTER0_outl_9_9_to_PRU_ICSSG0_pr1_edc0_latch1_in_1_1

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_9_9_to_PRU_ICSSG0_pr1_edc0_latch1_in_1_1

Initial value:

= {
    .lbase = 9,
    .len = 1,
    .rid = TISCI_DEV_PRU_ICSSG0,
    .rbase = 1,
}

TIMESYNC_EVENT_INTROUTER0_outl_10_10_to_PRU_ICSSG0_pr1_edc1_latch0_in_2_2

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_10_10_to_PRU_ICSSG0_pr1_edc1_latch0_in_2_2

Initial value:

= {
    .lbase = 10,
    .len = 1,
    .rid = TISCI_DEV_PRU_ICSSG0,
    .rbase = 2,
}

TIMESYNC_EVENT_INTROUTER0_outl_11_11_to_PRU_ICSSG0_pr1_edc1_latch1_in_3_3

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_11_11_to_PRU_ICSSG0_pr1_edc1_latch1_in_3_3

Initial value:

= {
    .lbase = 11,
    .len = 1,
    .rid = TISCI_DEV_PRU_ICSSG0,
    .rbase = 3,
}

TIMESYNC_EVENT_INTROUTER0_outl_12_12_to_PRU_ICSSG1_pr1_edc0_latch0_in_0_0

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_12_12_to_PRU_ICSSG1_pr1_edc0_latch0_in_0_0

Initial value:

= {
    .lbase = 12,
    .len = 1,
    .rid = TISCI_DEV_PRU_ICSSG1,
    .rbase = 0,
}

TIMESYNC_EVENT_INTROUTER0_outl_13_13_to_PRU_ICSSG1_pr1_edc0_latch1_in_1_1

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_13_13_to_PRU_ICSSG1_pr1_edc0_latch1_in_1_1

Initial value:

= {
    .lbase = 13,
    .len = 1,
    .rid = TISCI_DEV_PRU_ICSSG1,
    .rbase = 1,
}

TIMESYNC_EVENT_INTROUTER0_outl_14_14_to_PRU_ICSSG1_pr1_edc1_latch0_in_2_2

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_14_14_to_PRU_ICSSG1_pr1_edc1_latch0_in_2_2

Initial value:

= {
    .lbase = 14,
    .len = 1,
    .rid = TISCI_DEV_PRU_ICSSG1,
    .rbase = 2,
}

TIMESYNC_EVENT_INTROUTER0_outl_15_15_to_PRU_ICSSG1_pr1_edc1_latch1_in_3_3

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_15_15_to_PRU_ICSSG1_pr1_edc1_latch1_in_3_3

Initial value:

= {
    .lbase = 15,
    .len = 1,
    .rid = TISCI_DEV_PRU_ICSSG1,
    .rbase = 3,
}

TIMESYNC_EVENT_INTROUTER0_outl_16_16_to_CPTS0_cpts_hw1_push_0_0

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_16_16_to_CPTS0_cpts_hw1_push_0_0

Initial value:

= {
    .lbase = 16,
    .len = 1,
    .rid = TISCI_DEV_CPTS0,
    .rbase = 0,
}

TIMESYNC_EVENT_INTROUTER0_outl_17_17_to_CPTS0_cpts_hw2_push_1_1

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_17_17_to_CPTS0_cpts_hw2_push_1_1

Initial value:

= {
    .lbase = 17,
    .len = 1,
    .rid = TISCI_DEV_CPTS0,
    .rbase = 1,
}

TIMESYNC_EVENT_INTROUTER0_outl_18_18_to_CPTS0_cpts_hw3_push_2_2

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_18_18_to_CPTS0_cpts_hw3_push_2_2

Initial value:

= {
    .lbase = 18,
    .len = 1,
    .rid = TISCI_DEV_CPTS0,
    .rbase = 2,
}

TIMESYNC_EVENT_INTROUTER0_outl_19_19_to_CPTS0_cpts_hw4_push_3_3

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_19_19_to_CPTS0_cpts_hw4_push_3_3

Initial value:

= {
    .lbase = 19,
    .len = 1,
    .rid = TISCI_DEV_CPTS0,
    .rbase = 3,
}

TIMESYNC_EVENT_INTROUTER0_outl_20_20_to_CPTS0_cpts_hw5_push_4_4

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_20_20_to_CPTS0_cpts_hw5_push_4_4

Initial value:

= {
    .lbase = 20,
    .len = 1,
    .rid = TISCI_DEV_CPTS0,
    .rbase = 4,
}

TIMESYNC_EVENT_INTROUTER0_outl_21_21_to_CPTS0_cpts_hw6_push_5_5

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_21_21_to_CPTS0_cpts_hw6_push_5_5

Initial value:

= {
    .lbase = 21,
    .len = 1,
    .rid = TISCI_DEV_CPTS0,
    .rbase = 5,
}

TIMESYNC_EVENT_INTROUTER0_outl_22_22_to_CPTS0_cpts_hw7_push_6_6

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_22_22_to_CPTS0_cpts_hw7_push_6_6

Initial value:

= {
    .lbase = 22,
    .len = 1,
    .rid = TISCI_DEV_CPTS0,
    .rbase = 6,
}

TIMESYNC_EVENT_INTROUTER0_outl_23_23_to_CPTS0_cpts_hw8_push_7_7

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_23_23_to_CPTS0_cpts_hw8_push_7_7

Initial value:

= {
    .lbase = 23,
    .len = 1,
    .rid = TISCI_DEV_CPTS0,
    .rbase = 7,
}

TIMESYNC_EVENT_INTROUTER0_outl_29_29_to_PCIE0_pcie_cpts_hw2_push_0_0

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_29_29_to_PCIE0_pcie_cpts_hw2_push_0_0

Initial value:

= {
    .lbase = 29,
    .len = 1,
    .rid = TISCI_DEV_PCIE0,
    .rbase = 0,
}

TIMESYNC_EVENT_INTROUTER0_outl_30_30_to_CPSW0_cpts_hw1_push_0_0

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_30_30_to_CPSW0_cpts_hw1_push_0_0

Initial value:

= {
    .lbase = 30,
    .len = 1,
    .rid = TISCI_DEV_CPSW0,
    .rbase = 0,
}

TIMESYNC_EVENT_INTROUTER0_outl_31_31_to_CPSW0_cpts_hw2_push_1_1

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_31_31_to_CPSW0_cpts_hw2_push_1_1

Initial value:

= {
    .lbase = 31,
    .len = 1,
    .rid = TISCI_DEV_CPSW0,
    .rbase = 1,
}

TIMESYNC_EVENT_INTROUTER0_outl_32_32_to_CPSW0_cpts_hw3_push_2_2

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_32_32_to_CPSW0_cpts_hw3_push_2_2

Initial value:

= {
    .lbase = 32,
    .len = 1,
    .rid = TISCI_DEV_CPSW0,
    .rbase = 2,
}

TIMESYNC_EVENT_INTROUTER0_outl_33_33_to_CPSW0_cpts_hw4_push_3_3

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_33_33_to_CPSW0_cpts_hw4_push_3_3

Initial value:

= {
    .lbase = 33,
    .len = 1,
    .rid = TISCI_DEV_CPSW0,
    .rbase = 3,
}

TIMESYNC_EVENT_INTROUTER0_outl_34_34_to_CPSW0_cpts_hw5_push_4_4

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_34_34_to_CPSW0_cpts_hw5_push_4_4

Initial value:

= {
    .lbase = 34,
    .len = 1,
    .rid = TISCI_DEV_CPSW0,
    .rbase = 4,
}

TIMESYNC_EVENT_INTROUTER0_outl_35_35_to_CPSW0_cpts_hw6_push_5_5

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_35_35_to_CPSW0_cpts_hw6_push_5_5

Initial value:

= {
    .lbase = 35,
    .len = 1,
    .rid = TISCI_DEV_CPSW0,
    .rbase = 5,
}

TIMESYNC_EVENT_INTROUTER0_outl_36_36_to_CPSW0_cpts_hw7_push_6_6

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_36_36_to_CPSW0_cpts_hw7_push_6_6

Initial value:

= {
    .lbase = 36,
    .len = 1,
    .rid = TISCI_DEV_CPSW0,
    .rbase = 6,
}

TIMESYNC_EVENT_INTROUTER0_outl_37_37_to_CPSW0_cpts_hw8_push_7_7

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_37_37_to_CPSW0_cpts_hw8_push_7_7

Initial value:

= {
    .lbase = 37,
    .len = 1,
    .rid = TISCI_DEV_CPSW0,
    .rbase = 7,
}

tisci_if_TIMESYNC_EVENT_INTROUTER0

const struct Sciclient_rmIrqIf* const tisci_if_TIMESYNC_EVENT_INTROUTER0[]

Initial value:

= {
    &TIMESYNC_EVENT_INTROUTER0_outl_0_7_to_DMASS0_INTAGGR_0_intaggr_levi_pend_8_15,
    &TIMESYNC_EVENT_INTROUTER0_outl_8_8_to_PRU_ICSSG0_pr1_edc0_latch0_in_0_0,
    &TIMESYNC_EVENT_INTROUTER0_outl_9_9_to_PRU_ICSSG0_pr1_edc0_latch1_in_1_1,
    &TIMESYNC_EVENT_INTROUTER0_outl_10_10_to_PRU_ICSSG0_pr1_edc1_latch0_in_2_2,
    &TIMESYNC_EVENT_INTROUTER0_outl_11_11_to_PRU_ICSSG0_pr1_edc1_latch1_in_3_3,
    &TIMESYNC_EVENT_INTROUTER0_outl_12_12_to_PRU_ICSSG1_pr1_edc0_latch0_in_0_0,
    &TIMESYNC_EVENT_INTROUTER0_outl_13_13_to_PRU_ICSSG1_pr1_edc0_latch1_in_1_1,
    &TIMESYNC_EVENT_INTROUTER0_outl_14_14_to_PRU_ICSSG1_pr1_edc1_latch0_in_2_2,
    &TIMESYNC_EVENT_INTROUTER0_outl_15_15_to_PRU_ICSSG1_pr1_edc1_latch1_in_3_3,
    &TIMESYNC_EVENT_INTROUTER0_outl_16_16_to_CPTS0_cpts_hw1_push_0_0,
    &TIMESYNC_EVENT_INTROUTER0_outl_17_17_to_CPTS0_cpts_hw2_push_1_1,
    &TIMESYNC_EVENT_INTROUTER0_outl_18_18_to_CPTS0_cpts_hw3_push_2_2,
    &TIMESYNC_EVENT_INTROUTER0_outl_19_19_to_CPTS0_cpts_hw4_push_3_3,
    &TIMESYNC_EVENT_INTROUTER0_outl_20_20_to_CPTS0_cpts_hw5_push_4_4,
    &TIMESYNC_EVENT_INTROUTER0_outl_21_21_to_CPTS0_cpts_hw6_push_5_5,
    &TIMESYNC_EVENT_INTROUTER0_outl_22_22_to_CPTS0_cpts_hw7_push_6_6,
    &TIMESYNC_EVENT_INTROUTER0_outl_23_23_to_CPTS0_cpts_hw8_push_7_7,
    &TIMESYNC_EVENT_INTROUTER0_outl_29_29_to_PCIE0_pcie_cpts_hw2_push_0_0,
    &TIMESYNC_EVENT_INTROUTER0_outl_30_30_to_CPSW0_cpts_hw1_push_0_0,
    &TIMESYNC_EVENT_INTROUTER0_outl_31_31_to_CPSW0_cpts_hw2_push_1_1,
    &TIMESYNC_EVENT_INTROUTER0_outl_32_32_to_CPSW0_cpts_hw3_push_2_2,
    &TIMESYNC_EVENT_INTROUTER0_outl_33_33_to_CPSW0_cpts_hw4_push_3_3,
    &TIMESYNC_EVENT_INTROUTER0_outl_34_34_to_CPSW0_cpts_hw5_push_4_4,
    &TIMESYNC_EVENT_INTROUTER0_outl_35_35_to_CPSW0_cpts_hw6_push_5_5,
    &TIMESYNC_EVENT_INTROUTER0_outl_36_36_to_CPSW0_cpts_hw7_push_6_6,
    &TIMESYNC_EVENT_INTROUTER0_outl_37_37_to_CPSW0_cpts_hw8_push_7_7,
}

tisci_irq_TIMESYNC_EVENT_INTROUTER0

const struct Sciclient_rmIrqNode tisci_irq_TIMESYNC_EVENT_INTROUTER0

static

Initial value:

= {
    .id = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .n_if = 26,
    .p_if = &tisci_if_TIMESYNC_EVENT_INTROUTER0[0],
}

CPSW0_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_80_80

const struct Sciclient_rmIrqIf CPSW0_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_80_80

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_CMP_EVENT_INTROUTER0,
    .rbase = 80,
}

CPSW0_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_21_21

const struct Sciclient_rmIrqIf CPSW0_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_21_21

Initial value:

= {
    .lbase = 1,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 21,
}

CPSW0_cpts_genf1_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_22_22

const struct Sciclient_rmIrqIf CPSW0_cpts_genf1_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_22_22

Initial value:

= {
    .lbase = 2,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 22,
}

CPSW0_cpts_sync_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_34_34

const struct Sciclient_rmIrqIf CPSW0_cpts_sync_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_34_34

Initial value:

= {
    .lbase = 3,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 34,
}

tisci_if_CPSW0

const struct Sciclient_rmIrqIf* const tisci_if_CPSW0[]

Initial value:

= {
    &CPSW0_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_80_80,
    &CPSW0_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_21_21,
    &CPSW0_cpts_genf1_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_22_22,
    &CPSW0_cpts_sync_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_34_34,
}

tisci_irq_CPSW0

const struct Sciclient_rmIrqNode tisci_irq_CPSW0

static

Initial value:

= {
    .id = TISCI_DEV_CPSW0,
    .n_if = 4,
    .p_if = &tisci_if_CPSW0[0],
}

DMASS0_INTAGGR_0_intaggr_vintr_pend_0_39_to_GICSS0_spi_64_103

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_0_39_to_GICSS0_spi_64_103

Initial value:

= {
    .lbase = 0,
    .len = 40,
    .rid = TISCI_DEV_GICSS0,
    .rbase = 64,
}

DMASS0_INTAGGR_0_intaggr_vintr_pend_72_79_to_R5FSS0_CORE0_intr_8_15

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_72_79_to_R5FSS0_CORE0_intr_8_15

Initial value:

= {
    .lbase = 72,
    .len = 8,
    .rid = TISCI_DEV_R5FSS0_CORE0,
    .rbase = 8,
}

DMASS0_INTAGGR_0_intaggr_vintr_pend_40_71_to_R5FSS0_CORE0_intr_64_95

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_40_71_to_R5FSS0_CORE0_intr_64_95

Initial value:

= {
    .lbase = 40,
    .len = 32,
    .rid = TISCI_DEV_R5FSS0_CORE0,
    .rbase = 64,
}

DMASS0_INTAGGR_0_intaggr_vintr_pend_80_87_to_R5FSS0_CORE1_intr_8_15

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_80_87_to_R5FSS0_CORE1_intr_8_15

Initial value:

= {
    .lbase = 80,
    .len = 8,
    .rid = TISCI_DEV_R5FSS0_CORE1,
    .rbase = 8,
}

DMASS0_INTAGGR_0_intaggr_vintr_pend_40_71_to_R5FSS0_CORE1_intr_64_95

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_40_71_to_R5FSS0_CORE1_intr_64_95

Initial value:

= {
    .lbase = 40,
    .len = 32,
    .rid = TISCI_DEV_R5FSS0_CORE1,
    .rbase = 64,
}

DMASS0_INTAGGR_0_intaggr_vintr_pend_120_127_to_R5FSS1_CORE0_intr_8_15

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_120_127_to_R5FSS1_CORE0_intr_8_15

Initial value:

= {
    .lbase = 120,
    .len = 8,
    .rid = TISCI_DEV_R5FSS1_CORE0,
    .rbase = 8,
}

DMASS0_INTAGGR_0_intaggr_vintr_pend_88_119_to_R5FSS1_CORE0_intr_64_95

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_88_119_to_R5FSS1_CORE0_intr_64_95

Initial value:

= {
    .lbase = 88,
    .len = 32,
    .rid = TISCI_DEV_R5FSS1_CORE0,
    .rbase = 64,
}

DMASS0_INTAGGR_0_intaggr_vintr_pend_128_135_to_R5FSS1_CORE1_intr_8_15

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_128_135_to_R5FSS1_CORE1_intr_8_15

Initial value:

= {
    .lbase = 128,
    .len = 8,
    .rid = TISCI_DEV_R5FSS1_CORE1,
    .rbase = 8,
}

DMASS0_INTAGGR_0_intaggr_vintr_pend_88_119_to_R5FSS1_CORE1_intr_64_95

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_88_119_to_R5FSS1_CORE1_intr_64_95

Initial value:

= {
    .lbase = 88,
    .len = 32,
    .rid = TISCI_DEV_R5FSS1_CORE1,
    .rbase = 64,
}

DMASS0_INTAGGR_0_intaggr_vintr_pend_152_159_to_PRU_ICSSG0_pr1_slv_intr_16_23

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_152_159_to_PRU_ICSSG0_pr1_slv_intr_16_23

Initial value:

= {
    .lbase = 152,
    .len = 8,
    .rid = TISCI_DEV_PRU_ICSSG0,
    .rbase = 16,
}

DMASS0_INTAGGR_0_intaggr_vintr_pend_160_167_to_PRU_ICSSG1_pr1_slv_intr_16_23

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_160_167_to_PRU_ICSSG1_pr1_slv_intr_16_23

Initial value:

= {
    .lbase = 160,
    .len = 8,
    .rid = TISCI_DEV_PRU_ICSSG1,
    .rbase = 16,
}

DMASS0_INTAGGR_0_intaggr_vintr_pend_168_183_to_MCU_M4FSS0_CORE0_nvic_32_47

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_168_183_to_MCU_M4FSS0_CORE0_nvic_32_47

Initial value:

= {
    .lbase = 168,
    .len = 16,
    .rid = TISCI_DEV_MCU_M4FSS0_CORE0,
    .rbase = 32,
}

tisci_if_DMASS0_INTAGGR_0

const struct Sciclient_rmIrqIf* const tisci_if_DMASS0_INTAGGR_0[]

Initial value:

= {
    &DMASS0_INTAGGR_0_intaggr_vintr_pend_0_39_to_GICSS0_spi_64_103,
    &DMASS0_INTAGGR_0_intaggr_vintr_pend_72_79_to_R5FSS0_CORE0_intr_8_15,
    &DMASS0_INTAGGR_0_intaggr_vintr_pend_40_71_to_R5FSS0_CORE0_intr_64_95,
    &DMASS0_INTAGGR_0_intaggr_vintr_pend_80_87_to_R5FSS0_CORE1_intr_8_15,
    &DMASS0_INTAGGR_0_intaggr_vintr_pend_40_71_to_R5FSS0_CORE1_intr_64_95,
    &DMASS0_INTAGGR_0_intaggr_vintr_pend_120_127_to_R5FSS1_CORE0_intr_8_15,
    &DMASS0_INTAGGR_0_intaggr_vintr_pend_88_119_to_R5FSS1_CORE0_intr_64_95,
    &DMASS0_INTAGGR_0_intaggr_vintr_pend_128_135_to_R5FSS1_CORE1_intr_8_15,
    &DMASS0_INTAGGR_0_intaggr_vintr_pend_88_119_to_R5FSS1_CORE1_intr_64_95,
    &DMASS0_INTAGGR_0_intaggr_vintr_pend_152_159_to_PRU_ICSSG0_pr1_slv_intr_16_23,
    &DMASS0_INTAGGR_0_intaggr_vintr_pend_160_167_to_PRU_ICSSG1_pr1_slv_intr_16_23,
    &DMASS0_INTAGGR_0_intaggr_vintr_pend_168_183_to_MCU_M4FSS0_CORE0_nvic_32_47,
}

tisci_irq_DMASS0_INTAGGR_0

const struct Sciclient_rmIrqNode tisci_irq_DMASS0_INTAGGR_0

static

Initial value:

= {
    .id = TISCI_DEV_DMASS0_INTAGGR_0,
    .n_if = 12,
    .p_if = &tisci_if_DMASS0_INTAGGR_0[0],
}

TIMER0_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_0_0

const struct Sciclient_rmIrqIf TIMER0_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_0_0

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 0,
}

tisci_if_TIMER0

const struct Sciclient_rmIrqIf* const tisci_if_TIMER0[]

Initial value:

= {
    &TIMER0_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_0_0,
}

tisci_irq_TIMER0

const struct Sciclient_rmIrqNode tisci_irq_TIMER0

static

Initial value:

= {
    .id = TISCI_DEV_TIMER0,
    .n_if = 1,
    .p_if = &tisci_if_TIMER0[0],
}

TIMER1_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_1_1

const struct Sciclient_rmIrqIf TIMER1_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_1_1

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 1,
}

tisci_if_TIMER1

const struct Sciclient_rmIrqIf* const tisci_if_TIMER1[]

Initial value:

= {
    &TIMER1_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_1_1,
}

tisci_irq_TIMER1

const struct Sciclient_rmIrqNode tisci_irq_TIMER1

static

Initial value:

= {
    .id = TISCI_DEV_TIMER1,
    .n_if = 1,
    .p_if = &tisci_if_TIMER1[0],
}

TIMER2_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_2_2

const struct Sciclient_rmIrqIf TIMER2_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_2_2

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 2,
}

tisci_if_TIMER2

const struct Sciclient_rmIrqIf* const tisci_if_TIMER2[]

Initial value:

= {
    &TIMER2_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_2_2,
}

tisci_irq_TIMER2

const struct Sciclient_rmIrqNode tisci_irq_TIMER2

static

Initial value:

= {
    .id = TISCI_DEV_TIMER2,
    .n_if = 1,
    .p_if = &tisci_if_TIMER2[0],
}

TIMER3_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_3_3

const struct Sciclient_rmIrqIf TIMER3_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_3_3

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 3,
}

tisci_if_TIMER3

const struct Sciclient_rmIrqIf* const tisci_if_TIMER3[]

Initial value:

= {
    &TIMER3_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_3_3,
}

tisci_irq_TIMER3

const struct Sciclient_rmIrqNode tisci_irq_TIMER3

static

Initial value:

= {
    .id = TISCI_DEV_TIMER3,
    .n_if = 1,
    .p_if = &tisci_if_TIMER3[0],
}

GTC0_gtc_push_event_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_36_36

const struct Sciclient_rmIrqIf GTC0_gtc_push_event_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_36_36

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 36,
}

tisci_if_GTC0

const struct Sciclient_rmIrqIf* const tisci_if_GTC0[]

Initial value:

= {
    &GTC0_gtc_push_event_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_36_36,
}

tisci_irq_GTC0

const struct Sciclient_rmIrqNode tisci_irq_GTC0

static

Initial value:

= {
    .id = TISCI_DEV_GTC0,
    .n_if = 1,
    .p_if = &tisci_if_GTC0[0],
}

GPIO0_gpio_0_89_to_MAIN_GPIOMUX_INTROUTER0_in_0_89

const struct Sciclient_rmIrqIf GPIO0_gpio_0_89_to_MAIN_GPIOMUX_INTROUTER0_in_0_89

Initial value:

= {
    .lbase = 0,
    .len = 90,
    .rid = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .rbase = 0,
}

GPIO0_gpio_bank_90_98_to_MAIN_GPIOMUX_INTROUTER0_in_190_198

const struct Sciclient_rmIrqIf GPIO0_gpio_bank_90_98_to_MAIN_GPIOMUX_INTROUTER0_in_190_198

Initial value:

= {
    .lbase = 90,
    .len = 9,
    .rid = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .rbase = 190,
}

tisci_if_GPIO0

const struct Sciclient_rmIrqIf* const tisci_if_GPIO0[]

Initial value:

= {
    &GPIO0_gpio_0_89_to_MAIN_GPIOMUX_INTROUTER0_in_0_89,
    &GPIO0_gpio_bank_90_98_to_MAIN_GPIOMUX_INTROUTER0_in_190_198,
}

tisci_irq_GPIO0

const struct Sciclient_rmIrqNode tisci_irq_GPIO0

static

Initial value:

= {
    .id = TISCI_DEV_GPIO0,
    .n_if = 2,
    .p_if = &tisci_if_GPIO0[0],
}

GPIO1_gpio_0_89_to_MAIN_GPIOMUX_INTROUTER0_in_90_179

const struct Sciclient_rmIrqIf GPIO1_gpio_0_89_to_MAIN_GPIOMUX_INTROUTER0_in_90_179

Initial value:

= {
    .lbase = 0,
    .len = 90,
    .rid = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .rbase = 90,
}

GPIO1_gpio_bank_90_98_to_MAIN_GPIOMUX_INTROUTER0_in_180_188

const struct Sciclient_rmIrqIf GPIO1_gpio_bank_90_98_to_MAIN_GPIOMUX_INTROUTER0_in_180_188

Initial value:

= {
    .lbase = 90,
    .len = 9,
    .rid = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .rbase = 180,
}

tisci_if_GPIO1

const struct Sciclient_rmIrqIf* const tisci_if_GPIO1[]

Initial value:

= {
    &GPIO1_gpio_0_89_to_MAIN_GPIOMUX_INTROUTER0_in_90_179,
    &GPIO1_gpio_bank_90_98_to_MAIN_GPIOMUX_INTROUTER0_in_180_188,
}

tisci_irq_GPIO1

const struct Sciclient_rmIrqNode tisci_irq_GPIO1

static

Initial value:

= {
    .id = TISCI_DEV_GPIO1,
    .n_if = 2,
    .p_if = &tisci_if_GPIO1[0],
}

MCU_GPIO0_gpio_0_29_to_MCU_MCU_GPIOMUX_INTROUTER0_in_0_29

const struct Sciclient_rmIrqIf MCU_GPIO0_gpio_0_29_to_MCU_MCU_GPIOMUX_INTROUTER0_in_0_29

Initial value:

= {
    .lbase = 0,
    .len = 30,
    .rid = TISCI_DEV_MCU_MCU_GPIOMUX_INTROUTER0,
    .rbase = 0,
}

MCU_GPIO0_gpio_bank_30_31_to_MCU_MCU_GPIOMUX_INTROUTER0_in_30_31

const struct Sciclient_rmIrqIf MCU_GPIO0_gpio_bank_30_31_to_MCU_MCU_GPIOMUX_INTROUTER0_in_30_31

Initial value:

= {
    .lbase = 30,
    .len = 2,
    .rid = TISCI_DEV_MCU_MCU_GPIOMUX_INTROUTER0,
    .rbase = 30,
}

tisci_if_MCU_GPIO0

const struct Sciclient_rmIrqIf* const tisci_if_MCU_GPIO0[]

Initial value:

= {
    &MCU_GPIO0_gpio_0_29_to_MCU_MCU_GPIOMUX_INTROUTER0_in_0_29,
    &MCU_GPIO0_gpio_bank_30_31_to_MCU_MCU_GPIOMUX_INTROUTER0_in_30_31,
}

tisci_irq_MCU_GPIO0

const struct Sciclient_rmIrqNode tisci_irq_MCU_GPIO0

static

Initial value:

= {
    .id = TISCI_DEV_MCU_GPIO0,
    .n_if = 2,
    .p_if = &tisci_if_MCU_GPIO0[0],
}

GPMC0_gpmc_sdmareq_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_29_29

const struct Sciclient_rmIrqIf GPMC0_gpmc_sdmareq_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_29_29

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_DMASS0_INTAGGR_0,
    .rbase = 29,
}

tisci_if_GPMC0

const struct Sciclient_rmIrqIf* const tisci_if_GPMC0[]

Initial value:

= {
    &GPMC0_gpmc_sdmareq_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_29_29,
}

tisci_irq_GPMC0

const struct Sciclient_rmIrqNode tisci_irq_GPMC0

static

Initial value:

= {
    .id = TISCI_DEV_GPMC0,
    .n_if = 1,
    .p_if = &tisci_if_GPMC0[0],
}

PRU_ICSSG0_pr1_edc0_sync0_out_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_25_25

const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_edc0_sync0_out_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_25_25

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 25,
}

PRU_ICSSG0_pr1_edc0_sync1_out_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_26_26

const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_edc0_sync1_out_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_26_26

Initial value:

= {
    .lbase = 1,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 26,
}

PRU_ICSSG0_pr1_edc1_sync0_out_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_27_27

const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_edc1_sync0_out_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_27_27

Initial value:

= {
    .lbase = 2,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 27,
}

PRU_ICSSG0_pr1_edc1_sync1_out_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_28_28

const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_edc1_sync1_out_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_28_28

Initial value:

= {
    .lbase = 3,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 28,
}

PRU_ICSSG0_pr1_host_intr_req_4_11_to_CMP_EVENT_INTROUTER0_in_0_7

const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_host_intr_req_4_11_to_CMP_EVENT_INTROUTER0_in_0_7

Initial value:

= {
    .lbase = 4,
    .len = 8,
    .rid = TISCI_DEV_CMP_EVENT_INTROUTER0,
    .rbase = 0,
}

PRU_ICSSG0_pr1_iep0_cmp_intr_req_12_27_to_CMP_EVENT_INTROUTER0_in_16_31

const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_iep0_cmp_intr_req_12_27_to_CMP_EVENT_INTROUTER0_in_16_31

Initial value:

= {
    .lbase = 12,
    .len = 16,
    .rid = TISCI_DEV_CMP_EVENT_INTROUTER0,
    .rbase = 16,
}

PRU_ICSSG0_pr1_iep1_cmp_intr_req_28_43_to_CMP_EVENT_INTROUTER0_in_32_47

const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_iep1_cmp_intr_req_28_43_to_CMP_EVENT_INTROUTER0_in_32_47

Initial value:

= {
    .lbase = 28,
    .len = 16,
    .rid = TISCI_DEV_CMP_EVENT_INTROUTER0,
    .rbase = 32,
}

tisci_if_PRU_ICSSG0

const struct Sciclient_rmIrqIf* const tisci_if_PRU_ICSSG0[]

Initial value:

= {
    &PRU_ICSSG0_pr1_edc0_sync0_out_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_25_25,
    &PRU_ICSSG0_pr1_edc0_sync1_out_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_26_26,
    &PRU_ICSSG0_pr1_edc1_sync0_out_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_27_27,
    &PRU_ICSSG0_pr1_edc1_sync1_out_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_28_28,
    &PRU_ICSSG0_pr1_host_intr_req_4_11_to_CMP_EVENT_INTROUTER0_in_0_7,
    &PRU_ICSSG0_pr1_iep0_cmp_intr_req_12_27_to_CMP_EVENT_INTROUTER0_in_16_31,
    &PRU_ICSSG0_pr1_iep1_cmp_intr_req_28_43_to_CMP_EVENT_INTROUTER0_in_32_47,
}

tisci_irq_PRU_ICSSG0

const struct Sciclient_rmIrqNode tisci_irq_PRU_ICSSG0

static

Initial value:

= {
    .id = TISCI_DEV_PRU_ICSSG0,
    .n_if = 7,
    .p_if = &tisci_if_PRU_ICSSG0[0],
}

PRU_ICSSG1_pr1_edc0_sync0_out_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_29_29

const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_edc0_sync0_out_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_29_29

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 29,
}

PRU_ICSSG1_pr1_edc0_sync1_out_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_30_30

const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_edc0_sync1_out_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_30_30

Initial value:

= {
    .lbase = 1,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 30,
}

PRU_ICSSG1_pr1_edc1_sync0_out_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_31_31

const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_edc1_sync0_out_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_31_31

Initial value:

= {
    .lbase = 2,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 31,
}

PRU_ICSSG1_pr1_edc1_sync1_out_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_32_32

const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_edc1_sync1_out_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_32_32

Initial value:

= {
    .lbase = 3,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 32,
}

PRU_ICSSG1_pr1_host_intr_req_4_11_to_CMP_EVENT_INTROUTER0_in_8_15

const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_host_intr_req_4_11_to_CMP_EVENT_INTROUTER0_in_8_15

Initial value:

= {
    .lbase = 4,
    .len = 8,
    .rid = TISCI_DEV_CMP_EVENT_INTROUTER0,
    .rbase = 8,
}

PRU_ICSSG1_pr1_iep0_cmp_intr_req_12_27_to_CMP_EVENT_INTROUTER0_in_48_63

const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_iep0_cmp_intr_req_12_27_to_CMP_EVENT_INTROUTER0_in_48_63

Initial value:

= {
    .lbase = 12,
    .len = 16,
    .rid = TISCI_DEV_CMP_EVENT_INTROUTER0,
    .rbase = 48,
}

PRU_ICSSG1_pr1_iep1_cmp_intr_req_28_43_to_CMP_EVENT_INTROUTER0_in_64_79

const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_iep1_cmp_intr_req_28_43_to_CMP_EVENT_INTROUTER0_in_64_79

Initial value:

= {
    .lbase = 28,
    .len = 16,
    .rid = TISCI_DEV_CMP_EVENT_INTROUTER0,
    .rbase = 64,
}

tisci_if_PRU_ICSSG1

const struct Sciclient_rmIrqIf* const tisci_if_PRU_ICSSG1[]

Initial value:

= {
    &PRU_ICSSG1_pr1_edc0_sync0_out_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_29_29,
    &PRU_ICSSG1_pr1_edc0_sync1_out_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_30_30,
    &PRU_ICSSG1_pr1_edc1_sync0_out_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_31_31,
    &PRU_ICSSG1_pr1_edc1_sync1_out_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_32_32,
    &PRU_ICSSG1_pr1_host_intr_req_4_11_to_CMP_EVENT_INTROUTER0_in_8_15,
    &PRU_ICSSG1_pr1_iep0_cmp_intr_req_12_27_to_CMP_EVENT_INTROUTER0_in_48_63,
    &PRU_ICSSG1_pr1_iep1_cmp_intr_req_28_43_to_CMP_EVENT_INTROUTER0_in_64_79,
}

tisci_irq_PRU_ICSSG1

const struct Sciclient_rmIrqNode tisci_irq_PRU_ICSSG1

static

Initial value:

= {
    .id = TISCI_DEV_PRU_ICSSG1,
    .n_if = 7,
    .p_if = &tisci_if_PRU_ICSSG1[0],
}

CPTS0_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_82_82

const struct Sciclient_rmIrqIf CPTS0_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_82_82

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_CMP_EVENT_INTROUTER0,
    .rbase = 82,
}

CPTS0_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_16_16

const struct Sciclient_rmIrqIf CPTS0_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_16_16

Initial value:

= {
    .lbase = 1,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 16,
}

CPTS0_cpts_genf1_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_17_17

const struct Sciclient_rmIrqIf CPTS0_cpts_genf1_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_17_17

Initial value:

= {
    .lbase = 2,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 17,
}

CPTS0_cpts_genf2_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_18_18

const struct Sciclient_rmIrqIf CPTS0_cpts_genf2_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_18_18

Initial value:

= {
    .lbase = 3,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 18,
}

CPTS0_cpts_genf3_4_4_to_TIMESYNC_EVENT_INTROUTER0_in_19_19

const struct Sciclient_rmIrqIf CPTS0_cpts_genf3_4_4_to_TIMESYNC_EVENT_INTROUTER0_in_19_19

Initial value:

= {
    .lbase = 4,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 19,
}

CPTS0_cpts_genf4_5_5_to_TIMESYNC_EVENT_INTROUTER0_in_20_20

const struct Sciclient_rmIrqIf CPTS0_cpts_genf4_5_5_to_TIMESYNC_EVENT_INTROUTER0_in_20_20

Initial value:

= {
    .lbase = 5,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 20,
}

CPTS0_cpts_genf5_6_6_to_TIMESYNC_EVENT_INTROUTER0_in_24_24

const struct Sciclient_rmIrqIf CPTS0_cpts_genf5_6_6_to_TIMESYNC_EVENT_INTROUTER0_in_24_24

Initial value:

= {
    .lbase = 6,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 24,
}

CPTS0_cpts_sync_7_7_to_TIMESYNC_EVENT_INTROUTER0_in_35_35

const struct Sciclient_rmIrqIf CPTS0_cpts_sync_7_7_to_TIMESYNC_EVENT_INTROUTER0_in_35_35

Initial value:

= {
    .lbase = 7,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 35,
}

tisci_if_CPTS0

const struct Sciclient_rmIrqIf* const tisci_if_CPTS0[]

Initial value:

= {
    &CPTS0_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_82_82,
    &CPTS0_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_16_16,
    &CPTS0_cpts_genf1_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_17_17,
    &CPTS0_cpts_genf2_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_18_18,
    &CPTS0_cpts_genf3_4_4_to_TIMESYNC_EVENT_INTROUTER0_in_19_19,
    &CPTS0_cpts_genf4_5_5_to_TIMESYNC_EVENT_INTROUTER0_in_20_20,
    &CPTS0_cpts_genf5_6_6_to_TIMESYNC_EVENT_INTROUTER0_in_24_24,
    &CPTS0_cpts_sync_7_7_to_TIMESYNC_EVENT_INTROUTER0_in_35_35,
}

tisci_irq_CPTS0

const struct Sciclient_rmIrqNode tisci_irq_CPTS0

static

Initial value:

= {
    .id = TISCI_DEV_CPTS0,
    .n_if = 8,
    .p_if = &tisci_if_CPTS0[0],
}

EPWM0_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_39_39

const struct Sciclient_rmIrqIf EPWM0_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_39_39

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 39,
}

tisci_if_EPWM0

const struct Sciclient_rmIrqIf* const tisci_if_EPWM0[]

Initial value:

= {
    &EPWM0_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_39_39,
}

tisci_irq_EPWM0

const struct Sciclient_rmIrqNode tisci_irq_EPWM0

static

Initial value:

= {
    .id = TISCI_DEV_EPWM0,
    .n_if = 1,
    .p_if = &tisci_if_EPWM0[0],
}

EPWM3_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_40_40

const struct Sciclient_rmIrqIf EPWM3_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_40_40

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 40,
}

tisci_if_EPWM3

const struct Sciclient_rmIrqIf* const tisci_if_EPWM3[]

Initial value:

= {
    &EPWM3_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_40_40,
}

tisci_irq_EPWM3

const struct Sciclient_rmIrqNode tisci_irq_EPWM3

static

Initial value:

= {
    .id = TISCI_DEV_EPWM3,
    .n_if = 1,
    .p_if = &tisci_if_EPWM3[0],
}

EPWM6_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_41_41

const struct Sciclient_rmIrqIf EPWM6_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_41_41

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 41,
}

tisci_if_EPWM6

const struct Sciclient_rmIrqIf* const tisci_if_EPWM6[]

Initial value:

= {
    &EPWM6_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_41_41,
}

tisci_irq_EPWM6

const struct Sciclient_rmIrqNode tisci_irq_EPWM6

static

Initial value:

= {
    .id = TISCI_DEV_EPWM6,
    .n_if = 1,
    .p_if = &tisci_if_EPWM6[0],
}

PCIE0_pcie_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_81_81

const struct Sciclient_rmIrqIf PCIE0_pcie_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_81_81

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_CMP_EVENT_INTROUTER0,
    .rbase = 81,
}

PCIE0_pcie_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_23_23

const struct Sciclient_rmIrqIf PCIE0_pcie_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_23_23

Initial value:

= {
    .lbase = 1,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 23,
}

PCIE0_pcie_cpts_sync_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_33_33

const struct Sciclient_rmIrqIf PCIE0_pcie_cpts_sync_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_33_33

Initial value:

= {
    .lbase = 3,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 33,
}

PCIE0_pcie_cpts_hw1_push_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_37_37

const struct Sciclient_rmIrqIf PCIE0_pcie_cpts_hw1_push_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_37_37

Initial value:

= {
    .lbase = 2,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 37,
}

PCIE0_pcie_ptm_valid_pulse_4_4_to_TIMESYNC_EVENT_INTROUTER0_in_38_38

const struct Sciclient_rmIrqIf PCIE0_pcie_ptm_valid_pulse_4_4_to_TIMESYNC_EVENT_INTROUTER0_in_38_38

Initial value:

= {
    .lbase = 4,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 38,
}

tisci_if_PCIE0

const struct Sciclient_rmIrqIf* const tisci_if_PCIE0[]

Initial value:

= {
    &PCIE0_pcie_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_81_81,
    &PCIE0_pcie_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_23_23,
    &PCIE0_pcie_cpts_sync_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_33_33,
    &PCIE0_pcie_cpts_hw1_push_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_37_37,
    &PCIE0_pcie_ptm_valid_pulse_4_4_to_TIMESYNC_EVENT_INTROUTER0_in_38_38,
}

tisci_irq_PCIE0

const struct Sciclient_rmIrqNode tisci_irq_PCIE0

static

Initial value:

= {
    .id = TISCI_DEV_PCIE0,
    .n_if = 5,
    .p_if = &tisci_if_PCIE0[0],
}

gRmIrqTree

const struct Sciclient_rmIrqNode* const gRmIrqTree[]

Initial value:

= {
    &tisci_irq_CMP_EVENT_INTROUTER0,
    &tisci_irq_MAIN_GPIOMUX_INTROUTER0,
    &tisci_irq_MCU_MCU_GPIOMUX_INTROUTER0,
    &tisci_irq_TIMESYNC_EVENT_INTROUTER0,
    &tisci_irq_CPSW0,
    &tisci_irq_DMASS0_INTAGGR_0,
    &tisci_irq_TIMER0,
    &tisci_irq_TIMER1,
    &tisci_irq_TIMER2,
    &tisci_irq_TIMER3,
    &tisci_irq_GTC0,
    &tisci_irq_GPIO0,
    &tisci_irq_GPIO1,
    &tisci_irq_MCU_GPIO0,
    &tisci_irq_GPMC0,
    &tisci_irq_PRU_ICSSG0,
    &tisci_irq_PRU_ICSSG1,
    &tisci_irq_CPTS0,
    &tisci_irq_EPWM0,
    &tisci_irq_EPWM3,
    &tisci_irq_EPWM6,
    &tisci_irq_PCIE0,
}

gRmIrqTreeCount

const uint32_t gRmIrqTreeCount = sizeof(gRmIrqTree)/sizeof(gRmIrqTree[0])