AM64x MCU+ SDK  10.01.00
phy_common.h
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32 
41 #ifndef PHY_COMMON_H_
42 #define PHY_COMMON_H_
43 
44 /* ========================================================================== */
45 /* Include Files */
46 /* ========================================================================== */
47 
48 #include <stdint.h>
49 #include <stdbool.h>
50 
51 #ifdef __cplusplus
52 extern "C" {
53 #endif
54 
55 /* ========================================================================== */
56 /* Macros */
57 /* ========================================================================== */
58 
59 #define ETHPHYDRV_MAX_OBJ_SIZE (64) /* to meet the size of Phy_Obj_t */
60 
62 #define PHY_DIV_ROUNDUP(val, div) (((val) + (div) - 1) / (div))
63 
65 #define PHY_BIT(n) (1U << (n))
66 
68 #define PHY_ON (1U)
69 
70 #define PHY_OFF (0U)
71 
72 #define PHY_CFG_IS_ON(name) ((PHY_CFG_ ## name) == PHY_ON)
73 
74 #define PHY_CFG_IS_OFF(name) ((PHY_CFG_ ## name) == PHY_OFF)
75 
86 #define PHY_SOK ( (int32_t) (0))
87 
88 #define PHY_EFAIL (-(int32_t) (1))
89 
90 #define PHY_EBADARGS (-(int32_t) (2)) (-(int32_t) (2))
91 
92 #define PHY_EINVALIDPARAMS (-(int32_t) (3))
93 
94 #define PHY_ETIMEOUT (-(int32_t) (4))
95 
96 #define PHY_EALLOC (-(int32_t) (8))
97 
98 #define PHY_EPERM (PHY_EALLOC - 4)
99 
100 #define PHY_ENOTSUPPORTED (PHY_EALLOC - 5)
101 
104 /* PHY Register Definitions */
105 
107 #define PHY_BMCR (0x00U)
108 
109 #define PHY_BMSR (0x01U)
110 
111 #define PHY_PHYIDR1 (0x02U)
112 
113 #define PHY_PHYIDR2 (0x03U)
114 
115 #define PHY_ANAR (0x04U)
116 
117 #define PHY_ANLPAR (0x05U)
118 
119 #define PHY_ANER (0x06U)
120 
121 #define PHY_ANNPTR (0x07U)
122 
123 #define PHY_ANNPRR (0x08U)
124 
125 #define PHY_GIGCR (0x09U)
126 
127 #define PHY_GIGSR (0x0AU)
128 
129 #define PHY_MMD_CR (0x0DU)
130 
131 #define PHY_MMD_DR (0x0EU)
132 
133 #define PHY_GIGESR (0x0FU)
134 
135 /* MMD_CR register definitions */
136 #define MMD_CR_ADDR (0x0000U)
137 #define MMD_CR_DATA_NOPOSTINC (0x4000U)
138 #define MMD_CR_DATA_POSTINC_RW (0x8000U)
139 #define MMD_CR_DATA_POSTINC_W (0xC000U)
140 #define MMD_CR_DEVADDR (0x001FU)
141 
142 /* BMCR register definitions */
143 #define PHY_BMCR_RESET PHY_BIT(15)
144 #define PHY_BMCR_LOOPBACK PHY_BIT(14)
145 #define PHY_BMCR_SPEED100 PHY_BIT(13)
146 #define PHY_BMCR_ANEN PHY_BIT(12)
147 #define PHY_BMCR_PWRDOWN PHY_BIT(11)
148 #define PHY_BMCR_ISOLATE PHY_BIT(10)
149 #define PHY_BMCR_ANRESTART PHY_BIT(9)
150 #define PHY_BMCR_FD PHY_BIT(8)
151 #define PHY_BMCR_SPEED1000 PHY_BIT(6)
152 
154 #define PHY_EXTENDED_CFG_SIZE_MAX (128U)
155 
156 
158 #define PHY_LINK_CAP_HD10 PHY_BIT(1)
159 
160 #define PHY_LINK_CAP_FD10 PHY_BIT(2)
161 
162 #define PHY_LINK_CAP_HD100 PHY_BIT(3)
163 
164 #define PHY_LINK_CAP_FD100 PHY_BIT(4)
165 
166 #define PHY_LINK_CAP_HD1000 PHY_BIT(5)
167 
168 #define PHY_LINK_CAP_FD1000 PHY_BIT(6)
169 
170 #define PHY_LINK_CAP_10 (PHY_LINK_CAP_HD10 | PHY_LINK_CAP_FD10)
171 
172 #define PHY_LINK_CAP_100 (PHY_LINK_CAP_HD100 | PHY_LINK_CAP_FD100)
173 
174 #define PHY_LINK_CAP_1000 (PHY_LINK_CAP_HD1000 | PHY_LINK_CAP_FD1000)
175 
176 #define PHY_LINK_CAP_ALL (PHY_LINK_CAP_HD10 | PHY_LINK_CAP_FD10 | \
177  PHY_LINK_CAP_HD100 | PHY_LINK_CAP_FD100 | \
178  PHY_LINK_CAP_HD1000 | PHY_LINK_CAP_FD1000)
179 
180 /* ========================================================================== */
181 /* Structures and Enums */
182 /* ========================================================================== */
183 
184 
185 typedef struct Phy_Version_s
186 {
188  uint32_t oui;
190  uint32_t model;
192  uint32_t revision;
193 } Phy_Version;
194 
195 typedef enum Phy_Mii_e
196 {
198  PHY_MAC_MII_MII = 0U,
199 
201  PHY_MAC_MII_RMII,
202 
204  PHY_MAC_MII_GMII,
205 
207  PHY_MAC_MII_RGMII,
208 
210  PHY_MAC_MII_SGMII,
211 
213  PHY_MAC_MII_QSGMII,
214 } Phy_Mii;
215 
216 typedef struct
217 {
218  int32_t (*EnetPhy_readReg)(void* pArgs, uint32_t reg, uint16_t *val);
219 
220  int32_t (*EnetPhy_writeReg)(void* pArgs, uint32_t reg, uint16_t val);
221 
222  int32_t (*EnetPhy_rmwReg)(void* pArgs, uint32_t reg, uint16_t mask,
223  uint16_t val);
224 
225  int32_t (*EnetPhy_readExtReg)(void* pArgs, uint32_t reg,
226  uint16_t *val);
227 
228  int32_t (*EnetPhy_writeExtReg)(void* pArgs, uint32_t reg,
229  uint16_t val);
230 
232  void* pArgs;
233 
234 } Phy_RegAccessCb_t;
235 
236 typedef uint8_t EthPhyDrv_Handle[ETHPHYDRV_MAX_OBJ_SIZE];
237 
238 typedef struct
239 {
240 
241  struct
242  {
243 
249  const char *name;
250 
266  bool (*isPhyDevSupported)(EthPhyDrv_Handle hPhy,
267  const void *pVersion);
268 
280  bool (*isMacModeSupported)(EthPhyDrv_Handle hPhy,
281  Phy_Mii mii);
282 
294  void (*bind)(EthPhyDrv_Handle* hPhy,
295  uint8_t phyAddr,
296  Phy_RegAccessCb_t* pRegAccessCb);
297 
311  int32_t (*config)(EthPhyDrv_Handle hPhy,
312  const void *pExtCfg,
313  const uint32_t extCfgSize,
314  Phy_Mii mii,
315  bool loopbackEn);
316 
325  void (*reset)(EthPhyDrv_Handle hPhy);
326 
337  bool (*isResetComplete)(EthPhyDrv_Handle hPhy);
338 
351  int32_t (*readExtReg)(EthPhyDrv_Handle hPhy,
352  uint32_t reg,
353  uint16_t* val);
354 
367  int32_t (*writeExtReg)(EthPhyDrv_Handle hPhy,
368  uint32_t reg,
369  uint16_t val);
370 
382  int32_t (*rmwExtReg)(EthPhyDrv_Handle hPhy,
383  uint32_t reg,
384  uint16_t mask,
385  uint16_t* val);
386 
388  void (*printRegs)(EthPhyDrv_Handle hPhy);
389 
401  int32_t (*adjPtpFreq)(EthPhyDrv_Handle hPhy,
402  int64_t ppb);
403 
415  int32_t (*adjPtpPhase)(EthPhyDrv_Handle hPhy,
416  int64_t offset);
417 
429  int32_t (*getPtpTime)(EthPhyDrv_Handle hPhy,
430  uint64_t *ts64);
431 
443  int32_t (*setPtpTime)(EthPhyDrv_Handle hPhy,
444  uint64_t ts64);
445 
460  int32_t (*getPtpTxTime)(EthPhyDrv_Handle hPhy,
461  uint32_t domain,
462  uint32_t msgType,
463  uint32_t seqId,
464  uint64_t *ts64);
465 
480  int32_t (*getPtpRxTime)(EthPhyDrv_Handle hPhy,
481  uint32_t domain,
482  uint32_t msgType,
483  uint32_t seqId,
484  uint64_t *ts64);
485 
499  int32_t (*waitPtpTxTime)(EthPhyDrv_Handle hPhy,
500  uint32_t domain,
501  uint32_t msgType,
502  uint32_t seqId);
503 
517  int32_t (*procStatusFrame)(EthPhyDrv_Handle hPhy,
518  uint8_t *frame,
519  uint32_t size,
520  uint32_t *types);
521 
534  int32_t (*getStatusFrameEthHeader)(EthPhyDrv_Handle hPhy,
535  uint8_t *ethhdr,
536  uint32_t size);
537 
550  int32_t (*enablePtp)(EthPhyDrv_Handle hPhy,
551  bool on,
552  uint32_t srcMacStatusFrameType);
553 
563  int32_t (*tickDriver)(EthPhyDrv_Handle hPhy);
564 
579  int32_t (*enableEventCapture)(EthPhyDrv_Handle hPhy, uint32_t eventIdx,
580  bool falling, bool on);
581 
598  int32_t (*enableTriggerOutput)(EthPhyDrv_Handle hPhy, uint32_t triggerIdx,
599  uint64_t start, uint64_t period, bool repeat);
600 
613  int32_t (*getEventTs)(EthPhyDrv_Handle hPhy, uint32_t *eventIdx,
614  uint32_t *seqId, uint64_t *ts64);
615  } fxn;
616 
617  EthPhyDrv_Handle hDrv;
618 } Phy_DrvObj_t;
619 
620 typedef Phy_DrvObj_t* EthPhyDrv_If;
621 
622 
623 /* TODO: Move this to private files */
624 typedef struct
625 {
626  uint8_t phyAddr;
627  Phy_RegAccessCb_t regAccessApi;
628 } Phy_Obj_t;
629 
630 /* ========================================================================== */
631 /* Global Variables Declarations */
632 /* ========================================================================== */
633 
634 /* ========================================================================== */
635 /* Function Declarations */
636 /* ========================================================================== */
637 
638 int32_t GenericPhy_readExtReg(EthPhyDrv_Handle hPhy,
639  uint32_t reg,
640  uint16_t* val);
641 
642 int32_t GenericPhy_writeExtReg(EthPhyDrv_Handle hPhy,
643  uint32_t reg,
644  uint16_t val);
645 
646 void GenericPhy_reset(EthPhyDrv_Handle hPhy);
647 
648 bool GenericPhy_isResetComplete(EthPhyDrv_Handle hPhy);
649 
650 /* ========================================================================== */
651 /* Deprecated Function Declarations */
652 /* ========================================================================== */
653 
654 /* None */
655 
656 /* ========================================================================== */
657 /* Static Function Definitions */
658 /* ========================================================================== */
659 
660 /* None */
661 
662 #ifdef __cplusplus
663 }
664 #endif
665 
666 #endif /* PHY_COMMON_H_ */
667 
EthPhyDrv_If
Phy_DrvObj_t * EthPhyDrv_If
Definition: phy_common.h:620
PHY_MAC_MII_RGMII
@ PHY_MAC_MII_RGMII
RGMII interface.
Definition: phy_common.h:207
EnetPhy_writeExtReg
int32_t EnetPhy_writeExtReg(void *pArgs, uint32_t reg, uint16_t val)
Write PHY extended register.
Phy_Obj_t::regAccessApi
Phy_RegAccessCb_t regAccessApi
Definition: phy_common.h:627
size
uint16_t size
Definition: tisci_boardcfg.h:1
EnetPhy_readExtReg
int32_t EnetPhy_readExtReg(void *pArgs, uint32_t reg, uint16_t *val)
Read PHY extended register.
Phy_RegAccessCb_t
Definition: phy_common.h:217
EnetPhy_writeReg
int32_t EnetPhy_writeReg(void *pArgs, uint32_t reg, uint16_t val)
Write PHY register.
EthPhyDrv_Handle
uint8_t EthPhyDrv_Handle[ETHPHYDRV_MAX_OBJ_SIZE]
Definition: phy_common.h:236
Phy_DrvObj_t
Definition: phy_common.h:239
Phy_Mii
Phy_Mii
Definition: phy_common.h:196
Phy_Version
Definition: phy_common.h:186
PHY_MAC_MII_GMII
@ PHY_MAC_MII_GMII
GMII interface.
Definition: phy_common.h:204
PHY_MAC_MII_QSGMII
@ PHY_MAC_MII_QSGMII
QSGMII interface.
Definition: phy_common.h:213
GenericPhy_readExtReg
int32_t GenericPhy_readExtReg(EthPhyDrv_Handle hPhy, uint32_t reg, uint16_t *val)
PHY_MAC_MII_SGMII
@ PHY_MAC_MII_SGMII
SGMII interface.
Definition: phy_common.h:210
Phy_Obj_t::phyAddr
uint8_t phyAddr
Definition: phy_common.h:626
GenericPhy_reset
void GenericPhy_reset(EthPhyDrv_Handle hPhy)
Phy_Version::model
uint32_t model
Definition: phy_common.h:190
Phy_Version::revision
uint32_t revision
Definition: phy_common.h:192
EnetPhy_rmwReg
int32_t EnetPhy_rmwReg(void *pArgs, uint32_t reg, uint16_t mask, uint16_t val)
Read-modify-write PHY register.
EnetPhy_readReg
int32_t EnetPhy_readReg(void *pArgs, uint32_t reg, uint16_t *val)
Read PHY register.
ETHPHYDRV_MAX_OBJ_SIZE
#define ETHPHYDRV_MAX_OBJ_SIZE
Definition: phy_common.h:59
Phy_RegAccessCb_t::pArgs
void * pArgs
Definition: phy_common.h:232
GenericPhy_isResetComplete
bool GenericPhy_isResetComplete(EthPhyDrv_Handle hPhy)
Phy_Version::oui
uint32_t oui
Definition: phy_common.h:188
Phy_DrvObj_t::name
const char * name
Driver name.
Definition: phy_common.h:249
domain
domgrp_t domain
Definition: tisci_pm_core.h:1
GenericPhy_writeExtReg
int32_t GenericPhy_writeExtReg(EthPhyDrv_Handle hPhy, uint32_t reg, uint16_t val)
Phy_Obj_t
Definition: phy_common.h:625
PHY_MAC_MII_MII
@ PHY_MAC_MII_MII
MII interface.
Definition: phy_common.h:198
Phy_DrvObj_t::hDrv
EthPhyDrv_Handle hDrv
Definition: phy_common.h:617
PHY_MAC_MII_RMII
@ PHY_MAC_MII_RMII
RMII interface.
Definition: phy_common.h:201