AM64x MCU+ SDK  12.01.00
phy_common.h
Go to the documentation of this file.
1 /*
2  * Copyright (c) Texas Instruments Incorporated 2024-2025
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  *
8  * Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  *
11  * Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the
14  * distribution.
15  *
16  * Neither the name of Texas Instruments Incorporated nor the names of
17  * its contributors may be used to endorse or promote products derived
18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
41 #ifndef PHY_COMMON_H_
42 #define PHY_COMMON_H_
43 
44 /* ========================================================================== */
45 /* Include Files */
46 /* ========================================================================== */
47 
48 #include <stdint.h>
49 #include <stdbool.h>
50 
51 #ifdef __cplusplus
52 extern "C" {
53 #endif
54 
55 /* ========================================================================== */
56 /* Macros */
57 /* ========================================================================== */
58 
59 #define ETHPHYDRV_MAX_OBJ_SIZE (64) /* to meet the size of Phy_Obj_t */
60 
62 #define PHY_DIV_ROUNDUP(val, div) (((val) + (div) - 1) / (div))
63 
65 #define PHY_BIT(n) (1U << (n))
66 
68 #define PHY_ON (1U)
69 
70 #define PHY_OFF (0U)
71 
72 #define PHY_CFG_IS_ON(name) ((PHY_CFG_ ## name) == PHY_ON)
73 
74 #define PHY_CFG_IS_OFF(name) ((PHY_CFG_ ## name) == PHY_OFF)
75 
86 #define PHY_SOK ( (int32_t) (0))
87 
88 #define PHY_EFAIL (-(int32_t) (1))
89 
90 #define PHY_EBADARGS (-(int32_t) (2))
91 
92 #define PHY_EINVALIDPARAMS (-(int32_t) (3))
93 
94 #define PHY_ETIMEOUT (-(int32_t) (4))
95 
96 #define PHY_EALLOC (-(int32_t) (8))
97 
98 #define PHY_EPERM (PHY_EALLOC - 4)
99 
100 #define PHY_ENOTSUPPORTED (PHY_EALLOC - 5)
101 
104 /* PHY Register Definitions */
105 
107 #define PHY_BMCR (0x00U)
108 
109 #define PHY_BMSR (0x01U)
110 
111 #define PHY_PHYIDR1 (0x02U)
112 
113 #define PHY_PHYIDR2 (0x03U)
114 
115 #define PHY_ANAR (0x04U)
116 
117 #define PHY_ANLPAR (0x05U)
118 
119 #define PHY_ANER (0x06U)
120 
121 #define PHY_ANNPTR (0x07U)
122 
123 #define PHY_ANNPRR (0x08U)
124 
125 #define PHY_GIGCR (0x09U)
126 
127 #define PHY_GIGSR (0x0AU)
128 
129 #define PHY_MMD_CR (0x0DU)
130 
131 #define PHY_MMD_DR (0x0EU)
132 
133 #define PHY_GIGESR (0x0FU)
134 
135 /* MMD_CR register definitions */
136 #define MMD_CR_ADDR (0x0000U)
137 #define MMD_CR_DATA_NOPOSTINC (0x4000U)
138 #define MMD_CR_DATA_POSTINC_RW (0x8000U)
139 #define MMD_CR_DATA_POSTINC_W (0xC000U)
140 #define MMD_CR_DEVADDR (0x001FU)
141 
142 /* BMCR register definitions */
143 #define PHY_BMCR_RESET PHY_BIT(15)
144 #define PHY_BMCR_LOOPBACK PHY_BIT(14)
145 #define PHY_BMCR_SPEED100 PHY_BIT(13)
146 #define PHY_BMCR_ANEN PHY_BIT(12)
147 #define PHY_BMCR_PWRDOWN PHY_BIT(11)
148 #define PHY_BMCR_ISOLATE PHY_BIT(10)
149 #define PHY_BMCR_ANRESTART PHY_BIT(9)
150 #define PHY_BMCR_FD PHY_BIT(8)
151 #define PHY_BMCR_SPEED1000 PHY_BIT(6)
152 
154 #define PHY_EXTENDED_CFG_SIZE_MAX (128U)
155 
156 
158 #define PHY_LINK_CAP_HD10 PHY_BIT(1)
159 
160 #define PHY_LINK_CAP_FD10 PHY_BIT(2)
161 
162 #define PHY_LINK_CAP_HD100 PHY_BIT(3)
163 
164 #define PHY_LINK_CAP_FD100 PHY_BIT(4)
165 
166 #define PHY_LINK_CAP_HD1000 PHY_BIT(5)
167 
168 #define PHY_LINK_CAP_FD1000 PHY_BIT(6)
169 
170 #define PHY_LINK_CAP_10 (PHY_LINK_CAP_HD10 | PHY_LINK_CAP_FD10)
171 
172 #define PHY_LINK_CAP_100 (PHY_LINK_CAP_HD100 | PHY_LINK_CAP_FD100)
173 
174 #define PHY_LINK_CAP_1000 (PHY_LINK_CAP_HD1000 | PHY_LINK_CAP_FD1000)
175 
176 #define PHY_LINK_CAP_ALL (PHY_LINK_CAP_HD10 | PHY_LINK_CAP_FD10 | \
177  PHY_LINK_CAP_HD100 | PHY_LINK_CAP_FD100 | \
178  PHY_LINK_CAP_HD1000 | PHY_LINK_CAP_FD1000)
179 
181 #define PHY_LINK_ADV_HD10 PHY_BIT(1)
182 
183 #define PHY_LINK_ADV_FD10 PHY_BIT(2)
184 
185 #define PHY_LINK_ADV_HD100 PHY_BIT(3)
186 
187 #define PHY_LINK_ADV_FD100 PHY_BIT(4)
188 
189 #define PHY_LINK_ADV_HD1000 PHY_BIT(5)
190 
191 #define PHY_LINK_ADV_FD1000 PHY_BIT(6)
192 
193 #define PHY_LINK_ADV_10 (PHY_LINK_ADV_HD10 | PHY_LINK_ADV_FD10)
194 
195 #define PHY_LINK_ADV_100 (PHY_LINK_ADV_HD100 | PHY_LINK_ADV_FD100)
196 
197 #define PHY_LINK_ADV_1000 (PHY_LINK_ADV_HD1000 | PHY_LINK_ADV_FD1000)
198 
199 #define PHY_LINK_ADV_ALL (PHY_LINK_ADV_HD10 | PHY_LINK_ADV_FD10 | \
200  PHY_LINK_ADV_HD100 | PHY_LINK_ADV_FD100 | \
201  PHY_LINK_ADV_HD1000 | PHY_LINK_ADV_FD1000)
202 
204 #define PHY_FAST_LINK_DOWN_ENERGY_LOST PHY_BIT(0)
205 
206 #define PHY_FAST_LINK_DOWN_MSE PHY_BIT(1)
207 
208 #define PHY_FAST_LINK_DOWN_MLT3_ERRORS PHY_BIT(2)
209 
210 #define PHY_FAST_LINK_DOWN_RX_ERR PHY_BIT(3)
211 
212 #define PHY_FAST_LINK_DOWN_DESCRAMBLER_SYNC_LOSS PHY_BIT(4)
213 
214 /* ========================================================================== */
215 /* Structures and Enums */
216 /* ========================================================================== */
217 
218 
219 typedef struct Phy_Version_s
220 {
222  uint32_t oui;
224  uint32_t model;
226  uint32_t revision;
227 } Phy_Version;
228 
229 typedef enum Phy_Mii_e
230 {
232  PHY_MAC_MII_MII = 0U,
233 
235  PHY_MAC_MII_RMII,
236 
238  PHY_MAC_MII_GMII,
239 
241  PHY_MAC_MII_RGMII,
242 
244  PHY_MAC_MII_SGMII,
245 
247  PHY_MAC_MII_QSGMII,
248 } Phy_Mii;
249 
250 typedef enum Phy_Link_SpeedDuplex_e
251 {
253  PHY_LINK_AUTONEG = 0U,
254 
256  PHY_LINK_FD10,
257 
259  PHY_LINK_FD100,
260 
262  PHY_LINK_FD1000,
263 
265  PHY_LINK_HD10,
266 
268  PHY_LINK_HD100,
269 
271  PHY_LINK_HD1000,
272 
274  PHY_LINK_INVALID,
275 } Phy_Link_SpeedDuplex;
276 
277 typedef enum Phy_AutoNegCtrl_e
278 {
280  PHY_AUTO_NEGOTIATION_CTRL_DISABLE = 0U,
281 
283  PHY_AUTO_NEGOTIATION_CTRL_ENABLE,
284 
286  PHY_AUTO_NEGOTIATION_CTRL_RESTART,
287 
289  PHY_AUTO_NEGOTIATION_CTRL_ENABLE_AND_RESTART,
290 }Phy_AutoNegCtrl;
291 
292 typedef enum Phy_Mdi_e
293 {
295  PHY_MDI_MANUAL_CONFIG = 0U,
296 
298  PHY_MDIX_MANUAL_CONFIG,
299 
301  PHY_AUTO_CROSSOVER,
302 }Phy_Mdi;
303 
304 typedef struct
305 {
306  int32_t (*EnetPhy_readReg)(void* pArgs, uint32_t reg, uint16_t *val);
307 
308  int32_t (*EnetPhy_writeReg)(void* pArgs, uint32_t reg, uint16_t val);
309 
310  int32_t (*EnetPhy_rmwReg)(void* pArgs, uint32_t reg, uint16_t mask,
311  uint16_t val);
312 
313  int32_t (*EnetPhy_readExtReg)(void* pArgs, uint32_t reg,
314  uint16_t *val);
315 
316  int32_t (*EnetPhy_writeExtReg)(void* pArgs, uint32_t reg,
317  uint16_t val);
318 
319  int32_t (*EnetPhy_rmwExtReg)(void* pArgs, uint32_t reg, uint16_t mask,
320  uint16_t val);
321 
323  void* pArgs;
324 
325 } Phy_RegAccessCb_t;
326 
327 typedef uint8_t EthPhyDrv_Handle[ETHPHYDRV_MAX_OBJ_SIZE];
328 
329 typedef struct
330 {
331 
332  struct
333  {
334 
340  const char *name;
341 
357  bool (*isPhyDevSupported)(EthPhyDrv_Handle hPhy,
358  const void *pVersion);
359 
371  bool (*isMacModeSupported)(EthPhyDrv_Handle hPhy,
372  Phy_Mii mii);
373 
385  void (*bind)(EthPhyDrv_Handle* hPhy,
386  uint8_t phyAddr,
387  Phy_RegAccessCb_t* pRegAccessCb);
388 
402  int32_t (*config)(EthPhyDrv_Handle hPhy,
403  const void *pExtCfg,
404  const uint32_t extCfgSize,
405  Phy_Mii mii,
406  bool loopbackEn);
407 
418  int32_t (*reset)(EthPhyDrv_Handle hPhy);
419 
431  int32_t (*isResetComplete)(EthPhyDrv_Handle hPhy, bool *pCompleted);
432 
444  int32_t (*readReg) (EthPhyDrv_Handle hPhy,
445  uint32_t reg,
446  uint16_t *val);
447 
460  int32_t (*writeReg) (EthPhyDrv_Handle hPhy,
461  uint32_t reg,
462  uint16_t val);
463 
476  int32_t (*readExtReg)(EthPhyDrv_Handle hPhy,
477  uint32_t reg,
478  uint16_t* val);
479 
492  int32_t (*writeExtReg)(EthPhyDrv_Handle hPhy,
493  uint32_t reg,
494  uint16_t val);
495 
507  int32_t (*rmwExtReg)(EthPhyDrv_Handle hPhy,
508  uint32_t reg,
509  uint16_t mask,
510  uint16_t* val);
511 
513  void (*printRegs)(EthPhyDrv_Handle hPhy);
514 
526  int32_t (*adjPtpFreq)(EthPhyDrv_Handle hPhy,
527  int64_t ppb);
528 
540  int32_t (*adjPtpPhase)(EthPhyDrv_Handle hPhy,
541  int64_t offset);
542 
554  int32_t (*getPtpTime)(EthPhyDrv_Handle hPhy,
555  uint64_t *ts64);
556 
568  int32_t (*setPtpTime)(EthPhyDrv_Handle hPhy,
569  uint64_t ts64);
570 
585  int32_t (*getPtpTxTime)(EthPhyDrv_Handle hPhy,
586  uint32_t domain,
587  uint32_t msgType,
588  uint32_t seqId,
589  uint64_t *ts64);
590 
605  int32_t (*getPtpRxTime)(EthPhyDrv_Handle hPhy,
606  uint32_t domain,
607  uint32_t msgType,
608  uint32_t seqId,
609  uint64_t *ts64);
610 
624  int32_t (*waitPtpTxTime)(EthPhyDrv_Handle hPhy,
625  uint32_t domain,
626  uint32_t msgType,
627  uint32_t seqId);
628 
642  int32_t (*procStatusFrame)(EthPhyDrv_Handle hPhy,
643  uint8_t *frame,
644  uint32_t size,
645  uint32_t *types);
646 
659  int32_t (*getStatusFrameEthHeader)(EthPhyDrv_Handle hPhy,
660  uint8_t *ethhdr,
661  uint32_t size);
662 
675  int32_t (*enablePtp)(EthPhyDrv_Handle hPhy,
676  bool on,
677  uint32_t srcMacStatusFrameType);
678 
688  int32_t (*tickDriver)(EthPhyDrv_Handle hPhy);
689 
704  int32_t (*enableEventCapture)(EthPhyDrv_Handle hPhy, uint32_t eventIdx,
705  bool falling, bool on);
706 
723  int32_t (*enableTriggerOutput)(EthPhyDrv_Handle hPhy, uint32_t triggerIdx,
724  uint64_t start, uint64_t period, bool repeat);
725 
738  int32_t (*getEventTs)(EthPhyDrv_Handle hPhy, uint32_t *eventIdx,
739  uint32_t *seqId, uint64_t *ts64);
752  int32_t (*configMediaClock)(EthPhyDrv_Handle hPhy, bool isMaster,
753  uint8_t *streamIDMatchValue, bool enTrigOut);
764  int32_t (*nudgeCodecClock)(EthPhyDrv_Handle hPhy, int8_t nudgeValue);
765 
776  int32_t (*restart)(EthPhyDrv_Handle hPhy);
777 
792  int32_t (*isRestartComplete)(EthPhyDrv_Handle hPhy, bool* pCompleted);
793 
806  int32_t (*getId)(EthPhyDrv_Handle hPhy, uint32_t *pId);
807 
821  int32_t (*ctrlPowerDown)(EthPhyDrv_Handle hPhy, bool enable);
822 
836  int32_t (*isPowerDownActive)(EthPhyDrv_Handle hPhy, bool *pActive);
837 
865  int32_t (*setAdvertisement)(EthPhyDrv_Handle hPhy, uint32_t capabilities, uint32_t advertisement);
866 
894  int32_t (*enableAdvertisement)(EthPhyDrv_Handle hPhy, uint32_t capabilities, uint32_t advertisement);
895 
923  int32_t (*disableAdvertisement)(EthPhyDrv_Handle hPhy, uint32_t capabilities, uint32_t advertisement);
924 
940  int32_t (*ctrlAutoNegotiation)(EthPhyDrv_Handle hPhy, uint32_t control);
941 
955  int32_t (*isLinkPartnerAutoNegotiationAble)(EthPhyDrv_Handle hPhy, bool *pAble);
956 
969  int32_t (*isAutoNegotiationEnabled)(EthPhyDrv_Handle hPhy, bool *pEnabled);
970 
983  int32_t (*isAutoNegotiationComplete)(EthPhyDrv_Handle hPhy, bool *pCompleted);
984 
997  int32_t (*isAutoNegotiationRestartComplete)(EthPhyDrv_Handle hPhy, bool *pCompleted);
998 
1011  int32_t (*isLinkUp)(EthPhyDrv_Handle hPhy, bool *pLinkUp);
1012 
1025  int32_t (*isGigabitSupported) (EthPhyDrv_Handle hPhy, bool *pSupported);
1026 
1048  int32_t (*setSpeedDuplex)(EthPhyDrv_Handle hPhy, uint32_t capabilities, uint32_t settings);
1049 
1062  int32_t (*getSpeedDuplex)(EthPhyDrv_Handle hPhy, Phy_Link_SpeedDuplex* pConfig);
1063 
1083  int32_t (*getLocalCaps)(EthPhyDrv_Handle hPhy, uint32_t *pCapabilities);
1084  } fxn;
1085 
1086  EthPhyDrv_Handle hDrv;
1087 } Phy_DrvObj_t;
1088 
1089 typedef Phy_DrvObj_t* EthPhyDrv_If;
1090 
1091 
1092 /* TODO: Move this to private files */
1093 typedef struct
1094 {
1095  uint8_t phyAddr;
1096  Phy_RegAccessCb_t regAccessApi;
1097 } Phy_Obj_t;
1098 
1099 /* ========================================================================== */
1100 /* Global Variables Declarations */
1101 /* ========================================================================== */
1102 
1103 /* ========================================================================== */
1104 /* Function Declarations */
1105 /* ========================================================================== */
1106 
1107 int32_t GenericPhy_readReg(EthPhyDrv_Handle hPhy,
1108  uint32_t reg,
1109  uint16_t *val);
1110 
1111 int32_t GenericPhy_writeReg(EthPhyDrv_Handle hPhy,
1112  uint32_t reg,
1113  uint16_t val);
1114 
1115 int32_t GenericPhy_readExtReg(EthPhyDrv_Handle hPhy,
1116  uint32_t reg,
1117  uint16_t* val);
1118 
1119 int32_t GenericPhy_writeExtReg(EthPhyDrv_Handle hPhy,
1120  uint32_t reg,
1121  uint16_t val);
1122 
1123 int32_t GenericPhy_reset(EthPhyDrv_Handle hPhy);
1124 
1125 int32_t GenericPhy_isResetComplete(EthPhyDrv_Handle hPhy,
1126  bool *pCompleted);
1127 
1128 int32_t GenericPhy_ctrlPowerDown(EthPhyDrv_Handle hPhy,
1129  bool enable);
1130 
1131 int32_t GenericPhy_isPowerDownActive(EthPhyDrv_Handle hPhy,
1132  bool *pActive);
1133 
1134 int32_t GenericPhy_getLocalCaps (EthPhyDrv_Handle hPhy,
1135  uint32_t *pCapabilities);
1136 
1137 int32_t GenericPhy_setAdvertisement(EthPhyDrv_Handle hPhy,
1138  uint32_t capabilities,
1139  uint32_t advertisement);
1140 
1141 int32_t GenericPhy_enableAdvertisement(EthPhyDrv_Handle hPhy,
1142  uint32_t capabilities,
1143  uint32_t advertisement);
1144 
1145 int32_t GenericPhy_disableAdvertisement(EthPhyDrv_Handle hPhy,
1146  uint32_t capabilities,
1147  uint32_t advertisement);
1148 
1149 int32_t GenericPhy_ctrlAutoNegotiation(EthPhyDrv_Handle hPhy,
1150  uint32_t control);
1151 
1152 int32_t GenericPhy_isLinkPartnerAutoNegotiationAble (EthPhyDrv_Handle hPhy,
1153  bool *pAble);
1154 
1155 int32_t GenericPhy_isAutoNegotiationEnabled(EthPhyDrv_Handle hPhy,
1156  bool *enabled);
1157 
1158 int32_t GenericPhy_isAutoNegotiationComplete (EthPhyDrv_Handle hPhy,
1159  bool *completed);
1160 
1161 int32_t GenericPhy_isAutoNegotiationRestartComplete (EthPhyDrv_Handle hPhy,
1162  bool *completed);
1163 
1164 int32_t GenericPhy_isGigabitSupported (EthPhyDrv_Handle hPhy,
1165  bool *pSupported);
1166 
1167 int32_t GenericPhy_setSpeedDuplex (EthPhyDrv_Handle hPhy,
1168  uint32_t capabilities,
1169  uint32_t settings);
1170 
1171 int32_t GenericPhy_isLinkUp (EthPhyDrv_Handle hPhy,
1172  bool *linkUp);
1173 
1174 int32_t GenericPhy_getId(EthPhyDrv_Handle hPhy,
1175  uint32_t *id);
1176 
1177 /* ========================================================================== */
1178 /* Deprecated Function Declarations */
1179 /* ========================================================================== */
1180 
1181 /* None */
1182 
1183 /* ========================================================================== */
1184 /* Static Function Definitions */
1185 /* ========================================================================== */
1186 
1187 /* None */
1188 
1189 #ifdef __cplusplus
1190 }
1191 #endif
1192 
1193 #endif /* PHY_COMMON_H_ */
1194 
EthPhyDrv_If
Phy_DrvObj_t * EthPhyDrv_If
Definition: phy_common.h:1089
Phy_Mdi
Phy_Mdi
Definition: phy_common.h:293
PHY_MAC_MII_RGMII
@ PHY_MAC_MII_RGMII
RGMII interface.
Definition: phy_common.h:241
control
struct tisci_boardcfg_control control
Definition: tisci_boardcfg.h:1
GenericPhy_disableAdvertisement
int32_t GenericPhy_disableAdvertisement(EthPhyDrv_Handle hPhy, uint32_t capabilities, uint32_t advertisement)
GenericPhy_readReg
int32_t GenericPhy_readReg(EthPhyDrv_Handle hPhy, uint32_t reg, uint16_t *val)
EnetPhy_writeExtReg
int32_t EnetPhy_writeExtReg(void *pArgs, uint32_t reg, uint16_t val)
Write PHY extended register.
Phy_Obj_t::regAccessApi
Phy_RegAccessCb_t regAccessApi
Definition: phy_common.h:1096
size
uint16_t size
Definition: tisci_boardcfg.h:1
EnetPhy_readExtReg
int32_t EnetPhy_readExtReg(void *pArgs, uint32_t reg, uint16_t *val)
Read PHY extended register.
GenericPhy_reset
int32_t GenericPhy_reset(EthPhyDrv_Handle hPhy)
PHY_LINK_FD100
@ PHY_LINK_FD100
full-duplex, 100Mbps
Definition: phy_common.h:259
Phy_RegAccessCb_t
Definition: phy_common.h:305
GenericPhy_setAdvertisement
int32_t GenericPhy_setAdvertisement(EthPhyDrv_Handle hPhy, uint32_t capabilities, uint32_t advertisement)
GenericPhy_isAutoNegotiationComplete
int32_t GenericPhy_isAutoNegotiationComplete(EthPhyDrv_Handle hPhy, bool *completed)
PHY_AUTO_NEGOTIATION_CTRL_ENABLE
@ PHY_AUTO_NEGOTIATION_CTRL_ENABLE
Enable Auto Negotiation.
Definition: phy_common.h:283
EnetPhy_rmwExtReg
int32_t EnetPhy_rmwExtReg(EnetPhy_Handle hPhy, uint32_t reg, uint16_t mask, uint16_t val)
Read-modify-write PHY extended register.
EnetPhy_writeReg
int32_t EnetPhy_writeReg(void *pArgs, uint32_t reg, uint16_t val)
Write PHY register.
EthPhyDrv_Handle
uint8_t EthPhyDrv_Handle[ETHPHYDRV_MAX_OBJ_SIZE]
Definition: phy_common.h:327
Phy_DrvObj_t
Definition: phy_common.h:330
enable
uint8_t enable
Definition: tisci_pm_clock.h:6
Phy_Mii
Phy_Mii
Definition: phy_common.h:230
GenericPhy_ctrlPowerDown
int32_t GenericPhy_ctrlPowerDown(EthPhyDrv_Handle hPhy, bool enable)
Phy_Version
Definition: phy_common.h:220
PHY_LINK_HD100
@ PHY_LINK_HD100
half-duplex, 100Mbps
Definition: phy_common.h:268
PHY_LINK_AUTONEG
@ PHY_LINK_AUTONEG
Auto-Negotiation.
Definition: phy_common.h:253
PHY_MAC_MII_GMII
@ PHY_MAC_MII_GMII
GMII interface.
Definition: phy_common.h:238
GenericPhy_setSpeedDuplex
int32_t GenericPhy_setSpeedDuplex(EthPhyDrv_Handle hPhy, uint32_t capabilities, uint32_t settings)
PHY_MAC_MII_QSGMII
@ PHY_MAC_MII_QSGMII
QSGMII interface.
Definition: phy_common.h:247
GenericPhy_getLocalCaps
int32_t GenericPhy_getLocalCaps(EthPhyDrv_Handle hPhy, uint32_t *pCapabilities)
GenericPhy_isPowerDownActive
int32_t GenericPhy_isPowerDownActive(EthPhyDrv_Handle hPhy, bool *pActive)
PHY_LINK_FD1000
@ PHY_LINK_FD1000
full-duplex, 1000Mbps
Definition: phy_common.h:262
GenericPhy_isAutoNegotiationRestartComplete
int32_t GenericPhy_isAutoNegotiationRestartComplete(EthPhyDrv_Handle hPhy, bool *completed)
GenericPhy_readExtReg
int32_t GenericPhy_readExtReg(EthPhyDrv_Handle hPhy, uint32_t reg, uint16_t *val)
PHY_MAC_MII_SGMII
@ PHY_MAC_MII_SGMII
SGMII interface.
Definition: phy_common.h:244
Phy_Obj_t::phyAddr
uint8_t phyAddr
Definition: phy_common.h:1095
GenericPhy_writeReg
int32_t GenericPhy_writeReg(EthPhyDrv_Handle hPhy, uint32_t reg, uint16_t val)
PHY_LINK_HD10
@ PHY_LINK_HD10
half-duplex, 10Mbps
Definition: phy_common.h:265
PHY_AUTO_NEGOTIATION_CTRL_RESTART
@ PHY_AUTO_NEGOTIATION_CTRL_RESTART
Restart Auto Negotiation.
Definition: phy_common.h:286
Phy_Version::model
uint32_t model
Definition: phy_common.h:224
Phy_Version::revision
uint32_t revision
Definition: phy_common.h:226
PHY_AUTO_NEGOTIATION_CTRL_ENABLE_AND_RESTART
@ PHY_AUTO_NEGOTIATION_CTRL_ENABLE_AND_RESTART
Enable and Restart Auto Negotiation.
Definition: phy_common.h:289
PHY_LINK_FD10
@ PHY_LINK_FD10
full-duplex, 10Mbps
Definition: phy_common.h:256
GenericPhy_isResetComplete
int32_t GenericPhy_isResetComplete(EthPhyDrv_Handle hPhy, bool *pCompleted)
GenericPhy_isAutoNegotiationEnabled
int32_t GenericPhy_isAutoNegotiationEnabled(EthPhyDrv_Handle hPhy, bool *enabled)
EnetPhy_rmwReg
int32_t EnetPhy_rmwReg(void *pArgs, uint32_t reg, uint16_t mask, uint16_t val)
Read-modify-write PHY register.
GenericPhy_ctrlAutoNegotiation
int32_t GenericPhy_ctrlAutoNegotiation(EthPhyDrv_Handle hPhy, uint32_t control)
EnetPhy_readReg
int32_t EnetPhy_readReg(void *pArgs, uint32_t reg, uint16_t *val)
Read PHY register.
ETHPHYDRV_MAX_OBJ_SIZE
#define ETHPHYDRV_MAX_OBJ_SIZE
Definition: phy_common.h:59
Phy_AutoNegCtrl
Phy_AutoNegCtrl
Definition: phy_common.h:278
Phy_RegAccessCb_t::pArgs
void * pArgs
Definition: phy_common.h:323
GenericPhy_isLinkPartnerAutoNegotiationAble
int32_t GenericPhy_isLinkPartnerAutoNegotiationAble(EthPhyDrv_Handle hPhy, bool *pAble)
Phy_Version::oui
uint32_t oui
Definition: phy_common.h:222
GenericPhy_isGigabitSupported
int32_t GenericPhy_isGigabitSupported(EthPhyDrv_Handle hPhy, bool *pSupported)
Phy_Link_SpeedDuplex
Phy_Link_SpeedDuplex
Definition: phy_common.h:251
Phy_DrvObj_t::name
const char * name
Driver name.
Definition: phy_common.h:340
PHY_AUTO_CROSSOVER
@ PHY_AUTO_CROSSOVER
Enable automatic crossover.
Definition: phy_common.h:301
domain
domgrp_t domain
Definition: tisci_pm_core.h:1
PHY_AUTO_NEGOTIATION_CTRL_DISABLE
@ PHY_AUTO_NEGOTIATION_CTRL_DISABLE
Disable Auto Negotiation.
Definition: phy_common.h:280
GenericPhy_writeExtReg
int32_t GenericPhy_writeExtReg(EthPhyDrv_Handle hPhy, uint32_t reg, uint16_t val)
PHY_LINK_INVALID
@ PHY_LINK_INVALID
Invalid Speed Duplex.
Definition: phy_common.h:274
PHY_MDI_MANUAL_CONFIG
@ PHY_MDI_MANUAL_CONFIG
Manual MDI configuration.
Definition: phy_common.h:295
PHY_MDIX_MANUAL_CONFIG
@ PHY_MDIX_MANUAL_CONFIG
Manual MDI-X configuration.
Definition: phy_common.h:298
Phy_Obj_t
Definition: phy_common.h:1094
PHY_MAC_MII_MII
@ PHY_MAC_MII_MII
MII interface.
Definition: phy_common.h:232
GenericPhy_getId
int32_t GenericPhy_getId(EthPhyDrv_Handle hPhy, uint32_t *id)
Phy_DrvObj_t::hDrv
EthPhyDrv_Handle hDrv
Definition: phy_common.h:1086
PHY_LINK_HD1000
@ PHY_LINK_HD1000
half-duplex, 1000Mbps
Definition: phy_common.h:271
GenericPhy_isLinkUp
int32_t GenericPhy_isLinkUp(EthPhyDrv_Handle hPhy, bool *linkUp)
GenericPhy_enableAdvertisement
int32_t GenericPhy_enableAdvertisement(EthPhyDrv_Handle hPhy, uint32_t capabilities, uint32_t advertisement)
PHY_MAC_MII_RMII
@ PHY_MAC_MII_RMII
RMII interface.
Definition: phy_common.h:235