AM64x MCU+ SDK  12.01.00
mcspi_lld.h
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1 /*
2  * Copyright (C) 2023-25 Texas Instruments Incorporated
3  *
4  * Redistribution and use in source and binary forms, with or without
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31  */
32 
50 #ifndef MCSPI_LLD_H_
51 #define MCSPI_LLD_H_
52 
53 /* ========================================================================== */
54 /* Include Files */
55 /* ========================================================================== */
56 #include <stdint.h>
57 #include <stdbool.h>
58 #include <drivers/hw_include/csl_types.h>
59 #include <drivers/hw_include/cslr_mcspi.h>
60 #include <drivers/hw_include/cslr.h>
61 #include <drivers/mcspi/v0/lld/dma/mcspi_dma.h>
62 
63 #ifdef __cplusplus
64 extern "C" {
65 #endif
66 
67 /* ========================================================================== */
68 /* Macros & Typedefs */
69 /* ========================================================================== */
70 
71 
72 /* function pointer to get clock ticks */
73 typedef uint32_t (*MCSPI_clockGet) (void);
74 
75 
82 #define MCSPI_STATUS_SUCCESS ((int32_t)0)
83 
87 #define MCSPI_STATUS_FAILURE ((int32_t)-1)
88 
92 #define MCSPI_TIMEOUT ((int32_t)-2)
93 
97 #define MCSPI_INVALID_PARAM ((int32_t)-3)
98 
102 #define MCSPI_STATUS_BUSY ((int32_t)-4)
103 
107 #define MCSPI_INVALID_STATE ((int32_t)-5)
108 
117 #define MCSPI_NO_WAIT ((uint32_t)0)
118 
122 #define MCSPI_WAIT_FOREVER ((uint32_t)-1)
123 
131 #define MCSPI_STATE_RESET ((uint32_t)0U)
132 
136 #define MCSPI_STATE_READY ((uint32_t)1U)
137 
141 #define MCSPI_STATE_BUSY ((uint32_t)2U)
142 
146 #define MCSPI_STATE_ERROR ((uint32_t)3U)
147 
158 #define MCSPI_CHANNEL_0 (0U)
159 #define MCSPI_CHANNEL_1 (1U)
160 #define MCSPI_CHANNEL_2 (2U)
161 #define MCSPI_CHANNEL_3 (3U)
162 
172 #define MCSPI_OPER_MODE_POLLED (0U)
173 #define MCSPI_OPER_MODE_INTERRUPT (1U)
174 #define MCSPI_OPER_MODE_DMA (2U)
175 
178 #define MCSPI_MAX_NUM_CHANNELS (4U)
179 
188 #define MCSPI_TRANSFER_COMPLETED ((int32_t)0U)
189 #define MCSPI_TRANSFER_STARTED ((int32_t)1U)
190 #define MCSPI_TRANSFER_CANCELLED ((int32_t)2U)
191 #define MCSPI_TRANSFER_FAILED ((int32_t)3U)
192 #define MCSPI_TRANSFER_CSN_DEASSERT ((int32_t)4U)
193 #define MCSPI_TRANSFER_TIMEOUT ((int32_t)5U)
194 
212 #define MCSPI_MS_MODE_CONTROLLER (CSL_MCSPI_MODULCTRL_MS_MASTER)
213 
214 #define MCSPI_MS_MODE_PERIPHERAL (CSL_MCSPI_MODULCTRL_MS_SLAVE)
215 
231 #define MCSPI_FF_POL0_PHA0 (0U)
232 #define MCSPI_FF_POL0_PHA1 (1U)
233 #define MCSPI_FF_POL1_PHA0 (2U)
234 #define MCSPI_FF_POL1_PHA1 (3U)
235 
246 #define MCSPI_CS_POL_HIGH (CSL_MCSPI_CH0CONF_EPOL_ACTIVEHIGH)
247 
248 #define MCSPI_CS_POL_LOW (CSL_MCSPI_CH0CONF_EPOL_ACTIVELOW)
249 
257 #define MCSPI_TR_MODE_TX_RX (CSL_MCSPI_CH0CONF_TRM_TRANSRECEI)
258 #define MCSPI_TR_MODE_RX_ONLY (CSL_MCSPI_CH0CONF_TRM_RECEIVONLY)
259 #define MCSPI_TR_MODE_TX_ONLY (CSL_MCSPI_CH0CONF_TRM_TRANSONLY)
260 
269 #define MCSPI_IS_D0 (CSL_MCSPI_CH0CONF_IS_LINE0)
270 
271 #define MCSPI_IS_D1 (CSL_MCSPI_CH0CONF_IS_LINE1)
272 
281 #define MCSPI_DPE_ENABLE (CSL_MCSPI_CH0CONF_DPE0_ENABLED)
282 
283 #define MCSPI_DPE_DISABLE (CSL_MCSPI_CH0CONF_DPE0_DISABLED)
284 
292 #define MCSPI_SLV_CS_SELECT_0 (CSL_MCSPI_CH0CONF_SPIENSLV_SPIEN0)
293 #define MCSPI_SLV_CS_SELECT_1 (CSL_MCSPI_CH0CONF_SPIENSLV_SPIEN1)
294 #define MCSPI_SLV_CS_SELECT_2 (CSL_MCSPI_CH0CONF_SPIENSLV_SPIEN2)
295 #define MCSPI_SLV_CS_SELECT_3 (CSL_MCSPI_CH0CONF_SPIENSLV_SPIEN3)
296 
305 #define MCSPI_SB_POL_HIGH (CSL_MCSPI_CH0CONF_SBPOL_HIGHLEVEL)
306 
307 #define MCSPI_SB_POL_LOW (CSL_MCSPI_CH0CONF_SBPOL_LOWLEVEL)
308 
319 #define MCSPI_TCS0_0_CLK (CSL_MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY)
320 
321 #define MCSPI_TCS0_1_CLK (CSL_MCSPI_CH0CONF_TCS0_ONECYCLEDLY)
322 
323 #define MCSPI_TCS0_2_CLK (CSL_MCSPI_CH0CONF_TCS0_TWOCYCLEDLY)
324 
325 #define MCSPI_TCS0_3_CLK (CSL_MCSPI_CH0CONF_TCS0_THREECYCLEDLY)
326 
338 #define MCSPI_CH_MODE_SINGLE (CSL_MCSPI_MODULCTRL_SINGLE_SINGLE)
339 
340 #define MCSPI_CH_MODE_MULTI (CSL_MCSPI_MODULCTRL_SINGLE_MULTI)
341 
353 #define MCSPI_PINMODE_3PIN (CSL_MCSPI_MODULCTRL_PIN34_3PINMODE)
354 #define MCSPI_PINMODE_4PIN (CSL_MCSPI_MODULCTRL_PIN34_4PINMODE)
355 
366 #define MCSPI_INITDLY_0 (CSL_MCSPI_MODULCTRL_INITDLY_NODELAY)
367 
368 #define MCSPI_INITDLY_4 (CSL_MCSPI_MODULCTRL_INITDLY_4CLKDLY)
369 
370 #define MCSPI_INITDLY_8 (CSL_MCSPI_MODULCTRL_INITDLY_8CLKDLY)
371 
372 #define MCSPI_INITDLY_16 (CSL_MCSPI_MODULCTRL_INITDLY_16CLKDLY)
373 
374 #define MCSPI_INITDLY_32 (CSL_MCSPI_MODULCTRL_INITDLY_32CLKDLY)
375 
378 #define MCSPI_ERROR_TX_UNDERFLOW (0x00000001U)
379 #define MCSPI_ERROR_RX_OVERFLOW (0x00000002U)
380 
382 #define MCSPI_MAX_CLK_DIVIDER_SUPPORTED (4096U)
383 
404 #define MCSPI_DMA_MAX_TRANSFER_BYTES (4095U)
405 
406 /* ========================================================================== */
407 /* Advanced Macros & Typedefs */
408 /* ========================================================================== */
409 
411 #define MCSPI_FIFO_LENGTH (64U)
412 
415 #define MCSPI_RX_FIFO_ENABLE ((uint32_t) CSL_MCSPI_CH0CONF_FFER_FFENABLED \
416  << \
417  CSL_MCSPI_CH0CONF_FFER_SHIFT)
418 
422 #define MCSPI_RX_FIFO_DISABLE ((uint32_t) CSL_MCSPI_CH0CONF_FFER_FFDISABLED \
423  << CSL_MCSPI_CH0CONF_FFER_SHIFT)
424 
428 #define MCSPI_TX_FIFO_ENABLE ((uint32_t) CSL_MCSPI_CH0CONF_FFEW_FFENABLED \
429  << CSL_MCSPI_CH0CONF_FFEW_SHIFT)
430 
434 #define MCSPI_TX_FIFO_DISABLE ((uint32_t) CSL_MCSPI_CH0CONF_FFEW_FFDISABLED \
435  << CSL_MCSPI_CH0CONF_FFEW_SHIFT)
436 
440 #define MCSPI_REG_OFFSET (0x14U)
441 
442 #define MCSPI_CHCONF(x) ((uint32_t) CSL_MCSPI_CH0CONF + \
443  (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
444  (uint32_t) (x)))
445 
446 #define MCSPI_CHSTAT(x) ((uint32_t) CSL_MCSPI_CH0STAT + \
447  (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
448  (uint32_t) (x)))
449 
450 #define MCSPI_CHCTRL(x) ((uint32_t) CSL_MCSPI_CH0CTRL + \
451  (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
452  (uint32_t) (x)))
453 
454 #define MCSPI_CHTX(x) ((uint32_t) CSL_MCSPI_TX0 + \
455  (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
456  (uint32_t) (x)))
457 
458 #define MCSPI_CHRX(x) ((uint32_t) CSL_MCSPI_RX0 + \
459  (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
460  (uint32_t) (x)))
461 
462 #define MCSPI_CLKD_MASK (0x0FU)
463 
465 #define MCSPI_IRQSTATUS_CLEAR_ALL (CSL_MCSPI_IRQSTATUS_EOW_MASK | \
466  CSL_MCSPI_IRQSTATUS_WKS_MASK | \
467  CSL_MCSPI_IRQSTATUS_RX3_FULL_MASK | \
468  CSL_MCSPI_IRQSTATUS_TX3_UNDERFLOW_MASK | \
469  CSL_MCSPI_IRQSTATUS_TX3_EMPTY_MASK | \
470  CSL_MCSPI_IRQSTATUS_RX2_FULL_MASK | \
471  CSL_MCSPI_IRQSTATUS_TX2_UNDERFLOW_MASK | \
472  CSL_MCSPI_IRQSTATUS_TX2_EMPTY_MASK | \
473  CSL_MCSPI_IRQSTATUS_RX1_FULL_MASK | \
474  CSL_MCSPI_IRQSTATUS_TX1_UNDERFLOW_MASK | \
475  CSL_MCSPI_IRQSTATUS_TX1_EMPTY_MASK | \
476  CSL_MCSPI_IRQSTATUS_RX0_OVERFLOW_MASK | \
477  CSL_MCSPI_IRQSTATUS_RX0_FULL_MASK | \
478  CSL_MCSPI_IRQSTATUS_TX0_UNDERFLOW_MASK | \
479  CSL_MCSPI_IRQSTATUS_TX0_EMPTY_MASK)
480 
481 /* ========================================================================== */
482 /* Structure Declarations */
483 /* ========================================================================== */
484 
493 typedef struct
494 {
495  uint32_t channel;
498  uint32_t csDisable;
504  uint32_t dataSize;
515  uint32_t count;
518  void *txBuf;
529  void *rxBuf;
536  void *args;
538  uint32_t timeout;
540  uint32_t status;
542 } MCSPI_Transaction;
543 
553 typedef struct MCSPI_ExtendedParams_s
554 {
555  uint32_t channel;
558  uint32_t csDisable;
564  uint32_t dataSize;
575  void *args;
577 } MCSPI_ExtendedParams;
578 
590 typedef struct
591 {
592  uint32_t chNum;
594  uint32_t frameFormat;
596  uint32_t bitRate;
598  uint32_t csPolarity;
600  uint32_t trMode;
602  uint32_t inputSelect;
604  uint32_t dpe0;
606  uint32_t dpe1;
608  uint32_t slvCsSelect;
611  uint32_t startBitEnable;
614  uint32_t startBitPolarity;
617  uint32_t turboEnable;
619  uint32_t csIdleTime;
622  uint32_t defaultTxData;
625  uint32_t txFifoTrigLvl;
627  uint32_t rxFifoTrigLvl;
629 } MCSPI_ChConfig;
630 
631 /* ========================================================================== */
632 /* Function pointers Declarations */
633 /* ========================================================================== */
634 
642 typedef void (*MCSPI_transferCallbackFxn) (void *args, uint32_t transferStatus);
643 
651 typedef void (*MCSPI_errorCallbackFxn) (void *args, uint32_t transferStatus);
652 
653 /* ========================================================================== */
654 /* Internal/Private Structure Declarations */
655 /* ========================================================================== */
656 
660 typedef struct
661 {
662  /*
663  * User parameters
664  */
665  MCSPI_ChConfig *chCfg;
667  uint32_t dmaChConfigNum;
670  /*
671  * State variables
672  */
673  uint32_t isOpen;
675  uint32_t csDisable;
677  uint32_t csEnable;
679  uint8_t *curTxBufPtr;
681  uint8_t *curRxBufPtr;
683  uint32_t curTxWords;
687  uint32_t curRxWords;
690  /*
691  * MCSPI derived variables
692  */
693  uint8_t bufWidthShift;
699  uint32_t dataWidthBitMask;
701  uint32_t effTxFifoDepth;
703  uint32_t effRxFifoDepth;
705  uint32_t intrMask;
707  MCSPI_DmaChConfig dmaChCfg;
709  uint32_t chConfRegVal;
711  uint32_t chCtrlRegVal;
713  uint32_t systRegVal;
714 } MCSPI_ChObject;
715 
719 typedef struct
720 {
721  uint32_t inputClkFreq;
723  uint32_t intrNum;
725  uint32_t operMode;
727  uint8_t intrPriority;
729  uint32_t chMode;
731  uint32_t pinMode;
733  uint32_t initDelay;
735  uint32_t multiWordAccess;
737  uint32_t msMode;
739  uint32_t chEnabled[MCSPI_MAX_NUM_CHANNELS];
741  MCSPI_ChObject chObj[MCSPI_MAX_NUM_CHANNELS];
743  MCSPI_DmaHandle mcspiDmaHandle;
745  MCSPI_clockGet clockP_get;
746  /* clock usec to tick */
747  MCSPI_transferCallbackFxn transferCallbackFxn;
749  MCSPI_errorCallbackFxn errorCallbackFxn;
751 } MCSPILLD_InitObject, *MCSPILLD_InitHandle;
752 
756 typedef struct
757 {
758  uint32_t baseAddr;
761  /*
762  * User parameters
763  */
764  uint32_t state;
766  void *transferMutex;
768  MCSPILLD_InitHandle hMcspiInit;
770  uint32_t errorFlag;
773  /*
774  * Transfer parameters
775  */
776  uint32_t transferChannel;
778  uint32_t transferCsDisable;
780  uint32_t transferDataSize;
782  MCSPI_Transaction transaction;
784  void* args;
786 } MCSPILLD_Object, *MCSPILLD_Handle;
787 
788 /* ========================================================================== */
789 /* Function Declarations */
790 /* ========================================================================== */
791 
792 /* Low level HW functions */
793 void MCSPI_reset(uint32_t baseAddr);
794 void MCSPI_clearAllIrqStatus(uint32_t baseAddr);
795 void MCSPI_stop(MCSPILLD_Handle hMcspi, MCSPI_ChObject *chObj, uint32_t chNum);
796 void MCSPI_setChDataSize(uint32_t baseAddr, MCSPI_ChObject *chObj,
797  uint32_t dataSize, uint32_t csDisable);
798 
799 static inline void MCSPI_intrStatusClear(const MCSPI_ChObject *chObj,
800  uint32_t baseAddr, uint32_t intFlags)
801 {
802  /* Clear the SSB bit in the MCSPI_SYST register. */
803  CSL_REG32_WR(baseAddr + CSL_MCSPI_SYST, chObj->systRegVal);
804  /* Clear the interrupt status. */
805  CSL_REG32_WR(baseAddr + CSL_MCSPI_IRQSTATUS, intFlags);
806 }
807 
808 /* ========================================================================== */
809 /* Function Declarations */
810 /* ========================================================================== */
811 
820 int32_t MCSPI_lld_init(MCSPILLD_Handle hMcspi);
821 
830 int32_t MCSPI_lld_initDma(MCSPILLD_Handle hMcspi);
839 int32_t MCSPI_lld_deInit(MCSPILLD_Handle hMcspi);
840 
849 int32_t MCSPI_lld_deInitDma(MCSPILLD_Handle hMcspi);
850 
863 int32_t MCSPI_lld_write(MCSPILLD_Handle hMcspi, void *txBuf, uint32_t count, uint32_t timeout,
864  const MCSPI_ExtendedParams *extendedParams);
865 
878 int32_t MCSPI_lld_writeIntr(MCSPILLD_Handle hMcspi, void *txBuf, uint32_t count, uint32_t timeout,
879  const MCSPI_ExtendedParams *extendedParams);
880 
893 int32_t MCSPI_lld_writeDma(MCSPILLD_Handle hMcspi, void * txBuf, uint32_t count,
894  uint32_t timeout, const MCSPI_ExtendedParams *extendedParams);
895 
908 int32_t MCSPI_lld_read(MCSPILLD_Handle hMcspi, void * rxBuf, uint32_t count, uint32_t timeout,
909  const MCSPI_ExtendedParams *extendedParams);
910 
923 int32_t MCSPI_lld_readIntr(MCSPILLD_Handle hMcspi, void * rxBuf, uint32_t count, uint32_t timeout,
924  const MCSPI_ExtendedParams *extendedParams);
925 
939 int32_t MCSPI_lld_readDma(MCSPILLD_Handle hMcspi, void * rxBuf, uint32_t count,
940  uint32_t timeout, const MCSPI_ExtendedParams *extendedParams);
953 int32_t MCSPI_lld_readWrite(MCSPILLD_Handle hMcspi, void *txBuf, void *rxBuf, uint32_t count,
954  uint32_t timeout, const MCSPI_ExtendedParams *extendedParams);
967 int32_t MCSPI_lld_readWriteIntr(MCSPILLD_Handle hMcspi, void *txBuf, void *rxBuf, uint32_t count,
968  uint32_t timeout, const MCSPI_ExtendedParams *extendedParams);
981 int32_t MCSPI_lld_readWriteDma(MCSPILLD_Handle hMcspi, void *txBuf, void *rxBuf, uint32_t count,
982  uint32_t timeout, const MCSPI_ExtendedParams *extendedParams);
983 
992 int32_t MCSPI_lld_readWriteCancel(MCSPILLD_Handle hMcspi);
993 
1002 int32_t MCSPI_lld_readWriteDmaCancel(MCSPILLD_Handle hMcspi);
1003 
1013 int32_t MCSPI_lld_transfer(MCSPILLD_Handle hMcspi, MCSPI_Transaction *transaction);
1014 
1024 int32_t MCSPI_lld_transferIntr(MCSPILLD_Handle hMcspi, MCSPI_Transaction *transaction);
1025 
1035 int32_t MCSPI_lld_transferDma(MCSPILLD_Handle hMcspi, MCSPI_Transaction *transaction);
1036 
1043 void MCSPI_lld_controllerIsr(void* args);
1044 
1051 void MCSPI_lld_peripheralIsr(void* args);
1052 
1059 int32_t MCSPI_lld_getState(MCSPILLD_Handle hMcspi);
1060 
1069 int32_t MCSPI_lld_transferCancel(MCSPILLD_Handle hMcspi);
1070 
1079 int32_t MCSPI_lld_transferDmaCancel(MCSPILLD_Handle hMcspi);
1080 
1087 static inline void MCSPI_lld_ChConfig_init(MCSPI_ChConfig *chConfig);
1088 
1095 static inline void MCSPI_lld_Transaction_init(MCSPI_Transaction *trans);
1096 
1105 uint32_t MCSPI_lld_getBaseAddr(MCSPILLD_Handle handle);
1106 
1118 int32_t MCSPI_lld_reConfigFifo(MCSPILLD_Handle handle,
1119  uint32_t chNum,
1120  uint32_t numWordsRxTx);
1121 
1132 void MCSPI_initiateLastChunkTransfer(MCSPILLD_Handle hMcspi,
1133  MCSPI_ChObject *chObj,
1134  const MCSPI_Transaction *transaction);
1135 
1150 static inline uint8_t MCSPI_getBufWidthShift(uint32_t dataSize);
1151 
1175 static inline uint32_t MCSPI_readChStatusReg(uint32_t baseAddr, uint32_t chNum);
1176 
1187 static inline uint32_t MCSPI_readChCtrlReg(uint32_t baseAddr, uint32_t chNum);
1188 
1198 static inline void MCSPI_writeChCtrlReg(uint32_t baseAddr, uint32_t chNum,
1199  uint32_t regVal);
1200 
1211 static inline uint32_t MCSPI_readChConf(uint32_t baseAddr, uint32_t chNum);
1212 
1222 static inline void MCSPI_writeChConfReg(uint32_t baseAddr, uint32_t chNum,
1223  uint32_t regVal);
1224 
1241 static inline void MCSPI_writeTxDataReg(uint32_t baseAddr,
1242  uint32_t txData,
1243  uint32_t chNum);
1244 
1264 static inline void MCSPI_enableTxFIFO(uint32_t baseAddr, uint32_t chNum,
1265  uint32_t enableFlag);
1266 
1286 static inline void MCSPI_enableRxFIFO(uint32_t baseAddr, uint32_t chNum,
1287  uint32_t enableFlag);
1288 
1304 static inline uint32_t MCSPI_readRxDataReg(uint32_t baseAddr,
1305  uint32_t chNum);
1306 
1323 static inline void MCSPI_setDataWidth(uint32_t baseAddr, uint32_t chNum,
1324  uint32_t dataWidth);
1325 
1344 int32_t MCSPI_lld_dmaInit(MCSPI_DmaHandle mcspiDmaHandle);
1345 
1357 int32_t MCSPI_lld_dmaDeInit(MCSPILLD_Handle hMcspi, const MCSPI_ChConfig *chCfg, uint32_t chCnt);
1358 
1369 int32_t MCSPI_lld_dmaChInit(MCSPILLD_Handle hMcspi, uint32_t chCnt);
1370 
1383 int32_t MCSPI_lld_dmaTransfer(MCSPILLD_Handle hMcspi, MCSPI_ChObject *chObj, const MCSPI_Transaction *transaction);
1384 
1396 void MCSPI_lld_dmaStop(MCSPILLD_Handle hMcspi, MCSPI_ChObject *chObj, uint32_t chNum);
1397 
1400 /* ========================================================================== */
1401 /* Static Function Definitions */
1402 /* ========================================================================== */
1403 
1404 static inline void MCSPI_lld_ChConfig_init(MCSPI_ChConfig *chConfig)
1405 {
1406  if(chConfig != NULL)
1407  {
1408  chConfig->chNum = MCSPI_CHANNEL_0;
1409  chConfig->frameFormat = MCSPI_FF_POL0_PHA0;
1410  chConfig->bitRate = 1000000U;
1411  chConfig->csPolarity = MCSPI_CS_POL_LOW;
1412  chConfig->trMode = MCSPI_TR_MODE_TX_RX;
1413  chConfig->inputSelect = MCSPI_IS_D1;
1414  chConfig->dpe0 = MCSPI_DPE_ENABLE;
1415  chConfig->dpe1 = MCSPI_DPE_DISABLE;
1416  chConfig->slvCsSelect = MCSPI_SLV_CS_SELECT_0;
1417  chConfig->startBitEnable = FALSE;
1418  chConfig->startBitPolarity = MCSPI_SB_POL_LOW;
1419  chConfig->csIdleTime = MCSPI_TCS0_0_CLK;
1420  chConfig->defaultTxData = 0x00000000U;
1421  }
1422 }
1423 
1424 static inline void MCSPI_lld_Transaction_init(MCSPI_Transaction *trans)
1425 {
1426  if(trans != NULL)
1427  {
1428  trans->channel = 0U;
1429  trans->csDisable = TRUE;
1430  trans->dataSize = 8U;
1431  trans->count = 0U;
1432  trans->txBuf = NULL;
1433  trans->rxBuf = NULL;
1434  trans->args = NULL;
1435  trans->timeout = MCSPI_WAIT_FOREVER;
1436  }
1437 }
1438 
1439 static inline uint8_t MCSPI_getBufWidthShift(uint32_t dataSize)
1440 {
1441  uint8_t bufWidthShift = 0U;
1442 
1443  if(dataSize <= 8U)
1444  {
1445  bufWidthShift = 0U;
1446  }
1447  else if(dataSize <= 16U)
1448  {
1449  bufWidthShift = 1U;
1450  }
1451  else
1452  {
1453  bufWidthShift = 2U;
1454  }
1455 
1456  return bufWidthShift;
1457 }
1458 
1459 static inline uint32_t MCSPI_readChStatusReg(uint32_t baseAddr, uint32_t chNum)
1460 {
1461  /* Return the status from MCSPI_CHSTAT register. */
1462  return (CSL_REG32_RD(baseAddr + MCSPI_CHSTAT(chNum)));
1463 }
1464 
1465 static inline uint32_t MCSPI_readChCtrlReg(uint32_t baseAddr, uint32_t chNum)
1466 {
1467  return CSL_REG32_RD(baseAddr + MCSPI_CHCTRL(chNum));
1468 }
1469 
1470 static inline void MCSPI_writeChCtrlReg(uint32_t baseAddr, uint32_t chNum,
1471  uint32_t regVal)
1472 {
1473  CSL_REG32_WR(baseAddr + MCSPI_CHCTRL(chNum), regVal);
1474 }
1475 
1476 static inline uint32_t MCSPI_readChConf(uint32_t baseAddr, uint32_t chNum)
1477 {
1478  return CSL_REG32_RD(baseAddr + MCSPI_CHCONF(chNum));
1479 }
1480 
1481 static inline void MCSPI_writeChConfReg(uint32_t baseAddr, uint32_t chNum,
1482  uint32_t regVal)
1483 {
1484  CSL_REG32_WR(baseAddr + MCSPI_CHCONF(chNum), regVal);
1485 }
1486 
1487 static inline void MCSPI_writeTxDataReg(uint32_t baseAddr,
1488  uint32_t txData,
1489  uint32_t chNum)
1490 {
1491  /* Load the MCSPI_TX register with the data to be transmitted */
1492  CSL_REG32_WR(baseAddr + MCSPI_CHTX(chNum), txData);
1493 }
1494 
1495 static inline void MCSPI_enableTxFIFO(uint32_t baseAddr,
1496  uint32_t chNum,
1497  uint32_t enableFlag)
1498 {
1499  /* Set the FFEW field with user sent value. */
1500  CSL_REG32_FINS(
1501  baseAddr + MCSPI_CHCONF(chNum),
1502  MCSPI_CH0CONF_FFEW,
1503  enableFlag >> CSL_MCSPI_CH0CONF_FFEW_SHIFT);
1504 }
1505 
1506 static inline void MCSPI_enableRxFIFO(uint32_t baseAddr,
1507  uint32_t chNum,
1508  uint32_t enableFlag)
1509 {
1510  /* Set the FFER field with the user sent value. */
1511  CSL_REG32_FINS(
1512  baseAddr + MCSPI_CHCONF(chNum),
1513  MCSPI_CH0CONF_FFER,
1514  enableFlag >> CSL_MCSPI_CH0CONF_FFER_SHIFT);
1515 }
1516 
1517 static inline uint32_t MCSPI_readRxDataReg(uint32_t baseAddr, uint32_t chNum)
1518 {
1519  /* Return the data present in the MCSPI_RX register. */
1520  return (CSL_REG32_RD(baseAddr + MCSPI_CHRX(chNum)));
1521 }
1522 
1523 static inline void MCSPI_setDataWidth(uint32_t baseAddr, uint32_t chNum,
1524  uint32_t dataWidth)
1525 {
1526  uint32_t regVal;
1527 
1528  regVal = CSL_REG32_RD(baseAddr + MCSPI_CHCONF(chNum));
1529  CSL_FINS(regVal, MCSPI_CH0CONF_WL, (dataWidth - 1U));
1530  CSL_REG32_WR(baseAddr + MCSPI_CHCONF(chNum), regVal);
1531 }
1532 
1533 #ifdef __cplusplus
1534 }
1535 #endif
1536 
1537 #endif /* #ifndef MCSPI_LLD_H_ */
1538 
MCSPI_lld_readWriteDmaCancel
int32_t MCSPI_lld_readWriteDmaCancel(MCSPILLD_Handle hMcspi)
This API cancels current McSPI transfer in DMA mode.
MCSPILLD_InitObject::pinMode
uint32_t pinMode
Definition: mcspi_lld.h:731
MCSPI_getBufWidthShift
static uint8_t MCSPI_getBufWidthShift(uint32_t dataSize)
This API will return the buffer width in bytes based on dataSize.
Definition: mcspi_lld.h:1439
MCSPI_lld_dmaDeInit
int32_t MCSPI_lld_dmaDeInit(MCSPILLD_Handle hMcspi, const MCSPI_ChConfig *chCfg, uint32_t chCnt)
API to close an MCSPI DMA channel.
MCSPI_clockGet
uint32_t(* MCSPI_clockGet)(void)
Definition: mcspi_lld.h:73
MCSPI_ChObject::curTxBufPtr
uint8_t * curTxBufPtr
Definition: mcspi_lld.h:679
MCSPILLD_InitObject
MCSPI driver initialization object.
Definition: mcspi_lld.h:720
MCSPI_ChObject
MCSPI channel object.
Definition: mcspi_lld.h:661
MCSPI_Transaction::count
uint32_t count
Definition: mcspi_lld.h:515
MCSPI_ChConfig::txFifoTrigLvl
uint32_t txFifoTrigLvl
Definition: mcspi_lld.h:625
MCSPI_CHTX
#define MCSPI_CHTX(x)
Base address of McSPI_CHTX(x)
Definition: mcspi_lld.h:454
MCSPI_FF_POL0_PHA0
#define MCSPI_FF_POL0_PHA0
Definition: mcspi_lld.h:231
MCSPI_ChConfig::rxFifoTrigLvl
uint32_t rxFifoTrigLvl
Definition: mcspi_lld.h:627
MCSPILLD_InitObject::intrNum
uint32_t intrNum
Definition: mcspi_lld.h:723
MCSPI_lld_readWriteCancel
int32_t MCSPI_lld_readWriteCancel(MCSPILLD_Handle hMcspi)
This API cancels current McSPI transfer.
MCSPI_DPE_DISABLE
#define MCSPI_DPE_DISABLE
No transmission on Data Line.
Definition: mcspi_lld.h:283
MCSPI_Transaction::status
uint32_t status
Definition: mcspi_lld.h:540
MCSPI_Transaction
Data structure used with MCSPI_transfer()
Definition: mcspi_lld.h:494
MCSPI_ChObject::effTxFifoDepth
uint32_t effTxFifoDepth
Definition: mcspi_lld.h:701
MCSPI_TCS0_0_CLK
#define MCSPI_TCS0_0_CLK
0.5 clock cycles delay
Definition: mcspi_lld.h:319
MCSPI_writeTxDataReg
static void MCSPI_writeTxDataReg(uint32_t baseAddr, uint32_t txData, uint32_t chNum)
This API will put the data on to the McSPI Channel transmit register.
Definition: mcspi_lld.h:1487
MCSPILLD_Object::transferDataSize
uint32_t transferDataSize
Definition: mcspi_lld.h:780
MCSPI_lld_getBaseAddr
uint32_t MCSPI_lld_getBaseAddr(MCSPILLD_Handle handle)
Function to get base address of MCSPI instance of a particular handle.
MCSPI_ChObject::intrMask
uint32_t intrMask
Definition: mcspi_lld.h:705
MCSPILLD_InitObject::clockP_get
MCSPI_clockGet clockP_get
Definition: mcspi_lld.h:745
MCSPI_WAIT_FOREVER
#define MCSPI_WAIT_FOREVER
Value to use when needing a timeout of infinity or wait forver until resource is available.
Definition: mcspi_lld.h:122
MCSPI_ChObject::chConfRegVal
uint32_t chConfRegVal
Definition: mcspi_lld.h:709
MCSPI_DmaChConfig
struct MCSPI_DmaChConfig_s * MCSPI_DmaChConfig
Definition: mcspi_dma_udma.h:94
MCSPI_enableTxFIFO
static void MCSPI_enableTxFIFO(uint32_t baseAddr, uint32_t chNum, uint32_t enableFlag)
This API will enable/disable the Tx FIFOs of McSPI peripheral.
Definition: mcspi_lld.h:1495
MCSPI_lld_transferCancel
int32_t MCSPI_lld_transferCancel(MCSPILLD_Handle hMcspi)
This API cancels current McSPI transfer.
MCSPILLD_Object::errorFlag
uint32_t errorFlag
Definition: mcspi_lld.h:770
MCSPI_SLV_CS_SELECT_0
#define MCSPI_SLV_CS_SELECT_0
Definition: mcspi_lld.h:292
MCSPILLD_InitObject::intrPriority
uint8_t intrPriority
Definition: mcspi_lld.h:727
MCSPI_errorCallbackFxn
void(* MCSPI_errorCallbackFxn)(void *args, uint32_t transferStatus)
The definition of a error callback function used by the SPI driver when used in MCSPI_TRANSFER_MODE_C...
Definition: mcspi_lld.h:651
MCSPI_ChObject::dmaChConfigNum
uint32_t dmaChConfigNum
Definition: mcspi_lld.h:667
MCSPI_CHCONF
#define MCSPI_CHCONF(x)
Base address of McSPI_CHCONF(x)
Definition: mcspi_lld.h:442
MCSPI_lld_controllerIsr
void MCSPI_lld_controllerIsr(void *args)
This is the McSPI Controller ISR and can be used as IRQ handler in Controller mode.
MCSPI_lld_readWriteIntr
int32_t MCSPI_lld_readWriteIntr(MCSPILLD_Handle hMcspi, void *txBuf, void *rxBuf, uint32_t count, uint32_t timeout, const MCSPI_ExtendedParams *extendedParams)
This API reads writes data from the McSPI instance in Interrupt mode.
MCSPI_ChConfig::bitRate
uint32_t bitRate
Definition: mcspi_lld.h:596
MCSPI_lld_dmaTransfer
int32_t MCSPI_lld_dmaTransfer(MCSPILLD_Handle hMcspi, MCSPI_ChObject *chObj, const MCSPI_Transaction *transaction)
API to do a DMA transfer using a specific DMA driver - UDMA, EDMA etc.
MCSPI_ExtendedParams::args
void * args
Definition: mcspi_lld.h:575
MCSPILLD_InitObject::transferCallbackFxn
MCSPI_transferCallbackFxn transferCallbackFxn
Definition: mcspi_lld.h:747
MCSPI_lld_read
int32_t MCSPI_lld_read(MCSPILLD_Handle hMcspi, void *rxBuf, uint32_t count, uint32_t timeout, const MCSPI_ExtendedParams *extendedParams)
This API reads data from the McSPI instance in Polling mode.
MCSPI_lld_Transaction_init
static void MCSPI_lld_Transaction_init(MCSPI_Transaction *trans)
Function to initialize the MCSPI_Transaction struct to its defaults.
Definition: mcspi_lld.h:1424
MCSPILLD_Object
MCSPI driver object.
Definition: mcspi_lld.h:757
MCSPI_SB_POL_LOW
#define MCSPI_SB_POL_LOW
Start-bit polarity is held to 0 during MCSPI transfer.
Definition: mcspi_lld.h:307
MCSPI_Transaction::timeout
uint32_t timeout
Definition: mcspi_lld.h:538
MCSPI_readRxDataReg
static uint32_t MCSPI_readRxDataReg(uint32_t baseAddr, uint32_t chNum)
This API will return the data present in the MCSPI_RX register.
Definition: mcspi_lld.h:1517
MCSPI_DPE_ENABLE
#define MCSPI_DPE_ENABLE
Data line selected for transmission.
Definition: mcspi_lld.h:281
MCSPI_Transaction::csDisable
uint32_t csDisable
Definition: mcspi_lld.h:498
MCSPI_IS_D1
#define MCSPI_IS_D1
Data line 1 (SPIDAT[1]) selected for reception.
Definition: mcspi_lld.h:271
MCSPI_ChObject::chCtrlRegVal
uint32_t chCtrlRegVal
Definition: mcspi_lld.h:711
MCSPILLD_InitHandle
struct MCSPILLD_InitObject * MCSPILLD_InitHandle
MCSPI_lld_peripheralIsr
void MCSPI_lld_peripheralIsr(void *args)
This is the McSPI Peripheral ISR and can be used as IRQ handler in Peripheral mode.
MCSPI_CHRX
#define MCSPI_CHRX(x)
Base address of McSPI_CHRX(x)
Definition: mcspi_lld.h:458
MCSPI_lld_writeDma
int32_t MCSPI_lld_writeDma(MCSPILLD_Handle hMcspi, void *txBuf, uint32_t count, uint32_t timeout, const MCSPI_ExtendedParams *extendedParams)
This API writes data to the McSPI instance in DMA mode.
MCSPI_ChConfig::trMode
uint32_t trMode
Definition: mcspi_lld.h:600
MCSPI_transferCallbackFxn
void(* MCSPI_transferCallbackFxn)(void *args, uint32_t transferStatus)
The definition of a transfer completion callback function used by the SPI driver when used in MCSPI_T...
Definition: mcspi_lld.h:642
MCSPILLD_Object::hMcspiInit
MCSPILLD_InitHandle hMcspiInit
Definition: mcspi_lld.h:768
MCSPI_TR_MODE_TX_RX
#define MCSPI_TR_MODE_TX_RX
Definition: mcspi_lld.h:257
MCSPI_CHSTAT
#define MCSPI_CHSTAT(x)
Base address of McSPI_CHSTAT(x)
Definition: mcspi_lld.h:446
MCSPI_CHANNEL_0
#define MCSPI_CHANNEL_0
Definition: mcspi_lld.h:158
MCSPILLD_Object::transferChannel
uint32_t transferChannel
Definition: mcspi_lld.h:776
MCSPI_lld_ChConfig_init
static void MCSPI_lld_ChConfig_init(MCSPI_ChConfig *chConfig)
Function to initialize the MCSPI_ChConfig struct to its defaults.
Definition: mcspi_lld.h:1404
MCSPI_ChObject::isOpen
uint32_t isOpen
Definition: mcspi_lld.h:673
MCSPI_readChCtrlReg
static uint32_t MCSPI_readChCtrlReg(uint32_t baseAddr, uint32_t chNum)
This API returns Channel control register value.
Definition: mcspi_lld.h:1465
MCSPILLD_Object::state
uint32_t state
Definition: mcspi_lld.h:764
MCSPI_lld_initDma
int32_t MCSPI_lld_initDma(MCSPILLD_Handle hMcspi)
This API Initializes the McSPI instance in DMA Mode.
MCSPI_lld_deInitDma
int32_t MCSPI_lld_deInitDma(MCSPILLD_Handle hMcspi)
This API De-Initializes the McSPI instance in DMA mode.
MCSPI_lld_dmaChInit
int32_t MCSPI_lld_dmaChInit(MCSPILLD_Handle hMcspi, uint32_t chCnt)
API to init a DMA Channel opened.
MCSPI_lld_transfer
int32_t MCSPI_lld_transfer(MCSPILLD_Handle hMcspi, MCSPI_Transaction *transaction)
This API transfers data from the McSPI instance in Polling mode.
MCSPI_initiateLastChunkTransfer
void MCSPI_initiateLastChunkTransfer(MCSPILLD_Handle hMcspi, MCSPI_ChObject *chObj, const MCSPI_Transaction *transaction)
This API will initiate the last chuncks when FIFO is enabled. The byte thats are non-multiple of FIFO...
MCSPI_ChObject::curRxWords
uint32_t curRxWords
Definition: mcspi_lld.h:687
count
uint16_t count
Definition: tisci_pm_device.h:1
MCSPI_lld_transferDmaCancel
int32_t MCSPI_lld_transferDmaCancel(MCSPILLD_Handle hMcspi)
This API cancels current McSPI transfer in DMA mode.
MCSPI_lld_init
int32_t MCSPI_lld_init(MCSPILLD_Handle hMcspi)
This API Initializes the McSPI instance.
MCSPI_clearAllIrqStatus
void MCSPI_clearAllIrqStatus(uint32_t baseAddr)
MCSPI_lld_transferDma
int32_t MCSPI_lld_transferDma(MCSPILLD_Handle hMcspi, MCSPI_Transaction *transaction)
This API reads data from the McSPI instance in DMA mode.
MCSPI_enableRxFIFO
static void MCSPI_enableRxFIFO(uint32_t baseAddr, uint32_t chNum, uint32_t enableFlag)
This API will enable/disable the Rx FIFOs of McSPI peripheral.
Definition: mcspi_lld.h:1506
MCSPI_intrStatusClear
static void MCSPI_intrStatusClear(const MCSPI_ChObject *chObj, uint32_t baseAddr, uint32_t intFlags)
Definition: mcspi_lld.h:799
MCSPI_ChConfig::csPolarity
uint32_t csPolarity
Definition: mcspi_lld.h:598
MCSPI_ChConfig::startBitPolarity
uint32_t startBitPolarity
Definition: mcspi_lld.h:614
MCSPI_ChConfig::turboEnable
uint32_t turboEnable
Definition: mcspi_lld.h:617
MCSPI_ExtendedParams::channel
uint32_t channel
Definition: mcspi_lld.h:555
MCSPILLD_Object::transferMutex
void * transferMutex
Definition: mcspi_lld.h:766
MCSPILLD_InitObject::multiWordAccess
uint32_t multiWordAccess
Definition: mcspi_lld.h:735
MCSPI_lld_dmaInit
int32_t MCSPI_lld_dmaInit(MCSPI_DmaHandle mcspiDmaHandle)
API to open an MCSPI DMA channel.
MCSPI_reset
void MCSPI_reset(uint32_t baseAddr)
MCSPI_lld_dmaStop
void MCSPI_lld_dmaStop(MCSPILLD_Handle hMcspi, MCSPI_ChObject *chObj, uint32_t chNum)
API to Stop DMA using a specific DMA driver - UDMA, EDMA etc.
MCSPI_lld_writeIntr
int32_t MCSPI_lld_writeIntr(MCSPILLD_Handle hMcspi, void *txBuf, uint32_t count, uint32_t timeout, const MCSPI_ExtendedParams *extendedParams)
This API writes data to the McSPI instance in Interrupt mode.
MCSPI_ChObject::csDisable
uint32_t csDisable
Definition: mcspi_lld.h:675
MCSPI_Transaction::args
void * args
Definition: mcspi_lld.h:536
MCSPI_ChObject::dataWidthBitMask
uint32_t dataWidthBitMask
Definition: mcspi_lld.h:699
MCSPI_ExtendedParams
Data structure used with MCSPI_lld_read(), MCSPI_lld_readIntr(), MCSPI_lld_readDma(),...
Definition: mcspi_lld.h:554
MCSPI_ExtendedParams::dataSize
uint32_t dataSize
Definition: mcspi_lld.h:564
MCSPI_ChConfig::startBitEnable
uint32_t startBitEnable
Definition: mcspi_lld.h:611
MCSPI_Transaction::txBuf
void * txBuf
Definition: mcspi_lld.h:518
MCSPI_CHCTRL
#define MCSPI_CHCTRL(x)
Base address of McSPI_CHCTRL(x)
Definition: mcspi_lld.h:450
MCSPILLD_InitObject::chMode
uint32_t chMode
Definition: mcspi_lld.h:729
MCSPI_lld_reConfigFifo
int32_t MCSPI_lld_reConfigFifo(MCSPILLD_Handle handle, uint32_t chNum, uint32_t numWordsRxTx)
Function to re-configure Effective FIFO Words.
MCSPI_Transaction::rxBuf
void * rxBuf
Definition: mcspi_lld.h:529
MCSPI_ChObject::systRegVal
uint32_t systRegVal
Definition: mcspi_lld.h:713
MCSPI_ChObject::effRxFifoDepth
uint32_t effRxFifoDepth
Definition: mcspi_lld.h:703
MCSPI_MAX_NUM_CHANNELS
#define MCSPI_MAX_NUM_CHANNELS
Max number of channels/Chip Select (CS) supported.
Definition: mcspi_lld.h:178
MCSPI_Transaction::dataSize
uint32_t dataSize
Definition: mcspi_lld.h:504
MCSPI_lld_write
int32_t MCSPI_lld_write(MCSPILLD_Handle hMcspi, void *txBuf, uint32_t count, uint32_t timeout, const MCSPI_ExtendedParams *extendedParams)
This API writes data to the McSPI instance in Polling mode.
MCSPI_ChObject::curTxWords
uint32_t curTxWords
Definition: mcspi_lld.h:683
MCSPILLD_InitObject::mcspiDmaHandle
MCSPI_DmaHandle mcspiDmaHandle
Definition: mcspi_lld.h:743
MCSPI_ChConfig::slvCsSelect
uint32_t slvCsSelect
Definition: mcspi_lld.h:608
MCSPI_lld_deInit
int32_t MCSPI_lld_deInit(MCSPILLD_Handle hMcspi)
This API De-Initializes the McSPI instance.
MCSPI_readChStatusReg
static uint32_t MCSPI_readChStatusReg(uint32_t baseAddr, uint32_t chNum)
This API will return the status of the McSPI channel currently in use.
Definition: mcspi_lld.h:1459
MCSPI_stop
void MCSPI_stop(MCSPILLD_Handle hMcspi, MCSPI_ChObject *chObj, uint32_t chNum)
MCSPI_ChObject::bufWidthShift
uint8_t bufWidthShift
Definition: mcspi_lld.h:693
MCSPILLD_Object::transaction
MCSPI_Transaction transaction
Definition: mcspi_lld.h:782
MCSPILLD_Handle
struct MCSPILLD_Object * MCSPILLD_Handle
MCSPI_lld_readWriteDma
int32_t MCSPI_lld_readWriteDma(MCSPILLD_Handle hMcspi, void *txBuf, void *rxBuf, uint32_t count, uint32_t timeout, const MCSPI_ExtendedParams *extendedParams)
This API reads writes data from the McSPI instance in DMA mode.
MCSPI_ExtendedParams::csDisable
uint32_t csDisable
Definition: mcspi_lld.h:558
MCSPI_ChObject::curRxBufPtr
uint8_t * curRxBufPtr
Definition: mcspi_lld.h:681
MCSPI_lld_readIntr
int32_t MCSPI_lld_readIntr(MCSPILLD_Handle hMcspi, void *rxBuf, uint32_t count, uint32_t timeout, const MCSPI_ExtendedParams *extendedParams)
This API reads data from the McSPI instance in Interrupt mode.
MCSPI_CS_POL_LOW
#define MCSPI_CS_POL_LOW
SPIEN (CS) is held low during the ACTIVE state.
Definition: mcspi_lld.h:248
MCSPILLD_Object::args
void * args
Definition: mcspi_lld.h:784
MCSPI_lld_readWrite
int32_t MCSPI_lld_readWrite(MCSPILLD_Handle hMcspi, void *txBuf, void *rxBuf, uint32_t count, uint32_t timeout, const MCSPI_ExtendedParams *extendedParams)
This API reads writes data from the McSPI instance in polling mode.
MCSPI_ChConfig::defaultTxData
uint32_t defaultTxData
Definition: mcspi_lld.h:622
MCSPI_ChConfig::dpe1
uint32_t dpe1
Definition: mcspi_lld.h:606
MCSPI_DmaHandle
struct Udma_DrvObjectInt_t * MCSPI_DmaHandle
Definition: mcspi_dma_udma.h:96
MCSPILLD_InitObject::msMode
uint32_t msMode
Definition: mcspi_lld.h:737
MCSPI_ChObject::csEnable
uint32_t csEnable
Definition: mcspi_lld.h:677
MCSPILLD_InitObject::operMode
uint32_t operMode
Definition: mcspi_lld.h:725
MCSPI_writeChCtrlReg
static void MCSPI_writeChCtrlReg(uint32_t baseAddr, uint32_t chNum, uint32_t regVal)
This API sets Channel control register value.
Definition: mcspi_lld.h:1470
MCSPI_ChObject::chCfg
MCSPI_ChConfig * chCfg
Definition: mcspi_lld.h:665
MCSPI_readChConf
static uint32_t MCSPI_readChConf(uint32_t baseAddr, uint32_t chNum)
This API returns Channel Config register value.
Definition: mcspi_lld.h:1476
MCSPI_ChObject::dmaChCfg
MCSPI_DmaChConfig dmaChCfg
Definition: mcspi_lld.h:707
MCSPI_Transaction::channel
uint32_t channel
Definition: mcspi_lld.h:495
MCSPI_lld_readDma
int32_t MCSPI_lld_readDma(MCSPILLD_Handle hMcspi, void *rxBuf, uint32_t count, uint32_t timeout, const MCSPI_ExtendedParams *extendedParams)
This API reads data from the McSPI instance in DMA mode.
MCSPI_lld_transferIntr
int32_t MCSPI_lld_transferIntr(MCSPILLD_Handle hMcspi, MCSPI_Transaction *transaction)
This API reads data from the McSPI instance in Interrupt mode.
MCSPI_ChConfig::inputSelect
uint32_t inputSelect
Definition: mcspi_lld.h:602
MCSPILLD_Object::baseAddr
uint32_t baseAddr
Definition: mcspi_lld.h:758
MCSPI_ChConfig::dpe0
uint32_t dpe0
Definition: mcspi_lld.h:604
MCSPI_setChDataSize
void MCSPI_setChDataSize(uint32_t baseAddr, MCSPI_ChObject *chObj, uint32_t dataSize, uint32_t csDisable)
MCSPI_lld_getState
int32_t MCSPI_lld_getState(MCSPILLD_Handle hMcspi)
This API returns the driver state.
MCSPI_ChConfig
MCSPI configuration parameters for the channel.
Definition: mcspi_lld.h:591
MCSPI_writeChConfReg
static void MCSPI_writeChConfReg(uint32_t baseAddr, uint32_t chNum, uint32_t regVal)
This API sets Channel Config register value.
Definition: mcspi_lld.h:1481
MCSPILLD_InitObject::errorCallbackFxn
MCSPI_errorCallbackFxn errorCallbackFxn
Definition: mcspi_lld.h:749
MCSPILLD_Object::transferCsDisable
uint32_t transferCsDisable
Definition: mcspi_lld.h:778
MCSPILLD_InitObject::initDelay
uint32_t initDelay
Definition: mcspi_lld.h:733
MCSPI_setDataWidth
static void MCSPI_setDataWidth(uint32_t baseAddr, uint32_t chNum, uint32_t dataWidth)
This API will set the data width in the channel config register.
Definition: mcspi_lld.h:1523
MCSPILLD_InitObject::inputClkFreq
uint32_t inputClkFreq
Definition: mcspi_lld.h:721
MCSPI_ChConfig::frameFormat
uint32_t frameFormat
Definition: mcspi_lld.h:594
MCSPI_ChConfig::csIdleTime
uint32_t csIdleTime
Definition: mcspi_lld.h:619
MCSPI_ChConfig::chNum
uint32_t chNum
Definition: mcspi_lld.h:592