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AM64x MCU+ SDK
10.01.00
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Go to the documentation of this file.
81 #define ENETPHY_IS_ADDR_VALID(addr) ((addr) <= 31U)
84 #define ENETPHY_BIT(n) (1U << (n))
87 #define ENETPHY_IS_BIT_SET(val, n) (((val) & ENETPHY_BIT(n)) != 0U)
90 #define ENETPHY_ARRAYSIZE(x) (sizeof(x) / sizeof(x[0]))
104 #define ENETPHY_SOK (CSL_PASS)
107 #define ENETPHY_EFAIL (CSL_EFAIL)
110 #define ENETPHY_EBADARGS (CSL_EBADARGS)
113 #define ENETPHY_EINVALIDPARAMS (CSL_EINVALID_PARAMS)
116 #define ENETPHY_ETIMEOUT (CSL_ETIMEOUT)
119 #define ENETPHY_EALLOC (CSL_EALLOC)
122 #define ENETPHY_EPERM (CSL_EALLOC - 4)
125 #define ENETPHY_ENOTSUPPORTED (CSL_EALLOC - 5)
128 #define ENETPHY_EUNAVAILABLE (CSL_EALLOC - 6)
142 #define ENETPHY_LINK_CAP_HD10 ENETPHY_BIT(1)
145 #define ENETPHY_LINK_CAP_FD10 ENETPHY_BIT(2)
148 #define ENETPHY_LINK_CAP_HD100 ENETPHY_BIT(3)
151 #define ENETPHY_LINK_CAP_FD100 ENETPHY_BIT(4)
154 #define ENETPHY_LINK_CAP_HD1000 ENETPHY_BIT(5)
157 #define ENETPHY_LINK_CAP_FD1000 ENETPHY_BIT(6)
160 #define ENETPHY_LINK_CAP_10 (ENETPHY_LINK_CAP_HD10 | \
161 ENETPHY_LINK_CAP_FD10)
164 #define ENETPHY_LINK_CAP_100 (ENETPHY_LINK_CAP_HD100 | \
165 ENETPHY_LINK_CAP_FD100)
168 #define ENETPHY_LINK_CAP_1000 (ENETPHY_LINK_CAP_HD1000 | \
169 ENETPHY_LINK_CAP_FD1000)
172 #define ENETPHY_LINK_CAP_ALL (ENETPHY_LINK_CAP_HD10 | \
173 ENETPHY_LINK_CAP_FD10 | \
174 ENETPHY_LINK_CAP_HD100 | \
175 ENETPHY_LINK_CAP_FD100 | \
176 ENETPHY_LINK_CAP_HD1000 | \
177 ENETPHY_LINK_CAP_FD1000)
182 #define ENETPHY_EXTENDED_CFG_SIZE_MAX (128U)
185 #define ENETPHY_FSM_TICK_PERIOD_MS (100U)
188 #define ENETPHY_INVALID_PHYADDR (~0U)
191 #define ENETPHY_TIMEOUT_WAIT_FOREVER (0xFFFFFFFFU)
194 #define ENETPHY_TIMEOUT_NO_WAIT (0U)
203 typedef enum EnetPhy_Magic_e
215 typedef enum EnetPhy_Mii_e
239 typedef enum EnetPhy_Speed_e
257 typedef enum EnetPhy_Duplexity_e
272 typedef struct EnetPhy_Version_s
287 typedef enum EnetPhy_LinkStatus_e
305 typedef struct EnetPhy_LinkCfg_s
317 typedef struct EnetPhy_FsmTimeoutCfg_s
359 typedef struct EnetPhy_Cfg_s
407 typedef struct EnetPhy_Mdio_s
421 int32_t (*isAlive)(uint32_t phyAddr,
437 int32_t (*isLinked)(uint32_t phyAddr,
454 int32_t (*readC22)(uint32_t group,
473 int32_t (*writeC22)(uint32_t group,
493 int32_t (*readC45)(uint32_t group,
514 int32_t (*writeC45)(uint32_t group,
530 typedef enum EnetPhy_FsmState_e
569 typedef struct EnetPhy_State_s
620 typedef struct EnetPhy_Obj_s
701 const void *extendedCfg,
702 uint32_t extendedCfgSize);
724 uint32_t macPortCaps,
1019 uint32_t msgType, uint32_t seqId, uint64_t *ts64);
1035 uint32_t msgType, uint32_t seqId, uint64_t *ts64);
1050 uint32_t msgType, uint32_t seqId);
1065 uint32_t
size, uint32_t *types);
1079 uint8_t *ethhdr, uint32_t
size);
1093 uint32_t srcMacStatusFrameType);
1119 bool falling,
bool on);
1136 uint64_t start, uint64_t period,
bool repeat);
1151 uint32_t *seqId, uint64_t *ts64);
bool enableMdix
Definition: enetphy.h:614
@ PHY_MAC_MII_RGMII
RGMII interface.
Definition: phy_common.h:207
EnetPhy_FsmTimeoutCfg timeoutCfg
Definition: enetphy.h:638
int32_t EnetPhy_waitPtpTxTime(EnetPhy_Handle hPhy, uint32_t domain, uint32_t msgType, uint32_t seqId)
Add PHY PTP TX packet info to a waiting TX timestamp list.
void * priv
Definition: enetphy.h:662
int32_t EnetPhy_adjPtpFreq(EnetPhy_Handle hPhy, int64_t ppb)
Adjust PHY PTP clock frequency.
void EnetPhy_setExtendedCfg(EnetPhy_Cfg *phyCfg, const void *extendedCfg, uint32_t extendedCfgSize)
Set PHY extended parameters.
int32_t EnetPhy_enableEventCapture(EnetPhy_Handle hPhy, uint32_t eventIdx, bool falling, bool on)
Enable/Disable an event capture on a PHY GPIO pin.
int32_t EnetPhy_writeExtReg(void *pArgs, uint32_t reg, uint16_t val)
Write PHY extended register.
int32_t EnetPhy_getEventTs(EnetPhy_Handle hPhy, uint32_t *eventIdx, uint32_t *seqId, uint64_t *ts64)
Get event timestamp.
int32_t EnetPhy_getPtpTime(EnetPhy_Handle hPhy, uint64_t *ts64)
Get current PHY PTP clock time.
uint16_t size
Definition: tisci_boardcfg.h:1
int32_t EnetPhy_readExtReg(void *pArgs, uint32_t reg, uint16_t *val)
Read PHY extended register.
uint32_t nwayStartStateTicks
NWAY_START state timeout (in ticks).
Definition: enetphy.h:338
int32_t EnetPhy_enablePtp(EnetPhy_Handle hPhy, bool on, uint32_t srcMacStatusFrameType)
Enable/Disable PHY PTP module.
uint32_t findingStateTicks
FINDING state timeout (in ticks).
Definition: enetphy.h:323
bool extClkSource
Definition: enetphy.h:388
bool loopbackEn
Definition: enetphy.h:382
EnetPhy_MdioHandle hMdio
Definition: enetphy.h:623
bool isIsolateStateReq
Definition: enetphy.h:379
uint32_t addr
Definition: enetphy.h:647
int32_t EnetPhy_rmwC45Reg(EnetPhy_Handle hPhy, uint8_t mmd, uint32_t reg, uint16_t mask, uint16_t val)
Read-modify-write PHY register using Clause-45 frame.
EnetPhy_FsmTimeoutCfg timeoutCfg
Definition: enetphy.h:394
@ ENETPHY_SPEED_10MBIT
Definition: enetphy.h:242
uint32_t residenceTime
Definition: enetphy.h:587
int32_t EnetPhy_procStatusFrame(EnetPhy_Handle hPhy, uint8_t *frame, uint32_t size, uint32_t *types)
Process PHY status frame.
@ ENETPHY_FSM_STATE_FOUND
FOUND state.
Definition: enetphy.h:545
uint32_t phyAddr
Definition: enetphy.h:365
@ ENETPHY_FSM_STATE_NWAY_WAIT
NWAY_WAIT state (auto-negotiation path)
Definition: enetphy.h:551
EnetPhy_Speed speed
Definition: enetphy.h:578
int32_t EnetPhy_getLinkCfg(EnetPhy_Handle hPhy, EnetPhy_LinkCfg *linkCfg)
Get link configuration.
int32_t EnetPhy_readC45Reg(EnetPhy_Handle hPhy, uint8_t mmd, uint32_t reg, uint16_t *val)
Read PHY register using Clause-45 frame.
int32_t EnetPhy_rmwExtReg(EnetPhy_Handle hPhy, uint32_t reg, uint16_t mask, uint16_t val)
Read-modify-write PHY extended register.
int32_t EnetPhy_writeReg(void *pArgs, uint32_t reg, uint16_t val)
Write PHY register.
void EnetPhy_printRegs(EnetPhy_Handle hPhy)
Print all PHY registers.
@ ENETPHY_FSM_STATE_LINK_WAIT
LINK_WAIT state.
Definition: enetphy.h:554
EnetPhy_Mii
MAC Media-Independent Interface (MII).
Definition: enetphy.h:216
Definition: phy_common.h:239
@ ENETPHY_MAGIC
Definition: enetphy.h:206
@ ENETPHY_LINK_DOWN
Definition: enetphy.h:299
@ ENETPHY_FSM_STATE_ENABLE
ENABLE state.
Definition: enetphy.h:542
uint32_t linkCaps
Definition: enetphy.h:602
int32_t EnetPhy_getPtpRxTime(EnetPhy_Handle hPhy, uint32_t domain, uint32_t msgType, uint32_t seqId, uint64_t *ts64)
Get PHY PTP RX packet timestamp.
@ ENETPHY_MAC_MII_RMII
RMII interface.
Definition: enetphy.h:221
@ ENETPHY_MAC_MII_GMII
GMII interface.
Definition: enetphy.h:224
bool skipExtendedCfg
Definition: enetphy.h:391
int32_t EnetPhy_getPtpTxTime(EnetPhy_Handle hPhy, uint32_t domain, uint32_t msgType, uint32_t seqId, uint64_t *ts64)
Get PHY PTP TX packet timestamp.
@ ENETPHY_SPEED_AUTO
Definition: enetphy.h:251
@ PHY_MAC_MII_GMII
GMII interface.
Definition: phy_common.h:204
@ PHY_MAC_MII_QSGMII
QSGMII interface.
Definition: phy_common.h:213
uint32_t revision
Definition: enetphy.h:281
EnetPhy_Duplexity duplexity
Definition: enetphy.h:311
bool needsManualCfg
Definition: enetphy.h:596
int32_t EnetPhy_tickDriver(EnetPhy_Handle hPhy)
Provide timer tick to the driver.
PHY configuration parameters.
Definition: enetphy.h:360
EnetPhy_FsmState
PHY driver state-machine states.
Definition: enetphy.h:531
int32_t EnetPhy_getId(EnetPhy_Handle hPhy, EnetPhy_Version *version)
Get PHY id.
@ ENETPHY_MAC_MII_MII
MII interface.
Definition: enetphy.h:218
bool EnetPhy_isAlive(EnetPhy_Handle hPhy)
Get PHY alive status.
uint32_t mdixTicks
Timeout if MDIX is enabled (in ticks).
Definition: enetphy.h:353
@ ENETPHY_DUPLEX_HALF
Definition: enetphy.h:260
bool needsMdixSwitch
Definition: enetphy.h:611
@ PHY_MAC_MII_SGMII
SGMII interface.
Definition: phy_common.h:210
PHY version (ID).
Definition: enetphy.h:273
uint32_t resetWaitStateTicks
RESET_WAIT state timeout (in ticks).
Definition: enetphy.h:329
@ ENETPHY_DUPLEX_FULL
Definition: enetphy.h:263
EnetPhy_State state
Definition: enetphy.h:641
void EnetPhy_close(EnetPhy_Handle hPhy)
Close the PHY driver.
EnetPhy_LinkCfg linkCfg
Definition: enetphy.h:635
@ ENETPHY_SPEED_1GBIT
Definition: enetphy.h:248
EnetPhy_Mdio * EnetPhy_MdioHandle
MDIO driver handle.
Definition: enetphy.h:525
@ ENETPHY_FSM_STATE_LOOPBACK
LOOPBACK state.
Definition: enetphy.h:560
EnetPhy_Handle EnetPhy_open(const EnetPhy_Cfg *phyCfg, EnetPhy_Mii mii, const EnetPhy_LinkCfg *linkCfg, uint32_t macPortCaps, EnetPhy_MdioHandle hMdio, void *mdioArgs)
Open the PHY driver.
EnetPhy_Speed speed
Definition: enetphy.h:308
PHY State-Machine time-out values.
Definition: enetphy.h:318
struct EnetPhy_Obj_s * EnetPhy_Handle
PHY driver object handle.
Definition: enetphy.h:670
bool EnetPhy_isLinked(EnetPhy_Handle hPhy)
Get link status.
@ ENETPHY_LOST_LINK
Definition: enetphy.h:296
int32_t EnetPhy_writeC45Reg(EnetPhy_Handle hPhy, uint8_t mmd, uint32_t reg, uint16_t val)
Write PHY register using Clause-45 frame.
@ ENETPHY_NO_MAGIC
Definition: enetphy.h:209
@ ENETPHY_GOT_LINK
Definition: enetphy.h:290
EnetPhy_Magic magic
Definition: enetphy.h:656
void * mdioArgs
Definition: enetphy.h:659
uint32_t model
Definition: enetphy.h:278
@ ENETPHY_FSM_STATE_NWAY_START
NWAY_START state (auto-negotiation path)
Definition: enetphy.h:548
@ ENETPHY_DUPLEX_AUTO
Definition: enetphy.h:266
EnetPhy_Mii mii
Definition: enetphy.h:629
@ ENETPHY_LINK_UP
Definition: enetphy.h:293
PHY driver FSM state.
Definition: enetphy.h:570
uint32_t nwayWaitStateTicks
NWAY_WAIT state timeout (in ticks).
Definition: enetphy.h:344
uint32_t resetWaitStateResidenceTicks
RESET_WAIT state residence time (in ticks).
Definition: enetphy.h:332
@ ENETPHY_SPEED_100MBIT
Definition: enetphy.h:245
@ ENETPHY_FSM_STATE_FINDING
FINDING state.
Definition: enetphy.h:536
@ ENETPHY_MAC_MII_SGMII
SGMII interface.
Definition: enetphy.h:230
bool mdixEn
Definition: enetphy.h:371
int32_t EnetPhy_getStatusFrameEthHeader(EnetPhy_Handle hPhy, uint8_t *ethhdr, uint32_t size)
Get PHY status frame header.
uint32_t extendedCfgSize
Definition: enetphy.h:400
bool masterMode
Definition: enetphy.h:385
@ ENETPHY_FSM_STATE_INIT
INIT state.
Definition: enetphy.h:533
bool isNwayCapable
Definition: enetphy.h:590
#define ENETPHY_EXTENDED_CFG_SIZE_MAX
Max extended configuration size, arbitrarily chosen.
Definition: enetphy.h:182
bool needsNwayCfg
Definition: enetphy.h:599
@ ENETPHY_MAC_MII_QSGMII
QSGMII interface.
Definition: enetphy.h:233
uint32_t oui
Definition: enetphy.h:275
Link speed and duplexity configuration.
Definition: enetphy.h:306
void EnetPhy_initCfg(EnetPhy_Cfg *phyCfg)
Initialize PHY config params.
EnetPhy_FsmState fsmState
Definition: enetphy.h:572
EnetPhy_Duplexity duplexity
Definition: enetphy.h:581
int32_t EnetPhy_rmwReg(void *pArgs, uint32_t reg, uint16_t mask, uint16_t val)
Read-modify-write PHY register.
bool fsmStateChanged
Definition: enetphy.h:575
uint32_t nwayCaps
Definition: enetphy.h:368
uint32_t linkWaitStateTicks
LINK_WAIT state timeout (in ticks).
Definition: enetphy.h:350
int32_t EnetPhy_readReg(void *pArgs, uint32_t reg, uint16_t *val)
Read PHY register.
EnetPhy_Duplexity
MAC interface duplexity.
Definition: enetphy.h:258
int32_t EnetPhy_enableTriggerOutput(EnetPhy_Handle hPhy, uint32_t triggerIdx, uint64_t start, uint64_t period, bool repeat)
Enable/Disable clock trigger on a GPIO pin.
@ ENETPHY_MAC_MII_RGMII
RGMII interface.
Definition: enetphy.h:227
int32_t EnetPhy_setPtpTime(EnetPhy_Handle hPhy, uint64_t ts64)
Set PHY PTP clock time.
bool loopbackEn
Definition: enetphy.h:608
domgrp_t domain
Definition: tisci_pm_core.h:1
bool enableNway
Definition: enetphy.h:593
PHY driver object.
Definition: enetphy.h:621
uint32_t group
Definition: enetphy.h:644
uint32_t macCaps
Definition: enetphy.h:632
uint32_t phyLinkCaps
Definition: enetphy.h:605
uint32_t reqLinkCaps
Definition: enetphy.h:650
uint32_t phyGroup
Definition: enetphy.h:362
EnetPhy_LinkStatus EnetPhy_tick(EnetPhy_Handle hPhy)
Run PHY state machine.
EnetPhy_Speed
MAC interface speed.
Definition: enetphy.h:240
bool isStrapped
Definition: enetphy.h:376
@ ENETPHY_FSM_STATE_ISOLATE
ISOLATE state.
Definition: enetphy.h:563
MDIO driver.
Definition: enetphy.h:408
@ ENETPHY_FSM_STATE_RESET_WAIT
RESET_WAIT state.
Definition: enetphy.h:539
@ PHY_MAC_MII_MII
MII interface.
Definition: phy_common.h:198
Phy_DrvObj_t hDrvIf
Definition: enetphy.h:653
EnetPhy_Cfg phyCfg
Definition: enetphy.h:626
@ ENETPHY_FSM_STATE_LINKED
LINKED state.
Definition: enetphy.h:557
EnetPhy_Magic
EnetPhy driver magic value, used to indicate if driver is open or not.
Definition: enetphy.h:204
uint16_t version
Definition: tisci_core.h:2
uint32_t timeout
Definition: enetphy.h:584
int32_t EnetPhy_adjPtpPhase(EnetPhy_Handle hPhy, int64_t offset)
Adjust PHY PTP clock phase.
@ PHY_MAC_MII_RMII
RMII interface.
Definition: phy_common.h:201
EnetPhy_LinkStatus
PHY link status.
Definition: enetphy.h:288