AM64x MCU+ SDK  10.01.00
enetphy.h
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1 /*
2  * Copyright (c) Texas Instruments Incorporated 2020
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
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9  * notice, this list of conditions and the following disclaimer.
10  *
11  * Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the
14  * distribution.
15  *
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17  * its contributors may be used to endorse or promote products derived
18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
61 #ifndef ENETPHY_H_
62 #define ENETPHY_H_
63 
64 /* ========================================================================== */
65 /* Include Files */
66 /* ========================================================================== */
67 
68 #include <stdint.h>
69 #include <stdbool.h>
70 #include "phy_common.h"
71 
72 #ifdef __cplusplus
73 extern "C" {
74 #endif
75 
76 /* ========================================================================== */
77 /* Macros */
78 /* ========================================================================== */
79 
81 #define ENETPHY_IS_ADDR_VALID(addr) ((addr) <= 31U)
82 
84 #define ENETPHY_BIT(n) (1U << (n))
85 
87 #define ENETPHY_IS_BIT_SET(val, n) (((val) & ENETPHY_BIT(n)) != 0U)
88 
90 #define ENETPHY_ARRAYSIZE(x) (sizeof(x) / sizeof(x[0]))
91 
101 /* Ethernet PHY driver error codes are same as CSL's to maintain consistency */
102 
104 #define ENETPHY_SOK (CSL_PASS)
105 
107 #define ENETPHY_EFAIL (CSL_EFAIL)
108 
110 #define ENETPHY_EBADARGS (CSL_EBADARGS)
111 
113 #define ENETPHY_EINVALIDPARAMS (CSL_EINVALID_PARAMS)
114 
116 #define ENETPHY_ETIMEOUT (CSL_ETIMEOUT)
117 
119 #define ENETPHY_EALLOC (CSL_EALLOC)
120 
122 #define ENETPHY_EPERM (CSL_EALLOC - 4)
123 
125 #define ENETPHY_ENOTSUPPORTED (CSL_EALLOC - 5)
126 
128 #define ENETPHY_EUNAVAILABLE (CSL_EALLOC - 6)
129 
142 #define ENETPHY_LINK_CAP_HD10 ENETPHY_BIT(1)
143 
145 #define ENETPHY_LINK_CAP_FD10 ENETPHY_BIT(2)
146 
148 #define ENETPHY_LINK_CAP_HD100 ENETPHY_BIT(3)
149 
151 #define ENETPHY_LINK_CAP_FD100 ENETPHY_BIT(4)
152 
154 #define ENETPHY_LINK_CAP_HD1000 ENETPHY_BIT(5)
155 
157 #define ENETPHY_LINK_CAP_FD1000 ENETPHY_BIT(6)
158 
160 #define ENETPHY_LINK_CAP_10 (ENETPHY_LINK_CAP_HD10 | \
161  ENETPHY_LINK_CAP_FD10)
162 
164 #define ENETPHY_LINK_CAP_100 (ENETPHY_LINK_CAP_HD100 | \
165  ENETPHY_LINK_CAP_FD100)
166 
168 #define ENETPHY_LINK_CAP_1000 (ENETPHY_LINK_CAP_HD1000 | \
169  ENETPHY_LINK_CAP_FD1000)
170 
172 #define ENETPHY_LINK_CAP_ALL (ENETPHY_LINK_CAP_HD10 | \
173  ENETPHY_LINK_CAP_FD10 | \
174  ENETPHY_LINK_CAP_HD100 | \
175  ENETPHY_LINK_CAP_FD100 | \
176  ENETPHY_LINK_CAP_HD1000 | \
177  ENETPHY_LINK_CAP_FD1000)
178 
182 #define ENETPHY_EXTENDED_CFG_SIZE_MAX (128U)
183 
185 #define ENETPHY_FSM_TICK_PERIOD_MS (100U)
186 
188 #define ENETPHY_INVALID_PHYADDR (~0U)
189 
191 #define ENETPHY_TIMEOUT_WAIT_FOREVER (0xFFFFFFFFU)
192 
194 #define ENETPHY_TIMEOUT_NO_WAIT (0U)
195 
196 /* ========================================================================== */
197 /* Structures and Enums */
198 /* ========================================================================== */
199 
203 typedef enum EnetPhy_Magic_e
204 {
206  ENETPHY_MAGIC = 0xCADACADAU,
207 
210 } EnetPhy_Magic;
211 
215 typedef enum EnetPhy_Mii_e
216 {
219 
222 
225 
228 
231 
234 } EnetPhy_Mii;
235 
239 typedef enum EnetPhy_Speed_e
240 {
243 
246 
249 
252 } EnetPhy_Speed;
253 
257 typedef enum EnetPhy_Duplexity_e
258 {
261 
264 
268 
272 typedef struct EnetPhy_Version_s
273 {
275  uint32_t oui;
276 
278  uint32_t model;
279 
281  uint32_t revision;
283 
287 typedef enum EnetPhy_LinkStatus_e
288 {
291 
294 
297 
301 
305 typedef struct EnetPhy_LinkCfg_s
306 {
309 
313 
317 typedef struct EnetPhy_FsmTimeoutCfg_s
318 {
324 
330 
333 
339 
345 
351 
353  uint32_t mdixTicks;
355 
359 typedef struct EnetPhy_Cfg_s
360 {
362  uint32_t phyGroup;
363 
365  uint32_t phyAddr;
366 
368  uint32_t nwayCaps;
369 
371  bool mdixEn;
372 
377 
380 
383 
386 
389 
392 
395 
397  uint8_t extendedCfg[ENETPHY_EXTENDED_CFG_SIZE_MAX];
398 
400  uint32_t extendedCfgSize;
401 
402 } EnetPhy_Cfg;
403 
407 typedef struct EnetPhy_Mdio_s
408 {
421  int32_t (*isAlive)(uint32_t phyAddr,
422  bool *isAlive,
423  void *arg);
424 
437  int32_t (*isLinked)(uint32_t phyAddr,
438  bool *isLinked,
439  void *arg);
440 
454  int32_t (*readC22)(uint32_t group,
455  uint32_t phyAddr,
456  uint32_t reg,
457  uint16_t *val,
458  void *arg);
459 
473  int32_t (*writeC22)(uint32_t group,
474  uint32_t phyAddr,
475  uint32_t reg,
476  uint16_t val,
477  void *arg);
478 
493  int32_t (*readC45)(uint32_t group,
494  uint32_t phyAddr,
495  uint8_t mmd,
496  uint16_t reg,
497  uint16_t *val,
498  void *arg);
499 
514  int32_t (*writeC45)(uint32_t group,
515  uint32_t phyAddr,
516  uint8_t mmd,
517  uint16_t reg,
518  uint16_t val,
519  void *arg);
520 } EnetPhy_Mdio;
521 
526 
530 typedef enum EnetPhy_FsmState_e
531 {
534 
537 
540 
543 
546 
549 
552 
555 
558 
561 
565 
569 typedef struct EnetPhy_State_s
570 {
573 
576 
579 
582 
584  uint32_t timeout;
585 
587  uint32_t residenceTime;
588 
591 
594 
597 
600 
602  uint32_t linkCaps;
603 
605  uint32_t phyLinkCaps;
606 
609 
612 
615 } EnetPhy_State;
616 
620 typedef struct EnetPhy_Obj_s
621 {
624 
627 
630 
632  uint32_t macCaps;
633 
636 
639 
642 
644  uint32_t group;
645 
647  uint32_t addr;
648 
650  uint32_t reqLinkCaps;
651 
654 
657 
659  void *mdioArgs;
660 
662  void *priv;
663 } EnetPhy_Obj;
664 
670 typedef struct EnetPhy_Obj_s *EnetPhy_Handle;
671 
672 /* ========================================================================== */
673 /* Global Variables Declarations */
674 /* ========================================================================== */
675 
676 /* None */
677 
678 /* ========================================================================== */
679 /* Function Declarations */
680 /* ========================================================================== */
681 
690 
701  const void *extendedCfg,
702  uint32_t extendedCfgSize);
703 
722  EnetPhy_Mii mii,
723  const EnetPhy_LinkCfg *linkCfg,
724  uint32_t macPortCaps,
725  EnetPhy_MdioHandle hMdio,
726  void *mdioArgs);
727 
736 
747 
760 
771 
785 
799  EnetPhy_LinkCfg *linkCfg);
800 
812 int32_t EnetPhy_readReg(void *pArgs,
813  uint32_t reg,
814  uint16_t *val);
815 
827 int32_t EnetPhy_writeReg(void *pArgs,
828  uint32_t reg,
829  uint16_t val);
830 
843 int32_t EnetPhy_rmwReg(void *pArgs,
844  uint32_t reg,
845  uint16_t mask,
846  uint16_t val);
847 
859 int32_t EnetPhy_readExtReg(void *pArgs,
860  uint32_t reg,
861  uint16_t *val);
862 
874 int32_t EnetPhy_writeExtReg(void *pArgs,
875  uint32_t reg,
876  uint16_t val);
877 
891  uint32_t reg,
892  uint16_t mask,
893  uint16_t val);
894 
908  uint8_t mmd,
909  uint32_t reg,
910  uint16_t *val);
911 
925  uint8_t mmd,
926  uint32_t reg,
927  uint16_t val);
928 
943  uint8_t mmd,
944  uint32_t reg,
945  uint16_t mask,
946  uint16_t val);
947 
956 
967 int32_t EnetPhy_adjPtpFreq(EnetPhy_Handle hPhy, int64_t ppb);
968 
979 int32_t EnetPhy_adjPtpPhase(EnetPhy_Handle hPhy, int64_t offset);
980 
991 int32_t EnetPhy_getPtpTime(EnetPhy_Handle hPhy, uint64_t *ts64);
992 
1003 int32_t EnetPhy_setPtpTime(EnetPhy_Handle hPhy, uint64_t ts64);
1004 
1019  uint32_t msgType, uint32_t seqId, uint64_t *ts64);
1020 
1035  uint32_t msgType, uint32_t seqId, uint64_t *ts64);
1036 
1050  uint32_t msgType, uint32_t seqId);
1051 
1064 int32_t EnetPhy_procStatusFrame(EnetPhy_Handle hPhy, uint8_t *frame,
1065  uint32_t size, uint32_t *types);
1066 
1079  uint8_t *ethhdr, uint32_t size);
1080 
1092 int32_t EnetPhy_enablePtp(EnetPhy_Handle hPhy, bool on,
1093  uint32_t srcMacStatusFrameType);
1094 
1105 
1118 int32_t EnetPhy_enableEventCapture(EnetPhy_Handle hPhy, uint32_t eventIdx,
1119  bool falling, bool on);
1120 
1135 int32_t EnetPhy_enableTriggerOutput(EnetPhy_Handle hPhy, uint32_t triggerIdx,
1136  uint64_t start, uint64_t period, bool repeat);
1137 
1150 int32_t EnetPhy_getEventTs(EnetPhy_Handle hPhy, uint32_t *eventIdx,
1151  uint32_t *seqId, uint64_t *ts64);
1152 /* ========================================================================== */
1153 /* Deprecated Function Declarations */
1154 /* ========================================================================== */
1155 
1156 /* None */
1157 
1158 /* ========================================================================== */
1159 /* Static Function Definitions */
1160 /* ========================================================================== */
1161 
1162 /* None */
1163 
1164 #ifdef __cplusplus
1165 }
1166 #endif
1167 
1168 #endif /* ENETPHY_H_ */
1169 
EnetPhy_State::enableMdix
bool enableMdix
Definition: enetphy.h:614
PHY_MAC_MII_RGMII
@ PHY_MAC_MII_RGMII
RGMII interface.
Definition: phy_common.h:207
EnetPhy_Obj::timeoutCfg
EnetPhy_FsmTimeoutCfg timeoutCfg
Definition: enetphy.h:638
EnetPhy_waitPtpTxTime
int32_t EnetPhy_waitPtpTxTime(EnetPhy_Handle hPhy, uint32_t domain, uint32_t msgType, uint32_t seqId)
Add PHY PTP TX packet info to a waiting TX timestamp list.
EnetPhy_Obj::priv
void * priv
Definition: enetphy.h:662
EnetPhy_adjPtpFreq
int32_t EnetPhy_adjPtpFreq(EnetPhy_Handle hPhy, int64_t ppb)
Adjust PHY PTP clock frequency.
EnetPhy_setExtendedCfg
void EnetPhy_setExtendedCfg(EnetPhy_Cfg *phyCfg, const void *extendedCfg, uint32_t extendedCfgSize)
Set PHY extended parameters.
EnetPhy_enableEventCapture
int32_t EnetPhy_enableEventCapture(EnetPhy_Handle hPhy, uint32_t eventIdx, bool falling, bool on)
Enable/Disable an event capture on a PHY GPIO pin.
EnetPhy_writeExtReg
int32_t EnetPhy_writeExtReg(void *pArgs, uint32_t reg, uint16_t val)
Write PHY extended register.
EnetPhy_getEventTs
int32_t EnetPhy_getEventTs(EnetPhy_Handle hPhy, uint32_t *eventIdx, uint32_t *seqId, uint64_t *ts64)
Get event timestamp.
EnetPhy_getPtpTime
int32_t EnetPhy_getPtpTime(EnetPhy_Handle hPhy, uint64_t *ts64)
Get current PHY PTP clock time.
size
uint16_t size
Definition: tisci_boardcfg.h:1
EnetPhy_readExtReg
int32_t EnetPhy_readExtReg(void *pArgs, uint32_t reg, uint16_t *val)
Read PHY extended register.
EnetPhy_FsmTimeoutCfg::nwayStartStateTicks
uint32_t nwayStartStateTicks
NWAY_START state timeout (in ticks).
Definition: enetphy.h:338
EnetPhy_enablePtp
int32_t EnetPhy_enablePtp(EnetPhy_Handle hPhy, bool on, uint32_t srcMacStatusFrameType)
Enable/Disable PHY PTP module.
EnetPhy_FsmTimeoutCfg::findingStateTicks
uint32_t findingStateTicks
FINDING state timeout (in ticks).
Definition: enetphy.h:323
EnetPhy_Cfg::extClkSource
bool extClkSource
Definition: enetphy.h:388
EnetPhy_Cfg::loopbackEn
bool loopbackEn
Definition: enetphy.h:382
EnetPhy_Obj::hMdio
EnetPhy_MdioHandle hMdio
Definition: enetphy.h:623
EnetPhy_Cfg::isIsolateStateReq
bool isIsolateStateReq
Definition: enetphy.h:379
EnetPhy_Obj::addr
uint32_t addr
Definition: enetphy.h:647
EnetPhy_rmwC45Reg
int32_t EnetPhy_rmwC45Reg(EnetPhy_Handle hPhy, uint8_t mmd, uint32_t reg, uint16_t mask, uint16_t val)
Read-modify-write PHY register using Clause-45 frame.
EnetPhy_Cfg::timeoutCfg
EnetPhy_FsmTimeoutCfg timeoutCfg
Definition: enetphy.h:394
ENETPHY_SPEED_10MBIT
@ ENETPHY_SPEED_10MBIT
Definition: enetphy.h:242
EnetPhy_State::residenceTime
uint32_t residenceTime
Definition: enetphy.h:587
EnetPhy_procStatusFrame
int32_t EnetPhy_procStatusFrame(EnetPhy_Handle hPhy, uint8_t *frame, uint32_t size, uint32_t *types)
Process PHY status frame.
ENETPHY_FSM_STATE_FOUND
@ ENETPHY_FSM_STATE_FOUND
FOUND state.
Definition: enetphy.h:545
EnetPhy_Cfg::phyAddr
uint32_t phyAddr
Definition: enetphy.h:365
ENETPHY_FSM_STATE_NWAY_WAIT
@ ENETPHY_FSM_STATE_NWAY_WAIT
NWAY_WAIT state (auto-negotiation path)
Definition: enetphy.h:551
EnetPhy_State::speed
EnetPhy_Speed speed
Definition: enetphy.h:578
EnetPhy_getLinkCfg
int32_t EnetPhy_getLinkCfg(EnetPhy_Handle hPhy, EnetPhy_LinkCfg *linkCfg)
Get link configuration.
EnetPhy_readC45Reg
int32_t EnetPhy_readC45Reg(EnetPhy_Handle hPhy, uint8_t mmd, uint32_t reg, uint16_t *val)
Read PHY register using Clause-45 frame.
EnetPhy_rmwExtReg
int32_t EnetPhy_rmwExtReg(EnetPhy_Handle hPhy, uint32_t reg, uint16_t mask, uint16_t val)
Read-modify-write PHY extended register.
EnetPhy_writeReg
int32_t EnetPhy_writeReg(void *pArgs, uint32_t reg, uint16_t val)
Write PHY register.
EnetPhy_printRegs
void EnetPhy_printRegs(EnetPhy_Handle hPhy)
Print all PHY registers.
ENETPHY_FSM_STATE_LINK_WAIT
@ ENETPHY_FSM_STATE_LINK_WAIT
LINK_WAIT state.
Definition: enetphy.h:554
EnetPhy_Mii
EnetPhy_Mii
MAC Media-Independent Interface (MII).
Definition: enetphy.h:216
Phy_DrvObj_t
Definition: phy_common.h:239
ENETPHY_MAGIC
@ ENETPHY_MAGIC
Definition: enetphy.h:206
ENETPHY_LINK_DOWN
@ ENETPHY_LINK_DOWN
Definition: enetphy.h:299
ENETPHY_FSM_STATE_ENABLE
@ ENETPHY_FSM_STATE_ENABLE
ENABLE state.
Definition: enetphy.h:542
EnetPhy_State::linkCaps
uint32_t linkCaps
Definition: enetphy.h:602
EnetPhy_getPtpRxTime
int32_t EnetPhy_getPtpRxTime(EnetPhy_Handle hPhy, uint32_t domain, uint32_t msgType, uint32_t seqId, uint64_t *ts64)
Get PHY PTP RX packet timestamp.
ENETPHY_MAC_MII_RMII
@ ENETPHY_MAC_MII_RMII
RMII interface.
Definition: enetphy.h:221
ENETPHY_MAC_MII_GMII
@ ENETPHY_MAC_MII_GMII
GMII interface.
Definition: enetphy.h:224
EnetPhy_Cfg::skipExtendedCfg
bool skipExtendedCfg
Definition: enetphy.h:391
EnetPhy_getPtpTxTime
int32_t EnetPhy_getPtpTxTime(EnetPhy_Handle hPhy, uint32_t domain, uint32_t msgType, uint32_t seqId, uint64_t *ts64)
Get PHY PTP TX packet timestamp.
ENETPHY_SPEED_AUTO
@ ENETPHY_SPEED_AUTO
Definition: enetphy.h:251
PHY_MAC_MII_GMII
@ PHY_MAC_MII_GMII
GMII interface.
Definition: phy_common.h:204
PHY_MAC_MII_QSGMII
@ PHY_MAC_MII_QSGMII
QSGMII interface.
Definition: phy_common.h:213
EnetPhy_Version::revision
uint32_t revision
Definition: enetphy.h:281
EnetPhy_LinkCfg::duplexity
EnetPhy_Duplexity duplexity
Definition: enetphy.h:311
EnetPhy_State::needsManualCfg
bool needsManualCfg
Definition: enetphy.h:596
EnetPhy_tickDriver
int32_t EnetPhy_tickDriver(EnetPhy_Handle hPhy)
Provide timer tick to the driver.
EnetPhy_Cfg
PHY configuration parameters.
Definition: enetphy.h:360
EnetPhy_FsmState
EnetPhy_FsmState
PHY driver state-machine states.
Definition: enetphy.h:531
EnetPhy_getId
int32_t EnetPhy_getId(EnetPhy_Handle hPhy, EnetPhy_Version *version)
Get PHY id.
ENETPHY_MAC_MII_MII
@ ENETPHY_MAC_MII_MII
MII interface.
Definition: enetphy.h:218
EnetPhy_isAlive
bool EnetPhy_isAlive(EnetPhy_Handle hPhy)
Get PHY alive status.
EnetPhy_FsmTimeoutCfg::mdixTicks
uint32_t mdixTicks
Timeout if MDIX is enabled (in ticks).
Definition: enetphy.h:353
ENETPHY_DUPLEX_HALF
@ ENETPHY_DUPLEX_HALF
Definition: enetphy.h:260
EnetPhy_State::needsMdixSwitch
bool needsMdixSwitch
Definition: enetphy.h:611
PHY_MAC_MII_SGMII
@ PHY_MAC_MII_SGMII
SGMII interface.
Definition: phy_common.h:210
EnetPhy_Version
PHY version (ID).
Definition: enetphy.h:273
EnetPhy_FsmTimeoutCfg::resetWaitStateTicks
uint32_t resetWaitStateTicks
RESET_WAIT state timeout (in ticks).
Definition: enetphy.h:329
ENETPHY_DUPLEX_FULL
@ ENETPHY_DUPLEX_FULL
Definition: enetphy.h:263
EnetPhy_Obj::state
EnetPhy_State state
Definition: enetphy.h:641
EnetPhy_close
void EnetPhy_close(EnetPhy_Handle hPhy)
Close the PHY driver.
EnetPhy_Obj::linkCfg
EnetPhy_LinkCfg linkCfg
Definition: enetphy.h:635
ENETPHY_SPEED_1GBIT
@ ENETPHY_SPEED_1GBIT
Definition: enetphy.h:248
EnetPhy_MdioHandle
EnetPhy_Mdio * EnetPhy_MdioHandle
MDIO driver handle.
Definition: enetphy.h:525
ENETPHY_FSM_STATE_LOOPBACK
@ ENETPHY_FSM_STATE_LOOPBACK
LOOPBACK state.
Definition: enetphy.h:560
EnetPhy_open
EnetPhy_Handle EnetPhy_open(const EnetPhy_Cfg *phyCfg, EnetPhy_Mii mii, const EnetPhy_LinkCfg *linkCfg, uint32_t macPortCaps, EnetPhy_MdioHandle hMdio, void *mdioArgs)
Open the PHY driver.
EnetPhy_LinkCfg::speed
EnetPhy_Speed speed
Definition: enetphy.h:308
EnetPhy_FsmTimeoutCfg
PHY State-Machine time-out values.
Definition: enetphy.h:318
EnetPhy_Handle
struct EnetPhy_Obj_s * EnetPhy_Handle
PHY driver object handle.
Definition: enetphy.h:670
EnetPhy_isLinked
bool EnetPhy_isLinked(EnetPhy_Handle hPhy)
Get link status.
ENETPHY_LOST_LINK
@ ENETPHY_LOST_LINK
Definition: enetphy.h:296
EnetPhy_writeC45Reg
int32_t EnetPhy_writeC45Reg(EnetPhy_Handle hPhy, uint8_t mmd, uint32_t reg, uint16_t val)
Write PHY register using Clause-45 frame.
ENETPHY_NO_MAGIC
@ ENETPHY_NO_MAGIC
Definition: enetphy.h:209
ENETPHY_GOT_LINK
@ ENETPHY_GOT_LINK
Definition: enetphy.h:290
EnetPhy_Obj::magic
EnetPhy_Magic magic
Definition: enetphy.h:656
EnetPhy_Obj::mdioArgs
void * mdioArgs
Definition: enetphy.h:659
EnetPhy_Version::model
uint32_t model
Definition: enetphy.h:278
ENETPHY_FSM_STATE_NWAY_START
@ ENETPHY_FSM_STATE_NWAY_START
NWAY_START state (auto-negotiation path)
Definition: enetphy.h:548
ENETPHY_DUPLEX_AUTO
@ ENETPHY_DUPLEX_AUTO
Definition: enetphy.h:266
EnetPhy_Obj::mii
EnetPhy_Mii mii
Definition: enetphy.h:629
ENETPHY_LINK_UP
@ ENETPHY_LINK_UP
Definition: enetphy.h:293
EnetPhy_State
PHY driver FSM state.
Definition: enetphy.h:570
EnetPhy_FsmTimeoutCfg::nwayWaitStateTicks
uint32_t nwayWaitStateTicks
NWAY_WAIT state timeout (in ticks).
Definition: enetphy.h:344
EnetPhy_FsmTimeoutCfg::resetWaitStateResidenceTicks
uint32_t resetWaitStateResidenceTicks
RESET_WAIT state residence time (in ticks).
Definition: enetphy.h:332
ENETPHY_SPEED_100MBIT
@ ENETPHY_SPEED_100MBIT
Definition: enetphy.h:245
ENETPHY_FSM_STATE_FINDING
@ ENETPHY_FSM_STATE_FINDING
FINDING state.
Definition: enetphy.h:536
ENETPHY_MAC_MII_SGMII
@ ENETPHY_MAC_MII_SGMII
SGMII interface.
Definition: enetphy.h:230
phy_common.h
EnetPhy_Cfg::mdixEn
bool mdixEn
Definition: enetphy.h:371
EnetPhy_getStatusFrameEthHeader
int32_t EnetPhy_getStatusFrameEthHeader(EnetPhy_Handle hPhy, uint8_t *ethhdr, uint32_t size)
Get PHY status frame header.
EnetPhy_Cfg::extendedCfgSize
uint32_t extendedCfgSize
Definition: enetphy.h:400
EnetPhy_Cfg::masterMode
bool masterMode
Definition: enetphy.h:385
ENETPHY_FSM_STATE_INIT
@ ENETPHY_FSM_STATE_INIT
INIT state.
Definition: enetphy.h:533
EnetPhy_State::isNwayCapable
bool isNwayCapable
Definition: enetphy.h:590
ENETPHY_EXTENDED_CFG_SIZE_MAX
#define ENETPHY_EXTENDED_CFG_SIZE_MAX
Max extended configuration size, arbitrarily chosen.
Definition: enetphy.h:182
EnetPhy_State::needsNwayCfg
bool needsNwayCfg
Definition: enetphy.h:599
ENETPHY_MAC_MII_QSGMII
@ ENETPHY_MAC_MII_QSGMII
QSGMII interface.
Definition: enetphy.h:233
EnetPhy_Version::oui
uint32_t oui
Definition: enetphy.h:275
EnetPhy_LinkCfg
Link speed and duplexity configuration.
Definition: enetphy.h:306
EnetPhy_initCfg
void EnetPhy_initCfg(EnetPhy_Cfg *phyCfg)
Initialize PHY config params.
EnetPhy_State::fsmState
EnetPhy_FsmState fsmState
Definition: enetphy.h:572
EnetPhy_State::duplexity
EnetPhy_Duplexity duplexity
Definition: enetphy.h:581
EnetPhy_rmwReg
int32_t EnetPhy_rmwReg(void *pArgs, uint32_t reg, uint16_t mask, uint16_t val)
Read-modify-write PHY register.
EnetPhy_State::fsmStateChanged
bool fsmStateChanged
Definition: enetphy.h:575
EnetPhy_Cfg::nwayCaps
uint32_t nwayCaps
Definition: enetphy.h:368
EnetPhy_FsmTimeoutCfg::linkWaitStateTicks
uint32_t linkWaitStateTicks
LINK_WAIT state timeout (in ticks).
Definition: enetphy.h:350
EnetPhy_readReg
int32_t EnetPhy_readReg(void *pArgs, uint32_t reg, uint16_t *val)
Read PHY register.
EnetPhy_Duplexity
EnetPhy_Duplexity
MAC interface duplexity.
Definition: enetphy.h:258
EnetPhy_enableTriggerOutput
int32_t EnetPhy_enableTriggerOutput(EnetPhy_Handle hPhy, uint32_t triggerIdx, uint64_t start, uint64_t period, bool repeat)
Enable/Disable clock trigger on a GPIO pin.
ENETPHY_MAC_MII_RGMII
@ ENETPHY_MAC_MII_RGMII
RGMII interface.
Definition: enetphy.h:227
EnetPhy_setPtpTime
int32_t EnetPhy_setPtpTime(EnetPhy_Handle hPhy, uint64_t ts64)
Set PHY PTP clock time.
EnetPhy_State::loopbackEn
bool loopbackEn
Definition: enetphy.h:608
domain
domgrp_t domain
Definition: tisci_pm_core.h:1
EnetPhy_State::enableNway
bool enableNway
Definition: enetphy.h:593
EnetPhy_Obj
PHY driver object.
Definition: enetphy.h:621
EnetPhy_Obj::group
uint32_t group
Definition: enetphy.h:644
EnetPhy_Obj::macCaps
uint32_t macCaps
Definition: enetphy.h:632
EnetPhy_State::phyLinkCaps
uint32_t phyLinkCaps
Definition: enetphy.h:605
EnetPhy_Obj::reqLinkCaps
uint32_t reqLinkCaps
Definition: enetphy.h:650
EnetPhy_Cfg::phyGroup
uint32_t phyGroup
Definition: enetphy.h:362
EnetPhy_tick
EnetPhy_LinkStatus EnetPhy_tick(EnetPhy_Handle hPhy)
Run PHY state machine.
EnetPhy_Speed
EnetPhy_Speed
MAC interface speed.
Definition: enetphy.h:240
EnetPhy_Cfg::isStrapped
bool isStrapped
Definition: enetphy.h:376
ENETPHY_FSM_STATE_ISOLATE
@ ENETPHY_FSM_STATE_ISOLATE
ISOLATE state.
Definition: enetphy.h:563
EnetPhy_Mdio
MDIO driver.
Definition: enetphy.h:408
ENETPHY_FSM_STATE_RESET_WAIT
@ ENETPHY_FSM_STATE_RESET_WAIT
RESET_WAIT state.
Definition: enetphy.h:539
PHY_MAC_MII_MII
@ PHY_MAC_MII_MII
MII interface.
Definition: phy_common.h:198
EnetPhy_Obj::hDrvIf
Phy_DrvObj_t hDrvIf
Definition: enetphy.h:653
EnetPhy_Obj::phyCfg
EnetPhy_Cfg phyCfg
Definition: enetphy.h:626
ENETPHY_FSM_STATE_LINKED
@ ENETPHY_FSM_STATE_LINKED
LINKED state.
Definition: enetphy.h:557
EnetPhy_Magic
EnetPhy_Magic
EnetPhy driver magic value, used to indicate if driver is open or not.
Definition: enetphy.h:204
version
uint16_t version
Definition: tisci_core.h:2
EnetPhy_State::timeout
uint32_t timeout
Definition: enetphy.h:584
EnetPhy_adjPtpPhase
int32_t EnetPhy_adjPtpPhase(EnetPhy_Handle hPhy, int64_t offset)
Adjust PHY PTP clock phase.
PHY_MAC_MII_RMII
@ PHY_MAC_MII_RMII
RMII interface.
Definition: phy_common.h:201
EnetPhy_LinkStatus
EnetPhy_LinkStatus
PHY link status.
Definition: enetphy.h:288