AM64x MCU+ SDK  10.00.00
udma_soc.h File Reference

Introduction

UDMA Low Level Driver AM64x SOC specific file.

Go to the source code of this file.

Macros

#define UDMA_NUM_MAPPED_TX_GROUP   (4U)
 Number of Mapped TX Group. More...
 
#define UDMA_NUM_MAPPED_RX_GROUP   (4U)
 Number of Mapped RX Group. More...
 
#define UDMA_RM_NUM_SHARED_RES   (2U)
 Total number of shared resources - Global_Event/IR Intr. More...
 
#define UDMA_RM_SHARED_RES_MAX_INST   (UDMA_NUM_CORE)
 Maximum no.of instances to split a shared resource. This should be max(UDMA_NUM_CORE,UDMA_NUM_INST_ID) More...
 
#define UDMA_PSIL_DEST_THREAD_OFFSET   (0x8000U)
 Destination thread offset. More...
 
UDMA Instance ID specific to SOC

UDMA instance ID - BCDMA/PKTDMA

#define UDMA_INST_ID_BCDMA_0   (UDMA_INST_ID_2)
 BCDMA instance. More...
 
#define UDMA_INST_ID_PKTDMA_0   (UDMA_INST_ID_3)
 PKTDMA instance. More...
 
#define UDMA_INST_ID_START   (UDMA_INST_ID_2)
 Start of UDMA instance. More...
 
#define UDMA_INST_ID_MAX   (UDMA_INST_ID_3)
 Maximum number of UDMA instance. More...
 
#define UDMA_NUM_INST_ID   (UDMA_INST_ID_MAX - UDMA_INST_ID_START + 1U)
 Total number of UDMA instances. More...
 
UDMA SOC Configuration

UDMA Soc Cfg - Flags to indicate the presnce of various SOC specific modules.

#define UDMA_SOC_CFG_LCDMA_PRESENT   (1U)
 Flag to indicate LCDMA module is present or not in the SOC. More...
 
#define UDMA_SOC_CFG_RA_LCDMA_PRESENT   (1U)
 Flag to indicate LCDMA RA is present or not in the SOC. More...
 
#define UDMA_SOC_CFG_UDMAP_PRESENT   (0U)
 
#define UDMA_SOC_CFG_PROXY_PRESENT   (0U)
 Flag to indicate Proxy is present or not in the SOC. More...
 
#define UDMA_SOC_CFG_CLEC_PRESENT   (0U)
 Flag to indicate Clec is present or not in the SOC. More...
 
#define UDMA_SOC_CFG_RA_NORMAL_PRESENT   (0U)
 Flag to indicate Normal RA is present or not in the SOC. More...
 
#define UDMA_SOC_CFG_RING_MON_PRESENT   (0U)
 Flag to indicate Ring Monitor is present or not in the SOC. More...
 
#define UDMA_SOC_CFG_APPLY_RING_WORKAROUND   (0U)
 Flag to indicate the SOC needs ring reset workaround. More...
 
UDMA Tx Channels FDEPTH

UDMA Tx Ch Fdepth - Fdepth of various types of channels present in the SOC.

#define UDMA_TX_UHC_CHANS_FDEPTH   (0U)
 Tx Ultra High Capacity Channel FDEPTH. More...
 
#define UDMA_TX_HC_CHANS_FDEPTH   (0U)
 Tx High Capacity Channel FDEPTH. More...
 
#define UDMA_TX_CHANS_FDEPTH   (192U)
 Tx Normal Channel FDEPTH. More...
 
UDMA Ringacc address select (asel) endpoint

List of all valid address select (asel) endpoints in the SOC.

#define UDMA_RINGACC_ASEL_ENDPOINT_PHYSADDR   ((uint32_t) 0U)
 Physical address (normal) More...
 
#define UDMA_RINGACC_ASEL_ENDPOINT_PCIE0   ((uint32_t) 1U)
 PCIE0. More...
 
#define UDMA_RINGACC_ASEL_ENDPOINT_ACP_WR_ALLOC   ((uint32_t) 14U)
 ARM ACP port: write-allocate cacheable, bufferable. More...
 
#define UDMA_RINGACC_ASEL_ENDPOINT_ACP_RD_ALLOC   ((uint32_t) 15U)
 ARM ACP port: read-allocate, cacheable, bufferable. More...
 
Mapped TX Group specific to a SOC

List of all mapped TX groups present in the SOC.

#define UDMA_MAPPED_TX_GROUP_CPSW   (UDMA_MAPPED_GROUP0)
 
#define UDMA_MAPPED_TX_GROUP_SAUL   (UDMA_MAPPED_GROUP1)
 
#define UDMA_MAPPED_TX_GROUP_ICSSG_0   (UDMA_MAPPED_GROUP2)
 
#define UDMA_MAPPED_TX_GROUP_ICSSG_1   (UDMA_MAPPED_GROUP3)
 
Mapped RX Group specific to a SOC

List of all mapped RX groups present in the SOC.

#define UDMA_MAPPED_RX_GROUP_CPSW   (UDMA_MAPPED_GROUP4)
 
#define UDMA_MAPPED_RX_GROUP_SAUL   (UDMA_MAPPED_GROUP5)
 
#define UDMA_MAPPED_RX_GROUP_ICSSG_0   (UDMA_MAPPED_GROUP6)
 
#define UDMA_MAPPED_RX_GROUP_ICSSG_1   (UDMA_MAPPED_GROUP7)
 
Core ID specific to a SOC

List of all cores present in the SOC.

#define UDMA_CORE_ID_MPU1_0   (0U)
 
#define UDMA_CORE_ID_MCU2_0   (1U)
 
#define UDMA_CORE_ID_MCU2_1   (2U)
 
#define UDMA_CORE_ID_MCU1_0   (3U)
 
#define UDMA_CORE_ID_MCU1_1   (4U)
 
#define UDMA_CORE_ID_M4F_0   (5U)
 
#define UDMA_NUM_CORE   (6U)
 
UDMA Resources ID

List of all UDMA Resources Id's.

#define UDMA_RM_RES_ID_BC_UHC   (0U)
 Ultra High Capacity Block Copy Channels. More...
 
#define UDMA_RM_RES_ID_BC_HC   (1U)
 High Capacity Block Copy Channels. More...
 
#define UDMA_RM_RES_ID_BC   (2U)
 Normal Capacity Block Copy Channels. More...
 
#define UDMA_RM_RES_ID_TX_UHC   (3U)
 Ultra High Capacity TX Channels. More...
 
#define UDMA_RM_RES_ID_TX_HC   (4U)
 High Capacity TX Channels. More...
 
#define UDMA_RM_RES_ID_TX   (5U)
 Normal Capacity TX Channels. More...
 
#define UDMA_RM_RES_ID_RX_UHC   (6U)
 Ultra High Capacity RX Channels. More...
 
#define UDMA_RM_RES_ID_RX_HC   (7U)
 High Capacity RX Channels. More...
 
#define UDMA_RM_RES_ID_RX   (8U)
 Normal Capacity RX Channels. More...
 
#define UDMA_RM_RES_ID_GLOBAL_EVENT   (9U)
 Global Event. More...
 
#define UDMA_RM_RES_ID_VINTR   (10U)
 Virtual Interrupts. More...
 
#define UDMA_RM_RES_ID_MAPPED_TX_CPSW   (11U)
 [Pktdma Only] Mapped TX Channels for CPSW More...
 
#define UDMA_RM_RES_ID_MAPPED_TX_SAUL_0   (12U)
 [Pktdma Only] Mapped TX Channels for SAUL_0 More...
 
#define UDMA_RM_RES_ID_MAPPED_TX_SAUL_1   (13U)
 [Pktdma Only] Mapped TX Channels for SAUL_1 More...
 
#define UDMA_RM_RES_ID_MAPPED_TX_ICSSG_0   (14U)
 [Pktdma Only] Mapped TX Channels for ICSSG_0 More...
 
#define UDMA_RM_RES_ID_MAPPED_TX_ICSSG_1   (15U)
 [Pktdma Only] Mapped TX Channels for ICSSG_1 More...
 
#define UDMA_RM_RES_ID_MAPPED_RX_CPSW   (16U)
 [Pktdma Only] Mapped RX Channels for CPSW More...
 
#define UDMA_RM_RES_ID_MAPPED_RX_SAUL_0   (17U)
 [Pktdma Only] Mapped RX Channels for SAUL_0 More...
 
#define UDMA_RM_RES_ID_MAPPED_RX_SAUL_1   (18U)
 [Pktdma Only] Mapped RX Channels for SAUL_1 More...
 
#define UDMA_RM_RES_ID_MAPPED_RX_SAUL_2   (19U)
 [Pktdma Only] Mapped RX Channels for SAUL_2 More...
 
#define UDMA_RM_RES_ID_MAPPED_RX_SAUL_3   (20U)
 [Pktdma Only] Mapped RX Channels for SAUL_3 More...
 
#define UDMA_RM_RES_ID_MAPPED_RX_ICSSG_0   (21U)
 [Pktdma Only] Mapped RX Channels for ICSSG_0 More...
 
#define UDMA_RM_RES_ID_MAPPED_RX_ICSSG_1   (22U)
 [Pktdma Only] Mapped RX Channels for ICSSG_1 More...
 
#define UDMA_RM_RES_ID_MAPPED_TX_RING_CPSW   (23U)
 [Pktdma Only] Mapped TX Rings for CPSW More...
 
#define UDMA_RM_RES_ID_MAPPED_TX_RING_SAUL_0   (24U)
 [Pktdma Only] Mapped TX Rings for SAUL_0 More...
 
#define UDMA_RM_RES_ID_MAPPED_TX_RING_SAUL_1   (25U)
 [Pktdma Only] Mapped TX Rings for SAUL_1 More...
 
#define UDMA_RM_RES_ID_MAPPED_TX_RING_ICSSG_0   (26U)
 [Pktdma Only] Mapped TX Rings for ICSSG_0 More...
 
#define UDMA_RM_RES_ID_MAPPED_TX_RING_ICSSG_1   (27U)
 [Pktdma Only] Mapped TX Rings for ICSSG_1 More...
 
#define UDMA_RM_RES_ID_MAPPED_RX_RING_CPSW   (28U)
 [Pktdma Only] Mapped RX Rings for CPSW More...
 
#define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_0   (29U)
 [Pktdma Only] Mapped RX Rings for SAUL_0 More...
 
#define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_1   (30U)
 [Pktdma Only] Mapped RX Rings for SAUL_1 More...
 
#define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_2   (31U)
 [Pktdma Only] Mapped RX Rings for SAUL_2 More...
 
#define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_3   (32U)
 [Pktdma Only] Mapped RX Rings for SAUL_3 More...
 
#define UDMA_RM_RES_ID_MAPPED_RX_RING_ICSSG_0   (33U)
 [Pktdma Only] Mapped RX Rings for ICSSG_0 More...
 
#define UDMA_RM_RES_ID_MAPPED_RX_RING_ICSSG_1   (34U)
 [Pktdma Only] Mapped RX Rings for ICSSG_1 More...
 
#define UDMA_RM_NUM_BCDMA_RES   (11U)
 Total number of BCDMA resources. More...
 
#define UDMA_RM_NUM_PKTDMA_RES   (35U)
 Total number of PKTDMA resources. More...
 
#define UDMA_RM_NUM_RES   (35U)
 Total number of resources. More...
 
PSIL Channels

List of all PSIL channels and the corresponding counts

#define UDMA_PSIL_CH_CPSW2_RX   (0x4500U)
 
#define UDMA_PSIL_CH_SAUL0_RX   (0x4000U)
 
#define UDMA_PSIL_CH_ICSS_G0_RX   (0x4100U)
 
#define UDMA_PSIL_CH_ICSS_G1_RX   (0x4200U)
 
#define UDMA_PSIL_CH_CPSW2_TX   (UDMA_PSIL_CH_CPSW2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
#define UDMA_PSIL_CH_SAUL0_TX   (UDMA_PSIL_CH_SAUL0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
#define UDMA_PSIL_CH_ICSS_G0_TX   (UDMA_PSIL_CH_ICSS_G0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
#define UDMA_PSIL_CH_ICSS_G1_TX   (UDMA_PSIL_CH_ICSS_G1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
#define UDMA_PSIL_CH_CPSW2_TX_CNT   (8U)
 
#define UDMA_PSIL_CH_SAUL0_TX_CNT   (2U)
 
#define UDMA_PSIL_CH_ICSS_G0_TX_CNT   (9U)
 
#define UDMA_PSIL_CH_ICSS_G1_TX_CNT   (9U)
 
#define UDMA_PSIL_CH_CPSW2_RX_CNT   (1U)
 
#define UDMA_PSIL_CH_SAUL0_RX_CNT   (4U)
 
#define UDMA_PSIL_CH_ICSS_G0_RX_CNT   (5U)
 
#define UDMA_PSIL_CH_ICSS_G1_RX_CNT   (5U)
 
Main0 RX PDMA Channels

List of all Main0 PDMA RX channels

#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_RX   (0x4300U + 0U)
 
#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_RX   (0x4300U + 1U)
 
#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_RX   (0x4300U + 2U)
 
#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_RX   (0x4300U + 3U)
 
#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_RX   (0x4300U + 4U)
 
#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_RX   (0x4300U + 5U)
 
#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_RX   (0x4300U + 6U)
 
#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_RX   (0x4300U + 7U)
 
#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_RX   (0x4300U + 8U)
 
#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_RX   (0x4300U + 9U)
 
#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_RX   (0x4300U + 10U)
 
#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_RX   (0x4300U + 11U)
 
#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_RX   (0x4300U + 12U)
 
#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_RX   (0x4300U + 13U)
 
#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_RX   (0x4300U + 14U)
 
#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_RX   (0x4300U + 15U)
 
#define UDMA_PDMA_CH_MAIN0_UART0_RX   (0x4300U + 16U)
 
#define UDMA_PDMA_CH_MAIN0_UART1_RX   (0x4300U + 17U)
 
Main0 TX PDMA Channels

List of all Main0 PDMA TX channels

#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_TX   (UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_TX   (UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_TX   (UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_TX   (UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_TX   (UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_TX   (UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_TX   (UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_TX   (UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_TX   (UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_TX   (UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_TX   (UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_TX   (UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_TX   (UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_TX   (UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_TX   (UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_TX   (UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
#define UDMA_PDMA_CH_MAIN0_UART0_TX   (UDMA_PDMA_CH_MAIN0_UART0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
#define UDMA_PDMA_CH_MAIN0_UART1_TX   (UDMA_PDMA_CH_MAIN0_UART1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
Main1 RX PDMA Channels

List of all Main1 PDMA RX channels

#define UDMA_PDMA_CH_MAIN1_MCSPI4_CH0_RX   (0x4400U + 0U)
 
#define UDMA_PDMA_CH_MAIN1_MCSPI4_CH1_RX   (0x4400U + 1U)
 
#define UDMA_PDMA_CH_MAIN1_MCSPI4_CH2_RX   (0x4400U + 2U)
 
#define UDMA_PDMA_CH_MAIN1_MCSPI4_CH3_RX   (0x4400U + 3U)
 
#define UDMA_PDMA_CH_MAIN1_UART2_RX   (0x4400U + 4U)
 
#define UDMA_PDMA_CH_MAIN1_UART3_RX   (0x4400U + 5U)
 
#define UDMA_PDMA_CH_MAIN1_UART4_RX   (0x4400U + 6U)
 
#define UDMA_PDMA_CH_MAIN1_UART5_RX   (0x4400U + 7U)
 
#define UDMA_PDMA_CH_MAIN1_UART6_RX   (0x4400U + 8U)
 
#define UDMA_PDMA_CH_MAIN1_MCAN0_CH0_RX   (0x4400U + 9U)
 
#define UDMA_PDMA_CH_MAIN1_MCAN0_CH1_RX   (0x4400U + 10U)
 
#define UDMA_PDMA_CH_MAIN1_MCAN0_CH2_RX   (0x4400U + 11U)
 
#define UDMA_PDMA_CH_MAIN1_MCAN1_CH0_RX   (0x4400U + 12U)
 
#define UDMA_PDMA_CH_MAIN1_MCAN1_CH1_RX   (0x4400U + 13U)
 
#define UDMA_PDMA_CH_MAIN1_MCAN1_CH2_RX   (0x4400U + 14U)
 
#define UDMA_PDMA_CH_MAIN1_ADC0_CH0_RX   (0x4400U + 15U)
 
#define UDMA_PDMA_CH_MAIN1_ADC0_CH1_RX   (0x4400U + 16U)
 
Main1 TX PDMA Channels

List of all Main1 PDMA TX channels

#define UDMA_PDMA_CH_MAIN1_MCSPI4_CH0_TX   (UDMA_PDMA_CH_MAIN1_MCSPI4_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
#define UDMA_PDMA_CH_MAIN1_MCSPI4_CH1_TX   (UDMA_PDMA_CH_MAIN1_MCSPI4_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
#define UDMA_PDMA_CH_MAIN1_MCSPI4_CH2_TX   (UDMA_PDMA_CH_MAIN1_MCSPI4_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
#define UDMA_PDMA_CH_MAIN1_MCSPI4_CH3_TX   (UDMA_PDMA_CH_MAIN1_MCSPI4_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
#define UDMA_PDMA_CH_MAIN1_UART2_TX   (UDMA_PDMA_CH_MAIN1_UART2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
#define UDMA_PDMA_CH_MAIN1_UART3_TX   (UDMA_PDMA_CH_MAIN1_UART3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
#define UDMA_PDMA_CH_MAIN1_UART4_TX   (UDMA_PDMA_CH_MAIN1_UART4_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
#define UDMA_PDMA_CH_MAIN1_UART5_TX   (UDMA_PDMA_CH_MAIN1_UART5_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
#define UDMA_PDMA_CH_MAIN1_UART6_TX   (UDMA_PDMA_CH_MAIN1_UART6_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
#define UDMA_PDMA_CH_MAIN1_MCAN0_CH0_TX   (UDMA_PDMA_CH_MAIN1_MCAN0_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
#define UDMA_PDMA_CH_MAIN1_MCAN0_CH1_TX   (UDMA_PDMA_CH_MAIN1_MCAN0_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
#define UDMA_PDMA_CH_MAIN1_MCAN0_CH2_TX   (UDMA_PDMA_CH_MAIN1_MCAN0_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
#define UDMA_PDMA_CH_MAIN1_MCAN1_CH0_TX   (UDMA_PDMA_CH_MAIN1_MCAN1_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
#define UDMA_PDMA_CH_MAIN1_MCAN1_CH1_TX   (UDMA_PDMA_CH_MAIN1_MCAN1_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
#define UDMA_PDMA_CH_MAIN1_MCAN1_CH2_TX   (UDMA_PDMA_CH_MAIN1_MCAN1_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 

Functions

uint32_t Udma_isCacheCoherent (void)
 Returns TRUE if the memory is cache coherent. More...
 

Macro Definition Documentation

◆ UDMA_INST_ID_BCDMA_0

#define UDMA_INST_ID_BCDMA_0   (UDMA_INST_ID_2)

BCDMA instance.

◆ UDMA_INST_ID_PKTDMA_0

#define UDMA_INST_ID_PKTDMA_0   (UDMA_INST_ID_3)

PKTDMA instance.

◆ UDMA_INST_ID_START

#define UDMA_INST_ID_START   (UDMA_INST_ID_2)

Start of UDMA instance.

◆ UDMA_INST_ID_MAX

#define UDMA_INST_ID_MAX   (UDMA_INST_ID_3)

Maximum number of UDMA instance.

◆ UDMA_NUM_INST_ID

#define UDMA_NUM_INST_ID   (UDMA_INST_ID_MAX - UDMA_INST_ID_START + 1U)

Total number of UDMA instances.

◆ UDMA_SOC_CFG_LCDMA_PRESENT

#define UDMA_SOC_CFG_LCDMA_PRESENT   (1U)

Flag to indicate LCDMA module is present or not in the SOC.

◆ UDMA_SOC_CFG_RA_LCDMA_PRESENT

#define UDMA_SOC_CFG_RA_LCDMA_PRESENT   (1U)

Flag to indicate LCDMA RA is present or not in the SOC.

◆ UDMA_SOC_CFG_UDMAP_PRESENT

#define UDMA_SOC_CFG_UDMAP_PRESENT   (0U)

◆ UDMA_SOC_CFG_PROXY_PRESENT

#define UDMA_SOC_CFG_PROXY_PRESENT   (0U)

Flag to indicate Proxy is present or not in the SOC.

◆ UDMA_SOC_CFG_CLEC_PRESENT

#define UDMA_SOC_CFG_CLEC_PRESENT   (0U)

Flag to indicate Clec is present or not in the SOC.

◆ UDMA_SOC_CFG_RA_NORMAL_PRESENT

#define UDMA_SOC_CFG_RA_NORMAL_PRESENT   (0U)

Flag to indicate Normal RA is present or not in the SOC.

◆ UDMA_SOC_CFG_RING_MON_PRESENT

#define UDMA_SOC_CFG_RING_MON_PRESENT   (0U)

Flag to indicate Ring Monitor is present or not in the SOC.

◆ UDMA_SOC_CFG_APPLY_RING_WORKAROUND

#define UDMA_SOC_CFG_APPLY_RING_WORKAROUND   (0U)

Flag to indicate the SOC needs ring reset workaround.

◆ UDMA_TX_UHC_CHANS_FDEPTH

#define UDMA_TX_UHC_CHANS_FDEPTH   (0U)

Tx Ultra High Capacity Channel FDEPTH.

◆ UDMA_TX_HC_CHANS_FDEPTH

#define UDMA_TX_HC_CHANS_FDEPTH   (0U)

Tx High Capacity Channel FDEPTH.

◆ UDMA_TX_CHANS_FDEPTH

#define UDMA_TX_CHANS_FDEPTH   (192U)

Tx Normal Channel FDEPTH.

◆ UDMA_RINGACC_ASEL_ENDPOINT_PHYSADDR

#define UDMA_RINGACC_ASEL_ENDPOINT_PHYSADDR   ((uint32_t) 0U)

Physical address (normal)

◆ UDMA_RINGACC_ASEL_ENDPOINT_PCIE0

#define UDMA_RINGACC_ASEL_ENDPOINT_PCIE0   ((uint32_t) 1U)

PCIE0.

◆ UDMA_RINGACC_ASEL_ENDPOINT_ACP_WR_ALLOC

#define UDMA_RINGACC_ASEL_ENDPOINT_ACP_WR_ALLOC   ((uint32_t) 14U)

ARM ACP port: write-allocate cacheable, bufferable.

◆ UDMA_RINGACC_ASEL_ENDPOINT_ACP_RD_ALLOC

#define UDMA_RINGACC_ASEL_ENDPOINT_ACP_RD_ALLOC   ((uint32_t) 15U)

ARM ACP port: read-allocate, cacheable, bufferable.

◆ UDMA_NUM_MAPPED_TX_GROUP

#define UDMA_NUM_MAPPED_TX_GROUP   (4U)

Number of Mapped TX Group.

◆ UDMA_MAPPED_TX_GROUP_CPSW

#define UDMA_MAPPED_TX_GROUP_CPSW   (UDMA_MAPPED_GROUP0)

◆ UDMA_MAPPED_TX_GROUP_SAUL

#define UDMA_MAPPED_TX_GROUP_SAUL   (UDMA_MAPPED_GROUP1)

◆ UDMA_MAPPED_TX_GROUP_ICSSG_0

#define UDMA_MAPPED_TX_GROUP_ICSSG_0   (UDMA_MAPPED_GROUP2)

◆ UDMA_MAPPED_TX_GROUP_ICSSG_1

#define UDMA_MAPPED_TX_GROUP_ICSSG_1   (UDMA_MAPPED_GROUP3)

◆ UDMA_NUM_MAPPED_RX_GROUP

#define UDMA_NUM_MAPPED_RX_GROUP   (4U)

Number of Mapped RX Group.

◆ UDMA_MAPPED_RX_GROUP_CPSW

#define UDMA_MAPPED_RX_GROUP_CPSW   (UDMA_MAPPED_GROUP4)

◆ UDMA_MAPPED_RX_GROUP_SAUL

#define UDMA_MAPPED_RX_GROUP_SAUL   (UDMA_MAPPED_GROUP5)

◆ UDMA_MAPPED_RX_GROUP_ICSSG_0

#define UDMA_MAPPED_RX_GROUP_ICSSG_0   (UDMA_MAPPED_GROUP6)

◆ UDMA_MAPPED_RX_GROUP_ICSSG_1

#define UDMA_MAPPED_RX_GROUP_ICSSG_1   (UDMA_MAPPED_GROUP7)

◆ UDMA_CORE_ID_MPU1_0

#define UDMA_CORE_ID_MPU1_0   (0U)

◆ UDMA_CORE_ID_MCU2_0

#define UDMA_CORE_ID_MCU2_0   (1U)

◆ UDMA_CORE_ID_MCU2_1

#define UDMA_CORE_ID_MCU2_1   (2U)

◆ UDMA_CORE_ID_MCU1_0

#define UDMA_CORE_ID_MCU1_0   (3U)

◆ UDMA_CORE_ID_MCU1_1

#define UDMA_CORE_ID_MCU1_1   (4U)

◆ UDMA_CORE_ID_M4F_0

#define UDMA_CORE_ID_M4F_0   (5U)

◆ UDMA_NUM_CORE

#define UDMA_NUM_CORE   (6U)

◆ UDMA_RM_RES_ID_BC_UHC

#define UDMA_RM_RES_ID_BC_UHC   (0U)

Ultra High Capacity Block Copy Channels.

◆ UDMA_RM_RES_ID_BC_HC

#define UDMA_RM_RES_ID_BC_HC   (1U)

High Capacity Block Copy Channels.

◆ UDMA_RM_RES_ID_BC

#define UDMA_RM_RES_ID_BC   (2U)

Normal Capacity Block Copy Channels.

◆ UDMA_RM_RES_ID_TX_UHC

#define UDMA_RM_RES_ID_TX_UHC   (3U)

Ultra High Capacity TX Channels.

◆ UDMA_RM_RES_ID_TX_HC

#define UDMA_RM_RES_ID_TX_HC   (4U)

High Capacity TX Channels.

◆ UDMA_RM_RES_ID_TX

#define UDMA_RM_RES_ID_TX   (5U)

Normal Capacity TX Channels.

◆ UDMA_RM_RES_ID_RX_UHC

#define UDMA_RM_RES_ID_RX_UHC   (6U)

Ultra High Capacity RX Channels.

◆ UDMA_RM_RES_ID_RX_HC

#define UDMA_RM_RES_ID_RX_HC   (7U)

High Capacity RX Channels.

◆ UDMA_RM_RES_ID_RX

#define UDMA_RM_RES_ID_RX   (8U)

Normal Capacity RX Channels.

◆ UDMA_RM_RES_ID_GLOBAL_EVENT

#define UDMA_RM_RES_ID_GLOBAL_EVENT   (9U)

Global Event.

◆ UDMA_RM_RES_ID_VINTR

#define UDMA_RM_RES_ID_VINTR   (10U)

Virtual Interrupts.

◆ UDMA_RM_RES_ID_MAPPED_TX_CPSW

#define UDMA_RM_RES_ID_MAPPED_TX_CPSW   (11U)

[Pktdma Only] Mapped TX Channels for CPSW

◆ UDMA_RM_RES_ID_MAPPED_TX_SAUL_0

#define UDMA_RM_RES_ID_MAPPED_TX_SAUL_0   (12U)

[Pktdma Only] Mapped TX Channels for SAUL_0

◆ UDMA_RM_RES_ID_MAPPED_TX_SAUL_1

#define UDMA_RM_RES_ID_MAPPED_TX_SAUL_1   (13U)

[Pktdma Only] Mapped TX Channels for SAUL_1

◆ UDMA_RM_RES_ID_MAPPED_TX_ICSSG_0

#define UDMA_RM_RES_ID_MAPPED_TX_ICSSG_0   (14U)

[Pktdma Only] Mapped TX Channels for ICSSG_0

◆ UDMA_RM_RES_ID_MAPPED_TX_ICSSG_1

#define UDMA_RM_RES_ID_MAPPED_TX_ICSSG_1   (15U)

[Pktdma Only] Mapped TX Channels for ICSSG_1

◆ UDMA_RM_RES_ID_MAPPED_RX_CPSW

#define UDMA_RM_RES_ID_MAPPED_RX_CPSW   (16U)

[Pktdma Only] Mapped RX Channels for CPSW

◆ UDMA_RM_RES_ID_MAPPED_RX_SAUL_0

#define UDMA_RM_RES_ID_MAPPED_RX_SAUL_0   (17U)

[Pktdma Only] Mapped RX Channels for SAUL_0

◆ UDMA_RM_RES_ID_MAPPED_RX_SAUL_1

#define UDMA_RM_RES_ID_MAPPED_RX_SAUL_1   (18U)

[Pktdma Only] Mapped RX Channels for SAUL_1

◆ UDMA_RM_RES_ID_MAPPED_RX_SAUL_2

#define UDMA_RM_RES_ID_MAPPED_RX_SAUL_2   (19U)

[Pktdma Only] Mapped RX Channels for SAUL_2

◆ UDMA_RM_RES_ID_MAPPED_RX_SAUL_3

#define UDMA_RM_RES_ID_MAPPED_RX_SAUL_3   (20U)

[Pktdma Only] Mapped RX Channels for SAUL_3

◆ UDMA_RM_RES_ID_MAPPED_RX_ICSSG_0

#define UDMA_RM_RES_ID_MAPPED_RX_ICSSG_0   (21U)

[Pktdma Only] Mapped RX Channels for ICSSG_0

◆ UDMA_RM_RES_ID_MAPPED_RX_ICSSG_1

#define UDMA_RM_RES_ID_MAPPED_RX_ICSSG_1   (22U)

[Pktdma Only] Mapped RX Channels for ICSSG_1

◆ UDMA_RM_RES_ID_MAPPED_TX_RING_CPSW

#define UDMA_RM_RES_ID_MAPPED_TX_RING_CPSW   (23U)

[Pktdma Only] Mapped TX Rings for CPSW

◆ UDMA_RM_RES_ID_MAPPED_TX_RING_SAUL_0

#define UDMA_RM_RES_ID_MAPPED_TX_RING_SAUL_0   (24U)

[Pktdma Only] Mapped TX Rings for SAUL_0

◆ UDMA_RM_RES_ID_MAPPED_TX_RING_SAUL_1

#define UDMA_RM_RES_ID_MAPPED_TX_RING_SAUL_1   (25U)

[Pktdma Only] Mapped TX Rings for SAUL_1

◆ UDMA_RM_RES_ID_MAPPED_TX_RING_ICSSG_0

#define UDMA_RM_RES_ID_MAPPED_TX_RING_ICSSG_0   (26U)

[Pktdma Only] Mapped TX Rings for ICSSG_0

◆ UDMA_RM_RES_ID_MAPPED_TX_RING_ICSSG_1

#define UDMA_RM_RES_ID_MAPPED_TX_RING_ICSSG_1   (27U)

[Pktdma Only] Mapped TX Rings for ICSSG_1

◆ UDMA_RM_RES_ID_MAPPED_RX_RING_CPSW

#define UDMA_RM_RES_ID_MAPPED_RX_RING_CPSW   (28U)

[Pktdma Only] Mapped RX Rings for CPSW

◆ UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_0

#define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_0   (29U)

[Pktdma Only] Mapped RX Rings for SAUL_0

◆ UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_1

#define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_1   (30U)

[Pktdma Only] Mapped RX Rings for SAUL_1

◆ UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_2

#define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_2   (31U)

[Pktdma Only] Mapped RX Rings for SAUL_2

◆ UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_3

#define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_3   (32U)

[Pktdma Only] Mapped RX Rings for SAUL_3

◆ UDMA_RM_RES_ID_MAPPED_RX_RING_ICSSG_0

#define UDMA_RM_RES_ID_MAPPED_RX_RING_ICSSG_0   (33U)

[Pktdma Only] Mapped RX Rings for ICSSG_0

◆ UDMA_RM_RES_ID_MAPPED_RX_RING_ICSSG_1

#define UDMA_RM_RES_ID_MAPPED_RX_RING_ICSSG_1   (34U)

[Pktdma Only] Mapped RX Rings for ICSSG_1

◆ UDMA_RM_NUM_BCDMA_RES

#define UDMA_RM_NUM_BCDMA_RES   (11U)

Total number of BCDMA resources.

◆ UDMA_RM_NUM_PKTDMA_RES

#define UDMA_RM_NUM_PKTDMA_RES   (35U)

Total number of PKTDMA resources.

◆ UDMA_RM_NUM_RES

#define UDMA_RM_NUM_RES   (35U)

Total number of resources.

◆ UDMA_RM_NUM_SHARED_RES

#define UDMA_RM_NUM_SHARED_RES   (2U)

Total number of shared resources - Global_Event/IR Intr.

◆ UDMA_RM_SHARED_RES_MAX_INST

#define UDMA_RM_SHARED_RES_MAX_INST   (UDMA_NUM_CORE)

Maximum no.of instances to split a shared resource. This should be max(UDMA_NUM_CORE,UDMA_NUM_INST_ID)

◆ UDMA_PSIL_DEST_THREAD_OFFSET

#define UDMA_PSIL_DEST_THREAD_OFFSET   (0x8000U)

Destination thread offset.

◆ UDMA_PSIL_CH_CPSW2_RX

#define UDMA_PSIL_CH_CPSW2_RX   (0x4500U)

◆ UDMA_PSIL_CH_SAUL0_RX

#define UDMA_PSIL_CH_SAUL0_RX   (0x4000U)

◆ UDMA_PSIL_CH_ICSS_G0_RX

#define UDMA_PSIL_CH_ICSS_G0_RX   (0x4100U)

◆ UDMA_PSIL_CH_ICSS_G1_RX

#define UDMA_PSIL_CH_ICSS_G1_RX   (0x4200U)

◆ UDMA_PSIL_CH_CPSW2_TX

#define UDMA_PSIL_CH_CPSW2_TX   (UDMA_PSIL_CH_CPSW2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

◆ UDMA_PSIL_CH_SAUL0_TX

#define UDMA_PSIL_CH_SAUL0_TX   (UDMA_PSIL_CH_SAUL0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

◆ UDMA_PSIL_CH_ICSS_G0_TX

#define UDMA_PSIL_CH_ICSS_G0_TX   (UDMA_PSIL_CH_ICSS_G0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

◆ UDMA_PSIL_CH_ICSS_G1_TX

#define UDMA_PSIL_CH_ICSS_G1_TX   (UDMA_PSIL_CH_ICSS_G1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

◆ UDMA_PSIL_CH_CPSW2_TX_CNT

#define UDMA_PSIL_CH_CPSW2_TX_CNT   (8U)

◆ UDMA_PSIL_CH_SAUL0_TX_CNT

#define UDMA_PSIL_CH_SAUL0_TX_CNT   (2U)

◆ UDMA_PSIL_CH_ICSS_G0_TX_CNT

#define UDMA_PSIL_CH_ICSS_G0_TX_CNT   (9U)

◆ UDMA_PSIL_CH_ICSS_G1_TX_CNT

#define UDMA_PSIL_CH_ICSS_G1_TX_CNT   (9U)

◆ UDMA_PSIL_CH_CPSW2_RX_CNT

#define UDMA_PSIL_CH_CPSW2_RX_CNT   (1U)

◆ UDMA_PSIL_CH_SAUL0_RX_CNT

#define UDMA_PSIL_CH_SAUL0_RX_CNT   (4U)

◆ UDMA_PSIL_CH_ICSS_G0_RX_CNT

#define UDMA_PSIL_CH_ICSS_G0_RX_CNT   (5U)

◆ UDMA_PSIL_CH_ICSS_G1_RX_CNT

#define UDMA_PSIL_CH_ICSS_G1_RX_CNT   (5U)

◆ UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_RX

#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_RX   (0x4300U + 0U)

◆ UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_RX

#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_RX   (0x4300U + 1U)

◆ UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_RX

#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_RX   (0x4300U + 2U)

◆ UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_RX

#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_RX   (0x4300U + 3U)

◆ UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_RX

#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_RX   (0x4300U + 4U)

◆ UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_RX

#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_RX   (0x4300U + 5U)

◆ UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_RX

#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_RX   (0x4300U + 6U)

◆ UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_RX

#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_RX   (0x4300U + 7U)

◆ UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_RX

#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_RX   (0x4300U + 8U)

◆ UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_RX

#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_RX   (0x4300U + 9U)

◆ UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_RX

#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_RX   (0x4300U + 10U)

◆ UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_RX

#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_RX   (0x4300U + 11U)

◆ UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_RX

#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_RX   (0x4300U + 12U)

◆ UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_RX

#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_RX   (0x4300U + 13U)

◆ UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_RX

#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_RX   (0x4300U + 14U)

◆ UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_RX

#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_RX   (0x4300U + 15U)

◆ UDMA_PDMA_CH_MAIN0_UART0_RX

#define UDMA_PDMA_CH_MAIN0_UART0_RX   (0x4300U + 16U)

◆ UDMA_PDMA_CH_MAIN0_UART1_RX

#define UDMA_PDMA_CH_MAIN0_UART1_RX   (0x4300U + 17U)

◆ UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_TX

#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_TX   (UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

◆ UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_TX

#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_TX   (UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

◆ UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_TX

#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_TX   (UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

◆ UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_TX

#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_TX   (UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

◆ UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_TX

#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_TX   (UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

◆ UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_TX

#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_TX   (UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

◆ UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_TX

#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_TX   (UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

◆ UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_TX

#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_TX   (UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

◆ UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_TX

#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_TX   (UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

◆ UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_TX

#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_TX   (UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

◆ UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_TX

#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_TX   (UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

◆ UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_TX

#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_TX   (UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

◆ UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_TX

#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_TX   (UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

◆ UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_TX

#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_TX   (UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

◆ UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_TX

#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_TX   (UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

◆ UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_TX

#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_TX   (UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

◆ UDMA_PDMA_CH_MAIN0_UART0_TX

#define UDMA_PDMA_CH_MAIN0_UART0_TX   (UDMA_PDMA_CH_MAIN0_UART0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

◆ UDMA_PDMA_CH_MAIN0_UART1_TX

#define UDMA_PDMA_CH_MAIN0_UART1_TX   (UDMA_PDMA_CH_MAIN0_UART1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

◆ UDMA_PDMA_CH_MAIN1_MCSPI4_CH0_RX

#define UDMA_PDMA_CH_MAIN1_MCSPI4_CH0_RX   (0x4400U + 0U)

◆ UDMA_PDMA_CH_MAIN1_MCSPI4_CH1_RX

#define UDMA_PDMA_CH_MAIN1_MCSPI4_CH1_RX   (0x4400U + 1U)

◆ UDMA_PDMA_CH_MAIN1_MCSPI4_CH2_RX

#define UDMA_PDMA_CH_MAIN1_MCSPI4_CH2_RX   (0x4400U + 2U)

◆ UDMA_PDMA_CH_MAIN1_MCSPI4_CH3_RX

#define UDMA_PDMA_CH_MAIN1_MCSPI4_CH3_RX   (0x4400U + 3U)

◆ UDMA_PDMA_CH_MAIN1_UART2_RX

#define UDMA_PDMA_CH_MAIN1_UART2_RX   (0x4400U + 4U)

◆ UDMA_PDMA_CH_MAIN1_UART3_RX

#define UDMA_PDMA_CH_MAIN1_UART3_RX   (0x4400U + 5U)

◆ UDMA_PDMA_CH_MAIN1_UART4_RX

#define UDMA_PDMA_CH_MAIN1_UART4_RX   (0x4400U + 6U)

◆ UDMA_PDMA_CH_MAIN1_UART5_RX

#define UDMA_PDMA_CH_MAIN1_UART5_RX   (0x4400U + 7U)

◆ UDMA_PDMA_CH_MAIN1_UART6_RX

#define UDMA_PDMA_CH_MAIN1_UART6_RX   (0x4400U + 8U)

◆ UDMA_PDMA_CH_MAIN1_MCAN0_CH0_RX

#define UDMA_PDMA_CH_MAIN1_MCAN0_CH0_RX   (0x4400U + 9U)

◆ UDMA_PDMA_CH_MAIN1_MCAN0_CH1_RX

#define UDMA_PDMA_CH_MAIN1_MCAN0_CH1_RX   (0x4400U + 10U)

◆ UDMA_PDMA_CH_MAIN1_MCAN0_CH2_RX

#define UDMA_PDMA_CH_MAIN1_MCAN0_CH2_RX   (0x4400U + 11U)

◆ UDMA_PDMA_CH_MAIN1_MCAN1_CH0_RX

#define UDMA_PDMA_CH_MAIN1_MCAN1_CH0_RX   (0x4400U + 12U)

◆ UDMA_PDMA_CH_MAIN1_MCAN1_CH1_RX

#define UDMA_PDMA_CH_MAIN1_MCAN1_CH1_RX   (0x4400U + 13U)

◆ UDMA_PDMA_CH_MAIN1_MCAN1_CH2_RX

#define UDMA_PDMA_CH_MAIN1_MCAN1_CH2_RX   (0x4400U + 14U)

◆ UDMA_PDMA_CH_MAIN1_ADC0_CH0_RX

#define UDMA_PDMA_CH_MAIN1_ADC0_CH0_RX   (0x4400U + 15U)

◆ UDMA_PDMA_CH_MAIN1_ADC0_CH1_RX

#define UDMA_PDMA_CH_MAIN1_ADC0_CH1_RX   (0x4400U + 16U)

◆ UDMA_PDMA_CH_MAIN1_MCSPI4_CH0_TX

#define UDMA_PDMA_CH_MAIN1_MCSPI4_CH0_TX   (UDMA_PDMA_CH_MAIN1_MCSPI4_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

◆ UDMA_PDMA_CH_MAIN1_MCSPI4_CH1_TX

#define UDMA_PDMA_CH_MAIN1_MCSPI4_CH1_TX   (UDMA_PDMA_CH_MAIN1_MCSPI4_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

◆ UDMA_PDMA_CH_MAIN1_MCSPI4_CH2_TX

#define UDMA_PDMA_CH_MAIN1_MCSPI4_CH2_TX   (UDMA_PDMA_CH_MAIN1_MCSPI4_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

◆ UDMA_PDMA_CH_MAIN1_MCSPI4_CH3_TX

#define UDMA_PDMA_CH_MAIN1_MCSPI4_CH3_TX   (UDMA_PDMA_CH_MAIN1_MCSPI4_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

◆ UDMA_PDMA_CH_MAIN1_UART2_TX

#define UDMA_PDMA_CH_MAIN1_UART2_TX   (UDMA_PDMA_CH_MAIN1_UART2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

◆ UDMA_PDMA_CH_MAIN1_UART3_TX

#define UDMA_PDMA_CH_MAIN1_UART3_TX   (UDMA_PDMA_CH_MAIN1_UART3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

◆ UDMA_PDMA_CH_MAIN1_UART4_TX

#define UDMA_PDMA_CH_MAIN1_UART4_TX   (UDMA_PDMA_CH_MAIN1_UART4_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

◆ UDMA_PDMA_CH_MAIN1_UART5_TX

#define UDMA_PDMA_CH_MAIN1_UART5_TX   (UDMA_PDMA_CH_MAIN1_UART5_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

◆ UDMA_PDMA_CH_MAIN1_UART6_TX

#define UDMA_PDMA_CH_MAIN1_UART6_TX   (UDMA_PDMA_CH_MAIN1_UART6_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

◆ UDMA_PDMA_CH_MAIN1_MCAN0_CH0_TX

#define UDMA_PDMA_CH_MAIN1_MCAN0_CH0_TX   (UDMA_PDMA_CH_MAIN1_MCAN0_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

◆ UDMA_PDMA_CH_MAIN1_MCAN0_CH1_TX

#define UDMA_PDMA_CH_MAIN1_MCAN0_CH1_TX   (UDMA_PDMA_CH_MAIN1_MCAN0_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

◆ UDMA_PDMA_CH_MAIN1_MCAN0_CH2_TX

#define UDMA_PDMA_CH_MAIN1_MCAN0_CH2_TX   (UDMA_PDMA_CH_MAIN1_MCAN0_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

◆ UDMA_PDMA_CH_MAIN1_MCAN1_CH0_TX

#define UDMA_PDMA_CH_MAIN1_MCAN1_CH0_TX   (UDMA_PDMA_CH_MAIN1_MCAN1_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

◆ UDMA_PDMA_CH_MAIN1_MCAN1_CH1_TX

#define UDMA_PDMA_CH_MAIN1_MCAN1_CH1_TX   (UDMA_PDMA_CH_MAIN1_MCAN1_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

◆ UDMA_PDMA_CH_MAIN1_MCAN1_CH2_TX

#define UDMA_PDMA_CH_MAIN1_MCAN1_CH2_TX   (UDMA_PDMA_CH_MAIN1_MCAN1_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)

Function Documentation

◆ Udma_isCacheCoherent()

uint32_t Udma_isCacheCoherent ( void  )

Returns TRUE if the memory is cache coherent.

Returns
TRUE/FALSE