AM64x MCU+ SDK  10.00.00
udma_soc.h
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1 /*
2  * Copyright (C) 2018-2021 Texas Instruments Incorporated
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  *
8  * Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  *
11  * Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the
14  * distribution.
15  *
16  * Neither the name of Texas Instruments Incorporated nor the names of
17  * its contributors may be used to endorse or promote products derived
18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
39 #ifndef UDMA_SOC_H_
40 #define UDMA_SOC_H_
41 
42 /* ========================================================================== */
43 /* Include Files */
44 /* ========================================================================== */
45 
46 /* None */
47 
48 #ifdef __cplusplus
49 extern "C" {
50 #endif
51 
52 /* ========================================================================== */
53 /* Macros & Typedefs */
54 /* ========================================================================== */
55 
65 #define UDMA_INST_ID_BCDMA_0 (UDMA_INST_ID_2)
66 
67 #define UDMA_INST_ID_PKTDMA_0 (UDMA_INST_ID_3)
68 
69 #define UDMA_INST_ID_START (UDMA_INST_ID_2)
70 
71 #define UDMA_INST_ID_MAX (UDMA_INST_ID_3)
72 
73 #define UDMA_NUM_INST_ID (UDMA_INST_ID_MAX - UDMA_INST_ID_START + 1U)
74 
85 #define UDMA_SOC_CFG_LCDMA_PRESENT (1U)
86 
88 #define UDMA_SOC_CFG_RA_LCDMA_PRESENT (1U)
89 
90 #define UDMA_SOC_CFG_UDMAP_PRESENT (0U)
91 
93 #define UDMA_SOC_CFG_PROXY_PRESENT (0U)
94 
96 #define UDMA_SOC_CFG_CLEC_PRESENT (0U)
97 
99 #define UDMA_SOC_CFG_RA_NORMAL_PRESENT (0U)
100 
102 #define UDMA_SOC_CFG_RING_MON_PRESENT (0U)
103 
105 #define UDMA_SOC_CFG_APPLY_RING_WORKAROUND (0U)
106 
118 #define UDMA_TX_UHC_CHANS_FDEPTH (0U)
119 
120 #define UDMA_TX_HC_CHANS_FDEPTH (0U)
121 
122 #define UDMA_TX_CHANS_FDEPTH (192U)
123 
134 #define UDMA_RINGACC_ASEL_ENDPOINT_PHYSADDR ((uint32_t) 0U)
135 
136 #define UDMA_RINGACC_ASEL_ENDPOINT_PCIE0 ((uint32_t) 1U)
137 
138 #define UDMA_RINGACC_ASEL_ENDPOINT_ACP_WR_ALLOC ((uint32_t) 14U)
139 
140 #define UDMA_RINGACC_ASEL_ENDPOINT_ACP_RD_ALLOC ((uint32_t) 15U)
141 
144 #define UDMA_NUM_MAPPED_TX_GROUP (4U)
145 
153 #define UDMA_MAPPED_TX_GROUP_CPSW (UDMA_MAPPED_GROUP0)
154 #define UDMA_MAPPED_TX_GROUP_SAUL (UDMA_MAPPED_GROUP1)
155 #define UDMA_MAPPED_TX_GROUP_ICSSG_0 (UDMA_MAPPED_GROUP2)
156 #define UDMA_MAPPED_TX_GROUP_ICSSG_1 (UDMA_MAPPED_GROUP3)
157 
160 #define UDMA_NUM_MAPPED_RX_GROUP (4U)
161 
169 #define UDMA_MAPPED_RX_GROUP_CPSW (UDMA_MAPPED_GROUP4)
170 #define UDMA_MAPPED_RX_GROUP_SAUL (UDMA_MAPPED_GROUP5)
171 #define UDMA_MAPPED_RX_GROUP_ICSSG_0 (UDMA_MAPPED_GROUP6)
172 #define UDMA_MAPPED_RX_GROUP_ICSSG_1 (UDMA_MAPPED_GROUP7)
173 
183 /*
184  * Locally used core ID to define default RM configuration.
185  * Not to be used by caller
186  */
187 #define UDMA_CORE_ID_MPU1_0 (0U)
188 #define UDMA_CORE_ID_MCU2_0 (1U)
189 #define UDMA_CORE_ID_MCU2_1 (2U)
190 #define UDMA_CORE_ID_MCU1_0 (3U)
191 #define UDMA_CORE_ID_MCU1_1 (4U)
192 #define UDMA_CORE_ID_M4F_0 (5U)
193 /* Total number of cores */
194 #define UDMA_NUM_CORE (6U)
195 
206 #define UDMA_RM_RES_ID_BC_UHC (0U)
207 
208 #define UDMA_RM_RES_ID_BC_HC (1U)
209 
210 #define UDMA_RM_RES_ID_BC (2U)
211 
212 #define UDMA_RM_RES_ID_TX_UHC (3U)
213 
214 #define UDMA_RM_RES_ID_TX_HC (4U)
215 
216 #define UDMA_RM_RES_ID_TX (5U)
217 
218 #define UDMA_RM_RES_ID_RX_UHC (6U)
219 
220 #define UDMA_RM_RES_ID_RX_HC (7U)
221 
222 #define UDMA_RM_RES_ID_RX (8U)
223 
224 #define UDMA_RM_RES_ID_GLOBAL_EVENT (9U)
225 
226 #define UDMA_RM_RES_ID_VINTR (10U)
227 
228 #define UDMA_RM_RES_ID_MAPPED_TX_CPSW (11U)
229 
230 #define UDMA_RM_RES_ID_MAPPED_TX_SAUL_0 (12U)
231 
232 #define UDMA_RM_RES_ID_MAPPED_TX_SAUL_1 (13U)
233 
234 #define UDMA_RM_RES_ID_MAPPED_TX_ICSSG_0 (14U)
235 
236 #define UDMA_RM_RES_ID_MAPPED_TX_ICSSG_1 (15U)
237 
238 #define UDMA_RM_RES_ID_MAPPED_RX_CPSW (16U)
239 
240 #define UDMA_RM_RES_ID_MAPPED_RX_SAUL_0 (17U)
241 
242 #define UDMA_RM_RES_ID_MAPPED_RX_SAUL_1 (18U)
243 
244 #define UDMA_RM_RES_ID_MAPPED_RX_SAUL_2 (19U)
245 
246 #define UDMA_RM_RES_ID_MAPPED_RX_SAUL_3 (20U)
247 
248 #define UDMA_RM_RES_ID_MAPPED_RX_ICSSG_0 (21U)
249 
250 #define UDMA_RM_RES_ID_MAPPED_RX_ICSSG_1 (22U)
251 
252 #define UDMA_RM_RES_ID_MAPPED_TX_RING_CPSW (23U)
253 
254 #define UDMA_RM_RES_ID_MAPPED_TX_RING_SAUL_0 (24U)
255 
256 #define UDMA_RM_RES_ID_MAPPED_TX_RING_SAUL_1 (25U)
257 
258 #define UDMA_RM_RES_ID_MAPPED_TX_RING_ICSSG_0 (26U)
259 
260 #define UDMA_RM_RES_ID_MAPPED_TX_RING_ICSSG_1 (27U)
261 
262 #define UDMA_RM_RES_ID_MAPPED_RX_RING_CPSW (28U)
263 
264 #define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_0 (29U)
265 
266 #define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_1 (30U)
267 
268 #define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_2 (31U)
269 
270 #define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_3 (32U)
271 
272 #define UDMA_RM_RES_ID_MAPPED_RX_RING_ICSSG_0 (33U)
273 
274 #define UDMA_RM_RES_ID_MAPPED_RX_RING_ICSSG_1 (34U)
275 
276 #define UDMA_RM_NUM_BCDMA_RES (11U)
277 
278 #define UDMA_RM_NUM_PKTDMA_RES (35U)
279 
280 #define UDMA_RM_NUM_RES (35U)
281 
285 #define UDMA_RM_NUM_SHARED_RES (2U)
286 
288 #define UDMA_RM_SHARED_RES_MAX_INST (UDMA_NUM_CORE)
289 
291 #define UDMA_PSIL_DEST_THREAD_OFFSET (0x8000U)
292 
302 #define UDMA_PSIL_CH_CPSW2_RX (0x4500U)
303 #define UDMA_PSIL_CH_SAUL0_RX (0x4000U)
304 #define UDMA_PSIL_CH_ICSS_G0_RX (0x4100U)
305 #define UDMA_PSIL_CH_ICSS_G1_RX (0x4200U)
306 
307 #define UDMA_PSIL_CH_CPSW2_TX (UDMA_PSIL_CH_CPSW2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
308 #define UDMA_PSIL_CH_SAUL0_TX (UDMA_PSIL_CH_SAUL0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
309 #define UDMA_PSIL_CH_ICSS_G0_TX (UDMA_PSIL_CH_ICSS_G0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
310 #define UDMA_PSIL_CH_ICSS_G1_TX (UDMA_PSIL_CH_ICSS_G1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
311 
312 #define UDMA_PSIL_CH_CPSW2_TX_CNT (8U)
313 #define UDMA_PSIL_CH_SAUL0_TX_CNT (2U)
314 #define UDMA_PSIL_CH_ICSS_G0_TX_CNT (9U)
315 #define UDMA_PSIL_CH_ICSS_G1_TX_CNT (9U)
316 
317 #define UDMA_PSIL_CH_CPSW2_RX_CNT (1U)
318 #define UDMA_PSIL_CH_SAUL0_RX_CNT (4U)
319 #define UDMA_PSIL_CH_ICSS_G0_RX_CNT (5U)
320 #define UDMA_PSIL_CH_ICSS_G1_RX_CNT (5U)
321 
343 /*
344  * PDMA MAIN0 MCSPI RX Channels
345  */
346 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_RX (0x4300U + 0U)
347 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_RX (0x4300U + 1U)
348 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_RX (0x4300U + 2U)
349 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_RX (0x4300U + 3U)
350 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_RX (0x4300U + 4U)
351 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_RX (0x4300U + 5U)
352 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_RX (0x4300U + 6U)
353 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_RX (0x4300U + 7U)
354 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_RX (0x4300U + 8U)
355 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_RX (0x4300U + 9U)
356 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_RX (0x4300U + 10U)
357 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_RX (0x4300U + 11U)
358 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_RX (0x4300U + 12U)
359 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_RX (0x4300U + 13U)
360 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_RX (0x4300U + 14U)
361 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_RX (0x4300U + 15U)
362 /*
363  * PDMA MAIN0 UART RX Channels
364  */
365 #define UDMA_PDMA_CH_MAIN0_UART0_RX (0x4300U + 16U)
366 #define UDMA_PDMA_CH_MAIN0_UART1_RX (0x4300U + 17U)
367 
379 /*
380  * PDMA MAIN0 MCSPI TX Channels
381  */
382 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_TX (UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
383 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_TX (UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
384 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_TX (UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
385 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_TX (UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
386 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_TX (UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
387 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_TX (UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
388 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_TX (UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
389 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_TX (UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
390 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_TX (UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
391 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_TX (UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
392 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_TX (UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
393 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_TX (UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
394 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_TX (UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
395 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_TX (UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
396 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_TX (UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
397 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_TX (UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
398 /*
399  * PDMA MAIN0 UART TX Channels
400  */
401 #define UDMA_PDMA_CH_MAIN0_UART0_TX (UDMA_PDMA_CH_MAIN0_UART0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
402 #define UDMA_PDMA_CH_MAIN0_UART1_TX (UDMA_PDMA_CH_MAIN0_UART1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
403 
415 /*
416  * PDMA MAIN1 MCSPI RX Channels
417  */
418 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH0_RX (0x4400U + 0U)
419 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH1_RX (0x4400U + 1U)
420 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH2_RX (0x4400U + 2U)
421 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH3_RX (0x4400U + 3U)
422 /*
423  * PDMA MAIN1 UART RX Channels
424  */
425 #define UDMA_PDMA_CH_MAIN1_UART2_RX (0x4400U + 4U)
426 #define UDMA_PDMA_CH_MAIN1_UART3_RX (0x4400U + 5U)
427 #define UDMA_PDMA_CH_MAIN1_UART4_RX (0x4400U + 6U)
428 #define UDMA_PDMA_CH_MAIN1_UART5_RX (0x4400U + 7U)
429 #define UDMA_PDMA_CH_MAIN1_UART6_RX (0x4400U + 8U)
430 /*
431  * PDMA MAIN1 MCAN RX Channels
432  */
433 #define UDMA_PDMA_CH_MAIN1_MCAN0_CH0_RX (0x4400U + 9U)
434 #define UDMA_PDMA_CH_MAIN1_MCAN0_CH1_RX (0x4400U + 10U)
435 #define UDMA_PDMA_CH_MAIN1_MCAN0_CH2_RX (0x4400U + 11U)
436 #define UDMA_PDMA_CH_MAIN1_MCAN1_CH0_RX (0x4400U + 12U)
437 #define UDMA_PDMA_CH_MAIN1_MCAN1_CH1_RX (0x4400U + 13U)
438 #define UDMA_PDMA_CH_MAIN1_MCAN1_CH2_RX (0x4400U + 14U)
439 /*
440  * PDMA MAIN1 ADC RX Channels
441  */
442 #define UDMA_PDMA_CH_MAIN1_ADC0_CH0_RX (0x4400U + 15U)
443 #define UDMA_PDMA_CH_MAIN1_ADC0_CH1_RX (0x4400U + 16U)
444 
456 /*
457  * PDMA MAIN1 MCSPI TX Channels
458  */
459 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH0_TX (UDMA_PDMA_CH_MAIN1_MCSPI4_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
460 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH1_TX (UDMA_PDMA_CH_MAIN1_MCSPI4_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
461 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH2_TX (UDMA_PDMA_CH_MAIN1_MCSPI4_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
462 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH3_TX (UDMA_PDMA_CH_MAIN1_MCSPI4_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
463 /*
464  * PDMA MAIN1 UART TX Channels
465  */
466 #define UDMA_PDMA_CH_MAIN1_UART2_TX (UDMA_PDMA_CH_MAIN1_UART2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
467 #define UDMA_PDMA_CH_MAIN1_UART3_TX (UDMA_PDMA_CH_MAIN1_UART3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
468 #define UDMA_PDMA_CH_MAIN1_UART4_TX (UDMA_PDMA_CH_MAIN1_UART4_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
469 #define UDMA_PDMA_CH_MAIN1_UART5_TX (UDMA_PDMA_CH_MAIN1_UART5_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
470 #define UDMA_PDMA_CH_MAIN1_UART6_TX (UDMA_PDMA_CH_MAIN1_UART6_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
471 /*
472  * PDMA MAIN1 MCAN TX Channels
473  */
474 #define UDMA_PDMA_CH_MAIN1_MCAN0_CH0_TX (UDMA_PDMA_CH_MAIN1_MCAN0_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
475 #define UDMA_PDMA_CH_MAIN1_MCAN0_CH1_TX (UDMA_PDMA_CH_MAIN1_MCAN0_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
476 #define UDMA_PDMA_CH_MAIN1_MCAN0_CH2_TX (UDMA_PDMA_CH_MAIN1_MCAN0_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
477 #define UDMA_PDMA_CH_MAIN1_MCAN1_CH0_TX (UDMA_PDMA_CH_MAIN1_MCAN1_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
478 #define UDMA_PDMA_CH_MAIN1_MCAN1_CH1_TX (UDMA_PDMA_CH_MAIN1_MCAN1_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
479 #define UDMA_PDMA_CH_MAIN1_MCAN1_CH2_TX (UDMA_PDMA_CH_MAIN1_MCAN1_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
480 
484 /* ========================================================================== */
485 /* Structure Declarations */
486 /* ========================================================================== */
487 
488 /* None */
489 
490 /* ========================================================================== */
491 /* Function Declarations */
492 /* ========================================================================== */
493 
499 uint32_t Udma_isCacheCoherent(void);
500 
501 /* ========================================================================== */
502 /* Static Function Definitions */
503 /* ========================================================================== */
504 
505 /* None */
506 
507 #ifdef __cplusplus
508 }
509 #endif
510 
511 #endif /* #ifndef UDMA_SOC_H_ */
Udma_isCacheCoherent
uint32_t Udma_isCacheCoherent(void)
Returns TRUE if the memory is cache coherent.