AM64x MCU+ SDK  10.00.00
tisci_procboot.h
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1 /*
2  * Copyright (C) 2018-2024 Texas Instruments Incorporated
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  *
8  * Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  *
11  * Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the
14  * distribution.
15  *
16  * Neither the name of Texas Instruments Incorporated nor the names of
17  * its contributors may be used to endorse or promote products derived
18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  *
32  */
54 #ifndef TISCI_PROCBOOT_H_
55 #define TISCI_PROCBOOT_H_
56 
57 #ifdef __cplusplus
58 extern "C"
59 {
60 #endif
61 
62 
63 
76  struct tisci_header hdr;
77  uint8_t processor_id;
78 } __attribute__((__packed__));
79 
95  struct tisci_header hdr;
96 } __attribute__((__packed__));
97 
108  struct tisci_header hdr;
109  uint8_t processor_id;
110 } __attribute__((__packed__));
111 
126  struct tisci_header hdr;
127 } __attribute__((__packed__));
128 
141  struct tisci_header hdr;
142  uint8_t processor_id;
143  uint8_t host_id;
144 } __attribute__((__packed__));
145 
161  struct tisci_header hdr;
162 } __attribute__((__packed__));
163 
164 /* A53 Config Flags */
165 
167 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_ARMV8_DBG_EN (0x00000001U)
168 
169 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_ARMV8_DBG_NIDEN (0x00000002U)
170 
171 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_ARMV8_DBG_SPIDEN (0x00000004U)
172 
173 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_ARMV8_DBG_SPNIDEN (0x00000008U)
174 
175 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_ARMV8_AARCH32 (0x00000100U)
176 
177 /* R5 Config Flags */
178 
180 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_DBG_EN (0x00000001U)
181 
182 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_DBG_NIDEN (0x00000002U)
183 
184 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_LOCKSTEP (0x00000100U)
185 
186 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_TEINIT (0x00000200U)
187 
188 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_NMFI_EN (0x00000400U)
189 
190 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE (0x00000800U)
191 
192 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_BTCM_EN (0x00001000U)
193 
194 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_ATCM_EN (0x00002000U)
195 
196 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS (0x00004000U)
197 
199 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE (0x00008000U)
200 
201 /* C7x Config Flags */
202 
203 /* L2_PIPELINE_LATENCY_VALUE */
205 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_MASK (0x0000000FU)
206 
207 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_SHIFT (0x00000000U)
208 
209 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_1 (0x00000001U)
210 
211 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_2 (0x00000002U)
212 
213 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_3 (0x00000003U)
214 
215 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_4 (0x00000004U)
216 
217 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_5 (0x00000005U)
218 
219 /* L2_ACCESS_LATENCY_VALUE */
221 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2AL_MASK (0x000000F0U)
222 
223 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2AL_SHIFT (0x00000004U)
224 
225 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2AL_2 (0x00000020U)
226 
227 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2AL_3 (0x00000030U)
228 
229 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2AL_4 (0x00000040U)
230 
231 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2AL_5 (0x00000050U)
232 
233 /* C6x Config Flags */
234 
235 /* SSCLK_MODE_DIV_CLK_MODE_VALUE values
236  *
237  * NOTE: Values are 1 more than actual programmed values to avoid '0' as a
238  * valid value that we pass via flags.
239  */
241 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C6X_SSCLKMV_MASK (0x00000007U)
242 
243 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C6X_SSCLKMV_SHIFT (0x00000000U)
244 
245 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C6X_SSCLKMV_DIV2 (0x00000001U)
246 
247 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C6X_SSCLKMV_DIV3 (0x00000002U)
248 
249 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C6X_SSCLKMV_DIV4 (0x00000003U)
250 
251 /* M4F Config Flags */
252 
254 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_M4F_DBG_EN (0x00000001U)
255 
256 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_M4F_DBG_NIDEN (0x00000002U)
257 
258 #define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_HSM_DBG_EN (0x00000004U)
259 
272  struct tisci_header hdr;
273  uint8_t processor_id;
274  uint32_t bootvector_lo;
275  uint32_t bootvector_hi;
278 } __attribute__((__packed__));
279 
294  struct tisci_header hdr;
295 } __attribute__((__packed__));
296 
297 /* ARMV8 Control Flags */
298 
300 #define TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_ARMV8_ACINACTM (0x00000001U)
301 
302 #define TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_ARMV8_AINACTS (0x00000002U)
303 
304 #define TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_ARMV8_L2FLUSHREQ (0x00000100U)
305 
306 /* R5 Control Flags */
307 
309 #define TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT (0x00000001U)
310 
311 #define TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_LPSC (0x00000002U)
312 
313 #define TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_RESET (0x00000004U)
314 
315 /* M4 Control Flags */
316 
318 #define TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_HSM_M4_RESET (0x00000001U)
319 
330  struct tisci_header hdr;
331  uint8_t processor_id;
334 } __attribute__((__packed__));
335 
350  struct tisci_header hdr;
351 } __attribute__((__packed__));
352 
360  struct tisci_header hdr;
363 } __attribute__((__packed__));
364 
383  struct tisci_header hdr;
386  uint32_t image_size;
387 } __attribute__((__packed__));
388 
396  struct tisci_header hdr;
397  uint8_t processor_id;
398 } __attribute__((__packed__));
399 
400 /* ARMV8 Status Flags */
401 
403 #define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_ARMV8_WFE (0x00000001U)
404 
405 #define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_ARMV8_WFI (0x00000002U)
406 
407 #define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_ARMV8_L2F_DONE (0x00000010U)
408 
409 #define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_ARMV8_STANDBYWFIL2 (0x00000020U)
410 
411 /* R5 Status Flags */
412 
414 #define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_WFE (0x00000001U)
415 
416 #define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_WFI (0x00000002U)
417 
418 #define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_CLK_GATED (0x00000004U)
419 
420 #define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED (0x00000100U)
421 
422 #define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_SINGLECORE_ONLY (0x00000200U)
423 
424 /* C7x Status Flags */
425 
427 #define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_C7X_WFE (0x00000001U)
428 
429 #define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_C7X_WFI (0x00000002U)
430 
431 /* M4F Status Flags */
432 
434 #define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_M4F_WFI (0x00000002U)
435 
456  struct tisci_header hdr;
457  uint8_t processor_id;
458  uint32_t bootvector_lo;
459  uint32_t bootvector_hi;
460  uint32_t config_flags_1;
461  uint32_t control_flags_1;
462  uint32_t status_flags_1;
463 } __attribute__((__packed__));
464 
494  struct tisci_header hdr;
495  uint8_t processor_id;
504 } __attribute__((__packed__));
505 
518  struct tisci_header hdr;
519 } __attribute__((__packed__));
520 
521 
522 #ifdef __cplusplus
523 }
524 #endif
525 
526 #endif /* TISCI_SECURITY_H_ */
527 
tisci_msg_proc_request_resp::hdr
struct tisci_header hdr
Definition: tisci_procboot.h:95
tisci_msg_proc_set_config_req::bootvector_hi
uint32_t bootvector_hi
Definition: tisci_procboot.h:275
tisci_msg_proc_status_wait_req
Processor Status Wait.
Definition: tisci_procboot.h:493
tisci_msg_proc_release_resp
Release physical processor control response.
Definition: tisci_procboot.h:125
tisci_msg_proc_status_wait_resp
Processor Status Wait Response.
Definition: tisci_procboot.h:517
tisci_msg_proc_status_wait_req::delay_before_iteration_loop_start_us
uint8_t delay_before_iteration_loop_start_us
Definition: tisci_procboot.h:499
tisci_msg_proc_get_status_resp::hdr
struct tisci_header hdr
Definition: tisci_procboot.h:456
tisci_msg_proc_release_resp::hdr
struct tisci_header hdr
Definition: tisci_procboot.h:126
tisci_msg_proc_handover_req::processor_id
uint8_t processor_id
Definition: tisci_procboot.h:142
tisci_msg_proc_auth_boot_resp
Response to authenticate and start image request.
Definition: tisci_procboot.h:382
tisci_msg_proc_status_wait_req::processor_id
uint8_t processor_id
Definition: tisci_procboot.h:495
tisci_msg_proc_status_wait_req::status_flags_1_set_any_wait
uint32_t status_flags_1_set_any_wait
Definition: tisci_procboot.h:501
tisci_msg_proc_set_control_req::control_flags_1_set
uint32_t control_flags_1_set
Definition: tisci_procboot.h:332
tisci_msg_proc_release_req
Release physical processor control request.
Definition: tisci_procboot.h:107
__attribute__
struct tisci_msg_proc_request_req __attribute__((__packed__))
tisci_msg_proc_status_wait_req::hdr
struct tisci_header hdr
Definition: tisci_procboot.h:494
tisci_msg_proc_get_status_resp::bootvector_hi
uint32_t bootvector_hi
Definition: tisci_procboot.h:459
tisci_msg_proc_get_status_resp::config_flags_1
uint32_t config_flags_1
Definition: tisci_procboot.h:460
tisci_msg_proc_auth_boot_req::hdr
struct tisci_header hdr
Definition: tisci_procboot.h:360
tisci_msg_proc_set_control_req::processor_id
uint8_t processor_id
Definition: tisci_procboot.h:331
tisci_msg_proc_release_req::processor_id
uint8_t processor_id
Definition: tisci_procboot.h:109
tisci_msg_proc_set_config_req::bootvector_lo
uint32_t bootvector_lo
Definition: tisci_procboot.h:274
tisci_msg_proc_get_status_req
Processor Status request.
Definition: tisci_procboot.h:395
tisci_msg_proc_get_status_resp::control_flags_1
uint32_t control_flags_1
Definition: tisci_procboot.h:461
tisci_msg_proc_auth_boot_resp::image_address_hi
uint32_t image_address_hi
Definition: tisci_procboot.h:385
tisci_header
Header that prefixes all TISCI messages.
Definition: tisci_protocol.h:94
tisci_msg_proc_set_control_resp
Response to optional processor specific message for sequence control.
Definition: tisci_procboot.h:349
tisci_msg_proc_auth_boot_req::certificate_address_hi
uint32_t certificate_address_hi
Definition: tisci_procboot.h:362
tisci_msg_proc_set_config_req::config_flags_1_clear
uint32_t config_flags_1_clear
Definition: tisci_procboot.h:277
tisci_msg_proc_request_req::hdr
struct tisci_header hdr
Definition: tisci_procboot.h:76
tisci_msg_proc_get_status_resp::status_flags_1
uint32_t status_flags_1
Definition: tisci_procboot.h:462
tisci_msg_proc_handover_req::host_id
uint8_t host_id
Definition: tisci_procboot.h:143
tisci_msg_proc_get_status_resp::processor_id
uint8_t processor_id
Definition: tisci_procboot.h:457
tisci_msg_proc_get_status_req::processor_id
uint8_t processor_id
Definition: tisci_procboot.h:397
tisci_msg_proc_handover_req::hdr
struct tisci_header hdr
Definition: tisci_procboot.h:141
tisci_msg_proc_get_status_resp
Processor Status Response.
Definition: tisci_procboot.h:455
tisci_msg_proc_get_status_resp::bootvector_lo
uint32_t bootvector_lo
Definition: tisci_procboot.h:458
tisci_msg_proc_request_resp
Request for physical processor control response.
Definition: tisci_procboot.h:94
tisci_msg_proc_request_req
This file contains:
Definition: tisci_procboot.h:75
tisci_msg_proc_set_config_req
Processor Boot Configuration.
Definition: tisci_procboot.h:271
tisci_msg_proc_status_wait_req::status_flags_1_set_all_wait
uint32_t status_flags_1_set_all_wait
Definition: tisci_procboot.h:500
tisci_msg_proc_handover_req
Request to handover control of a processor to another host if permitted.
Definition: tisci_procboot.h:140
tisci_msg_proc_set_config_req::config_flags_1_set
uint32_t config_flags_1_set
Definition: tisci_procboot.h:276
tisci_msg_proc_request_req::processor_id
uint8_t processor_id
Definition: tisci_procboot.h:77
tisci_msg_proc_auth_boot_req::certificate_address_lo
uint32_t certificate_address_lo
Definition: tisci_procboot.h:361
tisci_msg_proc_set_control_req
Optional processor specific message for sequence control.
Definition: tisci_procboot.h:329
tisci_msg_proc_auth_boot_resp::hdr
struct tisci_header hdr
Definition: tisci_procboot.h:383
tisci_msg_proc_handover_resp
Response to handover of control of a processor to another host if permitted.
Definition: tisci_procboot.h:160
tisci_msg_proc_status_wait_req::status_flags_1_clr_all_wait
uint32_t status_flags_1_clr_all_wait
Definition: tisci_procboot.h:502
tisci_msg_proc_auth_boot_req
Authenticate and start image.
Definition: tisci_procboot.h:359
tisci_msg_proc_auth_boot_resp::image_size
uint32_t image_size
Definition: tisci_procboot.h:386
tisci_msg_proc_set_control_req::control_flags_1_clear
uint32_t control_flags_1_clear
Definition: tisci_procboot.h:333
tisci_msg_proc_set_config_resp
Response to Processor Boot Configuration message.
Definition: tisci_procboot.h:293
tisci_msg_proc_set_config_resp::hdr
struct tisci_header hdr
Definition: tisci_procboot.h:294
tisci_msg_proc_handover_resp::hdr
struct tisci_header hdr
Definition: tisci_procboot.h:161
tisci_msg_proc_get_status_req::hdr
struct tisci_header hdr
Definition: tisci_procboot.h:396
tisci_msg_proc_set_control_req::hdr
struct tisci_header hdr
Definition: tisci_procboot.h:330
tisci_msg_proc_status_wait_req::status_flags_1_clr_any_wait
uint32_t status_flags_1_clr_any_wait
Definition: tisci_procboot.h:503
tisci_msg_proc_release_req::hdr
struct tisci_header hdr
Definition: tisci_procboot.h:108
tisci_msg_proc_set_config_req::processor_id
uint8_t processor_id
Definition: tisci_procboot.h:273
tisci_msg_proc_auth_boot_resp::image_address_lo
uint32_t image_address_lo
Definition: tisci_procboot.h:384
tisci_msg_proc_status_wait_req::delay_per_iteration_us
uint8_t delay_per_iteration_us
Definition: tisci_procboot.h:498
tisci_msg_proc_status_wait_req::num_wait_iterations
uint8_t num_wait_iterations
Definition: tisci_procboot.h:496
tisci_msg_proc_status_wait_resp::hdr
struct tisci_header hdr
Definition: tisci_procboot.h:518
tisci_msg_proc_set_control_resp::hdr
struct tisci_header hdr
Definition: tisci_procboot.h:350
tisci_msg_proc_set_config_req::hdr
struct tisci_header hdr
Definition: tisci_procboot.h:272
tisci_msg_proc_status_wait_req::num_match_iterations
uint8_t num_match_iterations
Definition: tisci_procboot.h:497