AM64x MCU+ SDK  10.00.00

Detailed Description

UDMA channel open parameters.

Data Fields

uint32_t chNum
 
uint32_t peerChNum
 
uint32_t mappedChGrp
 
void * appData
 
Udma_RingPrms fqRingPrms
 
Udma_RingPrms cqRingPrms
 
Udma_RingPrms tdCqRingPrms
 

Field Documentation

◆ chNum

uint32_t Udma_ChPrms::chNum

[IN] UDMAP channel to allocate.

Set to UDMA_DMA_CH_ANY if the channel to allocate and open could be any from the free pool. Set to the actual DMA channel when specific DMA channel need to be allocated. This channel number is relative to the channel type (TX, RX or External). The driver will internally calculate the respective offset to get the actual UDMAP channel number.

◆ peerChNum

uint32_t Udma_ChPrms::peerChNum

[IN] The peer channel to link the chNum using PSILCFG.

Incase of PDMA peripherals this represent the PDMA channel to which the UDMA channel should pair with. Refer Udma_PdmaCh macros.

Incase of other PSIL master peripherals this represent the thread ID to which the UDMA channel should pair with. Refer Udma_PsilCh macros.

Incase of Block copy channel type (UDMA_CH_TYPE_TR_BLK_COPY), set this to UDMA_DMA_CH_NA, as the corresponding RX channel (same index as TX channel) is assumed to be paired with and the driver internally sets this up. The UdmaChPrms_init API takes care of this.

◆ mappedChGrp

uint32_t Udma_ChPrms::mappedChGrp

[IN] The Mapped channel group to use when channel type is UDMA_CH_TYPE_TX_MAPPED or UDMA_CH_TYPE_RX_MAPPED. Refer Udma_MappedTxGrpSoc macro for details about mapped TX channel groups or Udma_MappedRxGrpSoc macro for details about mapped RX channel groups.

For other channel type set to UDMA_MAPPED_GROUP_INVALID

◆ appData

void* Udma_ChPrms::appData

[IN] Application/caller context pointer passed back in all the channel callback functions. This could be used by the caller to identify the channel for which the callback is called. This can be set to NULL, if not required by caller.

◆ fqRingPrms

Udma_RingPrms Udma_ChPrms::fqRingPrms

[IN] Free queue ring params where descriptors are queued

◆ cqRingPrms

Udma_RingPrms Udma_ChPrms::cqRingPrms

[IN] Completion queue ring params where descriptors are dequeued This is not used for AM64x kind of devices, but even if the application sets this it will be ignored. But its not required to be set.

◆ tdCqRingPrms

Udma_RingPrms Udma_ChPrms::tdCqRingPrms

[IN] Teardown completion queue ring params where teardown response and TR response incase of direct TR mode are received from UDMA This is not used for AM64x kind of devices, but even if the application sets this it will be ignored. But its not required to be set.