tisci_rm_ra.h

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/*
 *  Copyright (C) 2017-2022 Texas Instruments Incorporated
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */
#ifndef RM_TISCI_RA_H
#define RM_TISCI_RA_H
 
 
#define TISCI_MSG_VALUE_RM_RING_ADDR_LO_VALID  (1u << 0u)
 
#define TISCI_MSG_VALUE_RM_RING_ADDR_HI_VALID  (1u << 1u)
 
#define TISCI_MSG_VALUE_RM_RING_COUNT_VALID    (1u << 2u)
 
#define TISCI_MSG_VALUE_RM_RING_MODE_VALID     (1u << 3u)
 
#define TISCI_MSG_VALUE_RM_RING_SIZE_VALID     (1u << 4u)
 
#define TISCI_MSG_VALUE_RM_RING_ORDER_ID_VALID (1u << 5u)
 
#define TISCI_MSG_VALUE_RM_RING_VIRTID_VALID   (1u << 6u)
 
#define TISCI_MSG_VALUE_RM_RING_ASEL_VALID     (1U << 7U)
 
#define TISCI_MSG_VALUE_RM_RING_MODE_RING      (0x0u)
 
#define TISCI_MSG_VALUE_RM_RING_MODE_MESSAGE   (0x1u)
 
#define TISCI_MSG_VALUE_RM_RING_MODE_CREDENTIALS (0x2u)
 
#define TISCI_MSG_VALUE_RM_RING_MODE_QM        (0x3u)
 
#define TISCI_MSG_VALUE_RM_RING_SIZE_4B        (0x0u)
 
#define TISCI_MSG_VALUE_RM_RING_SIZE_8B        (0x1u)
 
#define TISCI_MSG_VALUE_RM_RING_SIZE_16B       (0x2u)
 
#define TISCI_MSG_VALUE_RM_RING_SIZE_32B       (0x3u)
 
#define TISCI_MSG_VALUE_RM_RING_SIZE_64B       (0x4u)
 
#define TISCI_MSG_VALUE_RM_RING_SIZE_128B      (0x5u)
 
#define TISCI_MSG_VALUE_RM_RING_SIZE_256B      (0x6u)
 
#define TISCI_MSG_VALUE_RM_MON_SOURCE_VALID    (1u << 0U)
 
#define TISCI_MSG_VALUE_RM_MON_MODE_VALID      (1u << 1U)
 
#define TISCI_MSG_VALUE_RM_MON_QUEUE_VALID     (1u << 2U)
 
#define TISCI_MSG_VALUE_RM_MON_DATA0_VAL_VALID (1u << 3U)
 
#define TISCI_MSG_VALUE_RM_MON_DATA1_VAL_VALID (1u << 4U)
 
#define TISCI_MSG_VALUE_RM_MON_SRC_ELEM_CNT        (0U)
 
#define TISCI_MSG_VALUE_RM_MON_SRC_HEAD_PKT_SIZE   (1U)
 
#define TISCI_MSG_VALUE_RM_MON_SRC_ACCUM_Q_SIZE    (2U)
 
#define TISCI_MSG_VALUE_RM_MON_MODE_DISABLED       (0U)
 
#define TISCI_MSG_VALUE_RM_MON_MODE_PUSH_POP       (1U)
 
#define TISCI_MSG_VALUE_RM_MON_MODE_THRESHOLD      (2U)
 
#define TISCI_MSG_VALUE_RM_MON_MODE_WATERMARK      (3U)
 
#define TISCI_MSG_VALUE_RM_MON_MODE_STARVATION     (4U)
 
struct tisci_msg_rm_ring_cfg_req {
    struct tisci_header    hdr;
    uint32_t            valid_params;
    uint16_t            nav_id;
    uint16_t            index;
    uint32_t            addr_lo;
    uint32_t            addr_hi;
    uint32_t            count;
    uint8_t            mode;
    uint8_t            size;
    uint8_t            order_id;
    uint16_t            virtid;
    uint8_t            asel;
} __attribute__((__packed__));
 
struct tisci_msg_rm_ring_cfg_resp {
    struct tisci_header hdr;
} __attribute__((__packed__));
 
struct tisci_msg_rm_ring_mon_cfg_req {
    struct tisci_header    hdr;
    uint32_t            valid_params;
    uint16_t            nav_id;
    uint16_t            index;
    uint8_t            source;
    uint8_t            mode;
    uint16_t            queue;
    uint32_t            data0_val;
    uint32_t            data1_val;
} __attribute__((__packed__));
 
struct tisci_msg_rm_ring_mon_cfg_resp {
    struct tisci_header hdr;
} __attribute__((__packed__));
 
#endif /* RM_TISCI_RA_H */