AM64x MCU+ SDK  08.02.00

Detailed Description

Configures a Navigator Subsystem UDMAP receive flow's size threshold fields.

Configures a Navigator Subsystem UDMAP receive flow's size threshold fields

The flow index must be assigned to the host defined in the TISCI header via the RM board configuration resource assignment range list.

It's the user's responsibility to make sure any receive channels using the flow are disabled when changing the receive flow configuration. Otherwise, unknown operation may occur.

Parameters
hdrStandard TISCI header
valid_paramsBitfield defining validity of rx flow configuration parameters. The rx flow configuration fields are not valid, and will not be used for flow configuration, if their corresponding valid bit is zero. Valid bit usage: 0 - Valid bit for tisci_msg_rm_udmap_flow_size_thresh_cfg_req::rx_size_thresh0 1 - Valid bit for tisci_msg_rm_udmap_flow_size_thresh_cfg_req::rx_size_thresh1 2 - Valid bit for tisci_msg_rm_udmap_flow_size_thresh_cfg_req::rx_size_thresh2 3 - Valid bit for tisci_msg_rm_udmap_flow_size_thresh_cfg_req::rx_fdq0_sz1_qnum 4 - Valid bit for tisci_msg_rm_udmap_flow_size_thresh_cfg_req::rx_fdq0_sz2_qnum 5 - Valid bit for tisci_msg_rm_udmap_flow_size_thresh_cfg_req::rx_fdq0_sz3_qnum 6 - Valid bit for tisci_msg_rm_udmap_flow_size_thresh_cfg_req::rx_size_thresh_en
nav_idSoC device ID of Navigator Subsystem from which the receive flow is allocated
flow_indexUDMAP receive flow index for optional configuration.
rx_size_thresh0UDMAP receive flow packet size threshold 0 configuration to be programmed into the rx_size_thresh0 field of the flow's RFLOW_RFF register. The value must be provided in 32-byte units due to a 5-bit left shift performed by the hardware prior to comparison to packet size. See the UDMAP section of the TRM for more information on this setting and the shift on comparison.

This field is only valid if TISCI_MSG_VALUE_RM_UDMAP_FLOW_SIZE_THRESH0_VALID is set in tisci_msg_rm_udmap_flow_size_thresh_cfg_req::valid_params.

Parameters
rx_size_thresh1UDMAP receive flow packet size threshold 1 configuration to be programmed into the rx_size_thresh1 field of the flow's RFLOW_RFF register. The value must be provided in 32-byte units due to a 5-bit left shift performed by the hardware prior to comparison to packet size. See the UDMAP section of the TRM for more information on this setting and the shift on comparison.

This field is only valid if TISCI_MSG_VALUE_RM_UDMAP_FLOW_SIZE_THRESH1_VALID is set in tisci_msg_rm_udmap_flow_size_thresh_cfg_req::valid_params.

Parameters
rx_size_thresh2UDMAP receive flow packet size threshold 2 configuration to be programmed into the rx_size_thresh2 field of the flow's RFLOW_RFG register. The value must be provided in 32-byte units due to a 5-bit left shift performed by the hardware prior to comparison to packet size. See the UDMAP section of the TRM for more information on this setting and the shift on comparison.

This field is only valid if TISCI_MSG_VALUE_RM_UDMAP_FLOW_SIZE_THRESH2_VALID is set in tisci_msg_rm_udmap_flow_size_thresh_cfg_req::valid_params.

Parameters
rx_fdq0_sz1_qnumUDMAP receive flow free descriptor queue for size threshold 1 configuration to be programmed into the rx_fdq0_sz1_qnum field of the flow's RFLOW_RFG register. See the UDMAP section of the TRM for more information on this setting. The specified free queue must be valid within the Navigator Subsystem and must be owned by the host, or a subordinate of the host, who owns the receive flow index and who is making the optional configuration request.

This field is only valid if TISCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ1_QNUM_VALID is set in tisci_msg_rm_udmap_flow_size_thresh_cfg_req::valid_params.

Parameters
rx_fdq0_sz2_qnumUDMAP receive flow free descriptor queue for size threshold 2 configuration to be programmed into the rx_fdq0_sz2_qnum field of the flow's RFLOW_RFH register. See the UDMAP section of the TRM for more information on this setting. The specified free queue must be valid within the Navigator Subsystem and must be owned by the host, or a subordinate of the host, who owns the receive flow index and who is making the optional configuration request.

This field is only valid if TISCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ2_QNUM_VALID is set in tisci_msg_rm_udmap_flow_size_thresh_cfg_req::valid_params.

Parameters
rx_fdq0_sz3_qnumUDMAP receive flow free descriptor queue for size threshold 3 configuration to be programmed into the rx_fdq0_sz3_qnum field of the flow's RFLOW_RFH register. See the UDMAP section of the TRM for more information on this setting. The specified free queue must be valid within the Navigator Subsystem and must be owned by the host, or a subordinate of the host, who owns the receive flow index and who is making the optional configuration request.

This field is only valid if TISCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ3_QNUM_VALID is set in tisci_msg_rm_udmap_flow_size_thresh_cfg_req::valid_params.

Parameters
rx_size_thresh_enUDMAP receive flow packet size based free buffer queue enable configuration to be programmed into the rx_size_thresh_en field of the RFLOW_RFC register. See the UDMAP section of the TRM for more information on this setting. This parameter can be no greater than TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_SIZE_THRESH_MAX

This field is only valid if TISCI_MSG_VALUE_RM_UDMAP_FLOW_SIZE_THRESH_EN_VALID is set in tisci_msg_rm_udmap_flow_size_thresh_cfg_req::valid_params.

Data Fields

struct tisci_header hdr
 
uint32_t valid_params
 
uint16_t nav_id
 
uint16_t flow_index
 
uint16_t rx_size_thresh0
 
uint16_t rx_size_thresh1
 
uint16_t rx_size_thresh2
 
uint16_t rx_fdq0_sz1_qnum
 
uint16_t rx_fdq0_sz2_qnum
 
uint16_t rx_fdq0_sz3_qnum
 
uint8_t rx_size_thresh_en
 

Field Documentation

◆ hdr

struct tisci_header tisci_msg_rm_udmap_flow_size_thresh_cfg_req::hdr

◆ valid_params

uint32_t tisci_msg_rm_udmap_flow_size_thresh_cfg_req::valid_params

◆ nav_id

uint16_t tisci_msg_rm_udmap_flow_size_thresh_cfg_req::nav_id

◆ flow_index

uint16_t tisci_msg_rm_udmap_flow_size_thresh_cfg_req::flow_index

◆ rx_size_thresh0

uint16_t tisci_msg_rm_udmap_flow_size_thresh_cfg_req::rx_size_thresh0

◆ rx_size_thresh1

uint16_t tisci_msg_rm_udmap_flow_size_thresh_cfg_req::rx_size_thresh1

◆ rx_size_thresh2

uint16_t tisci_msg_rm_udmap_flow_size_thresh_cfg_req::rx_size_thresh2

◆ rx_fdq0_sz1_qnum

uint16_t tisci_msg_rm_udmap_flow_size_thresh_cfg_req::rx_fdq0_sz1_qnum

◆ rx_fdq0_sz2_qnum

uint16_t tisci_msg_rm_udmap_flow_size_thresh_cfg_req::rx_fdq0_sz2_qnum

◆ rx_fdq0_sz3_qnum

uint16_t tisci_msg_rm_udmap_flow_size_thresh_cfg_req::rx_fdq0_sz3_qnum

◆ rx_size_thresh_en

uint8_t tisci_msg_rm_udmap_flow_size_thresh_cfg_req::rx_size_thresh_en