tisci_msg_rm_irq_release_req Struct Reference

Detailed Description

Releases interrupt peripheral resources according to the valid configuration provided. The following tisci_msg_rm_irq_release_req::valid_params valid bit combinations are allowed: Interrupt Router Mux Release - Release an IR input to output mux connection where the IR input is the src_index and the IR output is the dst_host_irq. Both the src_id and the dst_id must be the device ID of the IR being configured. tisci_msg_rm_irq_release_req::dst_id valid bit == STRUE tisci_msg_rm_irq_release_req::dst_host_irq valid bit == STRUE tisci_msg_rm_irq_release_req::ia_id valid bit == SFALSE tisci_msg_rm_irq_release_req::vint valid bit == SFALSE tisci_msg_rm_irq_release_req::global_event valid bit == SFALSE tisci_msg_rm_irq_release_req::vint_status_bit_index valid bit == SFALSE Event to VINT Unmap Only - Clear only peripheral OES register and event to VINT status bit mapping tisci_msg_rm_irq_release_req::dst_id valid bit == SFALSE tisci_msg_rm_irq_release_req::dst_host_irq valid bit == SFALSE tisci_msg_rm_irq_release_req::ia_id valid bit == STRUE tisci_msg_rm_irq_release_req::vint valid bit == STRUE tisci_msg_rm_irq_release_req::global_event valid bit == STRUE tisci_msg_rm_irq_release_req::vint_status_bit_index valid bit == STRUE OES Register Programming Only - Only clears the OES register of the source. Useful for clearing UDMAP trigger events and any other events that are not translated to the interrupt domain: tisci_msg_rm_irq_release_req::dst_id valid bit == SFALSE tisci_msg_rm_irq_release_req::dst_host_irq valid bit == SFALSE tisci_msg_rm_irq_release_req::ia_id valid bit == SFALSE tisci_msg_rm_irq_release_req::vint valid bit == SFALSE tisci_msg_rm_irq_release_req::global_event valid bit == STRUE tisci_msg_rm_irq_release_req::vint_status_bit_index valid bit == SFALSE.

Parameters

hdr	Standard TISCI header
valid_params	Bitfield defining validity of interrupt route release parameters. The interrupt route release fields are not valid, and will not be used for route release, if their corresponding valid bit is zero. Valid bit usage: 0 - Valid bit for tisci_msg_rm_irq_release_req::dst_id 1 - Valid bit for tisci_msg_rm_irq_release_req::dst_host_irq 2 - Valid bit for tisci_msg_rm_irq_release_req::ia_id 3 - Valid bit for tisci_msg_rm_irq_release_req::vint 4 - Valid bit for tisci_msg_rm_irq_release_req::global_event 5 - Valid bit for tisci_msg_rm_irq_release_req::vint_status_bit_index 31 - Valid bit for tisci_msg_rm_irq_release_req::secondary_host
src_id	ID of interrupt source peripheral
src_index	Interrupt source index within source peripheral
dst_id	SoC IR device ID when the valid_params bits are set to release an IR mux connection. This field is only valid if TISCI_MSG_VALUE_RM_DST_ID_VALID is set in tisci_msg_rm_irq_release_req::valid_params.
dst_host_irq	SoC IR output index when the valid_params are set to release an IR mux connection. This field is only valid if TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID is set in tisci_msg_rm_irq_release_req::valid_params.
ia_id	Device ID of interrupt aggregator in which the virtual interrupt resides. This field is only valid if TISCI_MSG_VALUE_RM_IA_ID_VALID is set in tisci_msg_rm_irq_release_req::valid_params.
vint	Virtual interrupt number if the interrupt route is through an interrupt aggregator. This field is only valid if TISCI_MSG_VALUE_RM_VINT_VALID is set in tisci_msg_rm_irq_release_req::valid_params.
global_event	Global event mapped to interrupt aggregator virtual interrupt status bit. The event is cleared from the OES register of the interrupt source. This field is only applicable for interrupt source's capable of generating global events. This field is only valid if TISCI_MSG_VALUE_RM_GLOBAL_EVENT_VALID is set in tisci_msg_rm_irq_release_req::valid_params.
vint_status_bit_index	Virtual interrupt status bit to release if the interrupt route utilizes an interrupt aggregator virtual interrupt. This field is only valid if TISCI_MSG_VALUE_RM_VINT_STATUS_BIT_INDEX_VALID is set in tisci_msg_rm_irq_release_req::valid_params.
secondary_host	The interrupt route destination is the specified secondary host if the secondary_host's corresponding valid bit is set in tisci_msg_rm_irq_release_req::valid_params. Otherwise, the host within the TISCI message header is the route destination.

Data Fields
struct tisci_header	hdr
uint32_t	valid_params
uint16_t	src_id
uint16_t	src_index
uint16_t	dst_id
uint16_t	dst_host_irq
uint16_t	ia_id
uint16_t	vint
uint16_t	global_event
uint8_t	vint_status_bit_index
uint8_t	secondary_host

Field Documentation

hdr

struct tisci_header tisci_msg_rm_irq_release_req::hdr

valid_params

uint32_t tisci_msg_rm_irq_release_req::valid_params

src_id

uint16_t tisci_msg_rm_irq_release_req::src_id

src_index

uint16_t tisci_msg_rm_irq_release_req::src_index

dst_id

uint16_t tisci_msg_rm_irq_release_req::dst_id

dst_host_irq

uint16_t tisci_msg_rm_irq_release_req::dst_host_irq

ia_id

uint16_t tisci_msg_rm_irq_release_req::ia_id

vint

uint16_t tisci_msg_rm_irq_release_req::vint

global_event

uint16_t tisci_msg_rm_irq_release_req::global_event

vint_status_bit_index

uint8_t tisci_msg_rm_irq_release_req::vint_status_bit_index

secondary_host

uint8_t tisci_msg_rm_irq_release_req::secondary_host