Introduction

DMSC controls the power management, security and resource management of the device.

Data Structures
struct	tisci_msg_proc_request_req
	This file contains: More...

struct	tisci_msg_proc_request_resp
	Request for physical processor control response. More...

struct	tisci_msg_proc_release_req
	Release physical processor control request. More...

struct	tisci_msg_proc_release_resp
	Release physical processor control response. More...

struct	tisci_msg_proc_handover_req
	Request to handover control of a processor to another host if permitted. More...

struct	tisci_msg_proc_handover_resp
	Response to handover of control of a processor to another host if permitted. More...

struct	tisci_msg_proc_set_config_req
	Processor Boot Configuration. More...

struct	tisci_msg_proc_set_config_resp
	Response to Processor Boot Configuration message. More...

struct	tisci_msg_proc_set_control_req
	Optional processor specific message for sequence control. More...

struct	tisci_msg_proc_set_control_resp
	Response to optional processor specific message for sequence control. More...

struct	tisci_msg_proc_auth_boot_req
	Authenticate and start image. More...

struct	tisci_msg_proc_auth_boot_resp
	Response to authenticate and start image request. More...

struct	tisci_msg_proc_get_status_req
	Processor Status request. More...

struct	tisci_msg_proc_get_status_resp
	Processor Status Response. More...

struct	tisci_msg_proc_status_wait_req
	Processor Status Wait. More...

struct	tisci_msg_proc_status_wait_resp
	Processor Status Wait Response. More...

Functions
struct tisci_msg_proc_request_req	__attribute__ ((__packed__))

Macros
#define	TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_ARMV8_DBG_EN (0x00000001U)

#define	TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_ARMV8_DBG_NIDEN (0x00000002U)

#define	TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_ARMV8_DBG_SPIDEN (0x00000004U)

#define	TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_ARMV8_DBG_SPNIDEN (0x00000008U)

#define	TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_ARMV8_AARCH32 (0x00000100U)

#define	TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_DBG_EN (0x00000001U)

#define	TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_DBG_NIDEN (0x00000002U)

#define	TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_LOCKSTEP (0x00000100U)

#define	TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_TEINIT (0x00000200U)

#define	TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_NMFI_EN (0x00000400U)

#define	TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE (0x00000800U)

#define	TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_BTCM_EN (0x00001000U)

#define	TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_ATCM_EN (0x00002000U)

#define	TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS (0x00004000U)

#define	TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE (0x00008000U)

#define	TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_MASK (0x0000000FU)

#define	TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_SHIFT (0x00000000U)

#define	TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_1 (0x00000001U)

#define	TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_2 (0x00000002U)

#define	TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_3 (0x00000003U)

#define	TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_4 (0x00000004U)

#define	TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_5 (0x00000005U)

#define	TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2AL_MASK (0x000000F0U)

#define	TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2AL_SHIFT (0x00000004U)

#define	TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2AL_2 (0x00000020U)

#define	TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2AL_3 (0x00000030U)

#define	TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2AL_4 (0x00000040U)

#define	TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2AL_5 (0x00000050U)

#define	TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C6X_SSCLKMV_MASK (0x00000007U)

#define	TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C6X_SSCLKMV_SHIFT (0x00000000U)

#define	TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C6X_SSCLKMV_DIV2 (0x00000001U)

#define	TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C6X_SSCLKMV_DIV3 (0x00000002U)

#define	TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C6X_SSCLKMV_DIV4 (0x00000003U)

#define	TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_M4F_DBG_EN (0x00000001U)

#define	TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_M4F_DBG_NIDEN (0x00000002U)

#define	TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_ARMV8_ACINACTM (0x00000001U)

#define	TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_ARMV8_AINACTS (0x00000002U)

#define	TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_ARMV8_L2FLUSHREQ (0x00000100U)

#define	TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT (0x00000001U)

#define	TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_LPSC (0x00000002U)

#define	TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_RESET (0x00000004U)

#define	TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_ARMV8_WFE (0x00000001U)

#define	TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_ARMV8_WFI (0x00000002U)

#define	TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_ARMV8_L2F_DONE (0x00000010U)

#define	TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_ARMV8_STANDBYWFIL2 (0x00000020U)

#define	TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_WFE (0x00000001U)

#define	TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_WFI (0x00000002U)

#define	TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_CLK_GATED (0x00000004U)

#define	TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED (0x00000100U)

#define	TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_SINGLECORE_ONLY (0x00000200U)

#define	TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_C7X_WFE (0x00000001U)

#define	TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_C7X_WFI (0x00000002U)

#define	TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_M4F_WFI (0x00000002U)

Macro Definition Documentation

◆ TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_ARMV8_DBG_EN

#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_ARMV8_DBG_EN (0x00000001U)

ARMV8 Invasive debug

◆ TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_ARMV8_DBG_NIDEN

#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_ARMV8_DBG_NIDEN (0x00000002U)

ARMV8 Non-Invasive debug

◆ TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_ARMV8_DBG_SPIDEN

#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_ARMV8_DBG_SPIDEN (0x00000004U)

ARMV8 Secure invasive Debug

◆ TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_ARMV8_DBG_SPNIDEN

#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_ARMV8_DBG_SPNIDEN (0x00000008U)

ARMV8 Secure Non-invasive Debug

◆ TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_ARMV8_AARCH32

#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_ARMV8_AARCH32 (0x00000100U)

ARMV8 AARCH32

◆ TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_DBG_EN

#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_DBG_EN (0x00000001U)

R5 Invasive debug

◆ TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_DBG_NIDEN

#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_DBG_NIDEN (0x00000002U)

R5 Non-Invasive debug

◆ TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_LOCKSTEP

#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_LOCKSTEP (0x00000100U)

R5 Lockstep

◆ TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_TEINIT

#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_TEINIT (0x00000200U)

R5 Exception handling state at reset

◆ TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_NMFI_EN

#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_NMFI_EN (0x00000400U)

R5 Enable Core Non-Maskable Fast Interrupts

◆ TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE

#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE (0x00000800U)

R5 Core A/BTCM Reset Base address Indicator

◆ TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_BTCM_EN

#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_BTCM_EN (0x00001000U)

R5 Enable Core BTCM RAM at reset

◆ TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_ATCM_EN

#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_ATCM_EN (0x00002000U)

R5 Enable Core ATCM RAM at reset

◆ TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS

#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS (0x00004000U)

R5 Disables SRAM initialization (TCM, etc) at reset

◆ TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE

#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE (0x00008000U)

R5 Single / Dual CPU Mode 0 = Both CPUs are enabled, 1 = CPU1 Core is disabled

◆ TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_MASK

#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_MASK (0x0000000FU)

L2_PIPELINE_LATENCY_VALUES shifted mask for config

◆ TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_SHIFT

#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_SHIFT (0x00000000U)

L2_PIPELINE_LATENCY_VALUES bit shift for config

◆ TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_1

#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_1 (0x00000001U)

L2_PIPELINE_LATENCY_VALUES Latency of 1

◆ TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_2

#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_2 (0x00000002U)

L2_PIPELINE_LATENCY_VALUES Latency of 2

◆ TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_3

#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_3 (0x00000003U)

L2_PIPELINE_LATENCY_VALUES Latency of 3

◆ TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_4

#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_4 (0x00000004U)

L2_PIPELINE_LATENCY_VALUES Latency of 4

◆ TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_5

#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2PL_5 (0x00000005U)

L2_PIPELINE_LATENCY_VALUES Latency of 5

◆ TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2AL_MASK

#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2AL_MASK (0x000000F0U)

L2_ACCESS_LATENCY_VALUE shifted mask for config

◆ TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2AL_SHIFT

#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2AL_SHIFT (0x00000004U)

L2_ACCESS_LATENCY_VALUE bit shift for config

◆ TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2AL_2

#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2AL_2 (0x00000020U)

L2_ACCESS_LATENCY_VALUE Latency of 2

◆ TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2AL_3

#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2AL_3 (0x00000030U)

L2_ACCESS_LATENCY_VALUE Latency of 3

◆ TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2AL_4

#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2AL_4 (0x00000040U)

L2_ACCESS_LATENCY_VALUE Latency of 4

◆ TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2AL_5

#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C7X_L2AL_5 (0x00000050U)

L2_ACCESS_LATENCY_VALUE Latency of 5

◆ TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C6X_SSCLKMV_MASK

#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C6X_SSCLKMV_MASK (0x00000007U)

SSCLK_MODE_DIV_CLK_MODE_VALUE shifted mask for config

◆ TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C6X_SSCLKMV_SHIFT

#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C6X_SSCLKMV_SHIFT (0x00000000U)

SSCLK_MODE_DIV_CLK_MODE_VALUE bit shift for config

◆ TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C6X_SSCLKMV_DIV2

#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C6X_SSCLKMV_DIV2 (0x00000001U)

SSCLK_MODE_DIV_CLK_MODE_VALUE Div2 clock mode.

◆ TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C6X_SSCLKMV_DIV3

#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C6X_SSCLKMV_DIV3 (0x00000002U)

SSCLK_MODE_DIV_CLK_MODE_VALUE Div3 clock mode.

◆ TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C6X_SSCLKMV_DIV4

#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_C6X_SSCLKMV_DIV4 (0x00000003U)

SSCLK_MODE_DIV_CLK_MODE_VALUE Div4 clock mode.

◆ TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_M4F_DBG_EN

#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_M4F_DBG_EN (0x00000001U)

M4F Invasive debug

◆ TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_M4F_DBG_NIDEN

#define TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_M4F_DBG_NIDEN (0x00000002U)

M4F Non-Invasive debug

◆ TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_ARMV8_ACINACTM

#define TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_ARMV8_ACINACTM (0x00000001U)

ARMV8 ACINACTM control: with the primary core of cluster

◆ TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_ARMV8_AINACTS

#define TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_ARMV8_AINACTS (0x00000002U)

ARMV8 AINACTS control: with primary core of cluster

◆ TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_ARMV8_L2FLUSHREQ

#define TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_ARMV8_L2FLUSHREQ (0x00000100U)

ARMV8 SoC L2FLUSHREQ control: with primary core of cluster

◆ TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT

#define TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_CORE_HALT (0x00000001U)

R5 Core Halt

◆ TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_LPSC

#define TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_LPSC (0x00000002U)

R5F Processor LPSC Control

◆ TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_RESET

#define TISCI_MSG_VAL_PROC_BOOT_CTRL_FLAG_R5_RESET (0x00000004U)

R5F Processor Reset Control

◆ TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_ARMV8_WFE

#define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_ARMV8_WFE (0x00000001U)

ARMV8 Set if the core is in WFE state

◆ TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_ARMV8_WFI

#define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_ARMV8_WFI (0x00000002U)

ARMV8 Set if the core is in WFI state

◆ TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_ARMV8_L2F_DONE

#define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_ARMV8_L2F_DONE (0x00000010U)

ARMV8 L2 Hardware Flush complete

◆ TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_ARMV8_STANDBYWFIL2

#define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_ARMV8_STANDBYWFIL2 (0x00000020U)

ARMV8 STANDBYWFIL2 WFI achieved

◆ TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_WFE

#define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_WFE (0x00000001U)

R5 Set if the core is in WFE state

◆ TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_WFI

#define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_WFI (0x00000002U)

R5 Set if the core is in WFI state

◆ TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_CLK_GATED

#define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_CLK_GATED (0x00000004U)

R5 Core Clock Stopped due to WFI or WFE state

◆ TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED

#define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED (0x00000100U)

R5 Is Lockstep configuration permitted

◆ TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_SINGLECORE_ONLY

#define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_SINGLECORE_ONLY (0x00000200U)

R5 Single Core configuration Only Efuse setting

◆ TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_C7X_WFE

#define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_C7X_WFE (0x00000001U)

C7x Set if the core is in WFE state

◆ TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_C7X_WFI

#define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_C7X_WFI (0x00000002U)

C7x Set if the core is in WFI state

◆ TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_M4F_WFI

#define TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_M4F_WFI (0x00000002U)

M4F Set if the core is in WFI state

Function Documentation

◆ attribute()

struct tisci_msg_proc_request_req __attribute__ ( (__packed__) )