AM64x MCU+ SDK  08.02.00
enetphy.h
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1 /*
2  * Copyright (c) Texas Instruments Incorporated 2020
3  *
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30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
61 #ifndef ENETPHY_H_
62 #define ENETPHY_H_
63 
64 /* ========================================================================== */
65 /* Include Files */
66 /* ========================================================================== */
67 
68 #include <stdint.h>
69 #include <stdbool.h>
70 
71 #ifdef __cplusplus
72 extern "C" {
73 #endif
74 
75 /* ========================================================================== */
76 /* Macros */
77 /* ========================================================================== */
78 
80 #define ENETPHY_IS_ADDR_VALID(addr) ((addr) <= 31U)
81 
83 #define ENETPHY_BIT(n) (1U << (n))
84 
86 #define ENETPHY_IS_BIT_SET(val, n) (((val) & ENETPHY_BIT(n)) != 0U)
87 
89 #define ENETPHY_ARRAYSIZE(x) (sizeof(x) / sizeof(x[0]))
90 
100 /* Ethernet PHY driver error codes are same as CSL's to maintain consistency */
101 
103 #define ENETPHY_SOK (CSL_PASS)
104 
106 #define ENETPHY_EFAIL (CSL_EFAIL)
107 
109 #define ENETPHY_EBADARGS (CSL_EBADARGS)
110 
112 #define ENETPHY_EINVALIDPARAMS (CSL_EINVALID_PARAMS)
113 
115 #define ENETPHY_ETIMEOUT (CSL_ETIMEOUT)
116 
118 #define ENETPHY_EALLOC (CSL_EALLOC)
119 
121 #define ENETPHY_EPERM (CSL_EALLOC - 4)
122 
124 #define ENETPHY_ENOTSUPPORTED (CSL_EALLOC - 5)
125 
138 #define ENETPHY_LINK_CAP_HD10 ENETPHY_BIT(1)
139 
141 #define ENETPHY_LINK_CAP_FD10 ENETPHY_BIT(2)
142 
144 #define ENETPHY_LINK_CAP_HD100 ENETPHY_BIT(3)
145 
147 #define ENETPHY_LINK_CAP_FD100 ENETPHY_BIT(4)
148 
150 #define ENETPHY_LINK_CAP_HD1000 ENETPHY_BIT(5)
151 
153 #define ENETPHY_LINK_CAP_FD1000 ENETPHY_BIT(6)
154 
156 #define ENETPHY_LINK_CAP_10 (ENETPHY_LINK_CAP_HD10 | \
157  ENETPHY_LINK_CAP_FD10)
158 
160 #define ENETPHY_LINK_CAP_100 (ENETPHY_LINK_CAP_HD100 | \
161  ENETPHY_LINK_CAP_FD100)
162 
164 #define ENETPHY_LINK_CAP_1000 (ENETPHY_LINK_CAP_HD1000 | \
165  ENETPHY_LINK_CAP_FD1000)
166 
168 #define ENETPHY_LINK_CAP_ALL (ENETPHY_LINK_CAP_HD10 | \
169  ENETPHY_LINK_CAP_FD10 | \
170  ENETPHY_LINK_CAP_HD100 | \
171  ENETPHY_LINK_CAP_FD100 | \
172  ENETPHY_LINK_CAP_HD1000 | \
173  ENETPHY_LINK_CAP_FD1000)
174 
178 #define ENETPHY_EXTENDED_CFG_SIZE_MAX (128U)
179 
181 #define ENETPHY_FSM_TICK_PERIOD_MS (100U)
182 
184 #define ENETPHY_INVALID_PHYADDR (~0U)
185 
186 /* ========================================================================== */
187 /* Structures and Enums */
188 /* ========================================================================== */
189 
193 typedef enum EnetPhy_Magic_e
194 {
196  ENETPHY_MAGIC = 0xCADACADAU,
197 
200 } EnetPhy_Magic;
201 
205 typedef enum EnetPhy_Mii_e
206 {
209 
212 
215 
218 
221 
224 } EnetPhy_Mii;
225 
229 typedef enum EnetPhy_Speed_e
230 {
233 
236 
239 
242 } EnetPhy_Speed;
243 
247 typedef enum EnetPhy_Duplexity_e
248 {
251 
254 
258 
262 typedef struct EnetPhy_Version_s
263 {
265  uint32_t oui;
266 
268  uint32_t model;
269 
271  uint32_t revision;
273 
277 typedef enum EnetPhy_LinkStatus_e
278 {
281 
284 
287 
291 
295 typedef struct EnetPhy_LinkCfg_s
296 {
299 
303 
307 typedef struct EnetPhy_FsmTimeoutCfg_s
308 {
311 
314 
317 
320 
323 
326 
328  uint32_t mdixTicks;
330 
334 typedef struct EnetPhy_Cfg_s
335 {
337  uint32_t phyGroup;
338 
340  uint32_t phyAddr;
341 
343  uint32_t nwayCaps;
344 
346  bool mdixEn;
347 
352 
355 
358 
361 
364 
367 
369  uint8_t extendedCfg[ENETPHY_EXTENDED_CFG_SIZE_MAX];
370 
372  uint32_t extendedCfgSize;
373 } EnetPhy_Cfg;
374 
378 typedef struct EnetPhy_Mdio_s
379 {
392  int32_t (*isAlive)(uint32_t phyAddr,
393  bool *isAlive,
394  void *arg);
395 
408  int32_t (*isLinked)(uint32_t phyAddr,
409  bool *isLinked,
410  void *arg);
411 
425  int32_t (*readC22)(uint32_t group,
426  uint8_t phyAddr,
427  uint32_t reg,
428  uint16_t *val,
429  void *arg);
430 
444  int32_t (*writeC22)(uint32_t group,
445  uint8_t phyAddr,
446  uint32_t reg,
447  uint16_t val,
448  void *arg);
449 
464  int32_t (*readC45)(uint32_t group,
465  uint8_t phyAddr,
466  uint8_t mmd,
467  uint16_t reg,
468  uint16_t *val,
469  void *arg);
470 
485  int32_t (*writeC45)(uint32_t group,
486  uint8_t phyAddr,
487  uint8_t mmd,
488  uint16_t reg,
489  uint16_t val,
490  void *arg);
491 } EnetPhy_Mdio;
492 
497 
501 typedef struct EnetPhy_Drv_s *EnetPhyDrv_Handle;
502 
506 typedef enum EnetPhy_FsmState_e
507 {
510 
513 
516 
519 
522 
525 
528 
531 
534 
538 
542 typedef struct EnetPhy_State_s
543 {
546 
549 
552 
555 
557  uint32_t timeout;
558 
560  uint32_t residenceTime;
561 
564 
567 
570 
573 
575  uint32_t linkCaps;
576 
578  uint32_t phyLinkCaps;
579 
582 
585 
588 } EnetPhy_State;
589 
593 typedef struct EnetPhy_Obj_s
594 {
597 
600 
603 
605  uint32_t macCaps;
606 
609 
612 
615 
617  uint32_t group;
618 
620  uint32_t addr;
621 
623  uint32_t reqLinkCaps;
624 
627 
630 
632  void *mdioArgs;
633 } EnetPhy_Obj;
634 
640 typedef struct EnetPhy_Obj_s *EnetPhy_Handle;
641 
642 /* ========================================================================== */
643 /* Global Variables Declarations */
644 /* ========================================================================== */
645 
646 /* None */
647 
648 /* ========================================================================== */
649 /* Function Declarations */
650 /* ========================================================================== */
651 
660 
671  const void *extendedCfg,
672  uint32_t extendedCfgSize);
673 
692  EnetPhy_Mii mii,
693  const EnetPhy_LinkCfg *linkCfg,
694  uint32_t macPortCaps,
695  EnetPhy_MdioHandle hMdio,
696  void *mdioArgs);
697 
706 
717 
730 
741 
755 
769  EnetPhy_LinkCfg *linkCfg);
770 
783  uint32_t reg,
784  uint16_t *val);
785 
798  uint32_t reg,
799  uint16_t val);
800 
814  uint32_t reg,
815  uint16_t mask,
816  uint16_t val);
817 
830  uint32_t reg,
831  uint16_t *val);
832 
845  uint32_t reg,
846  uint16_t val);
847 
861  uint32_t reg,
862  uint16_t mask,
863  uint16_t val);
864 
878  uint8_t mmd,
879  uint32_t reg,
880  uint16_t *val);
881 
895  uint8_t mmd,
896  uint32_t reg,
897  uint16_t val);
898 
913  uint8_t mmd,
914  uint32_t reg,
915  uint16_t mask,
916  uint16_t val);
917 
926 
927 /* ========================================================================== */
928 /* Deprecated Function Declarations */
929 /* ========================================================================== */
930 
931 /* None */
932 
933 /* ========================================================================== */
934 /* Static Function Definitions */
935 /* ========================================================================== */
936 
937 /* None */
938 
939 #ifdef __cplusplus
940 }
941 #endif
942 
943 #endif /* ENETPHY_H_ */
944 
EnetPhy_State::enableMdix
bool enableMdix
Definition: enetphy.h:587
EnetPhy_Obj::timeoutCfg
EnetPhy_FsmTimeoutCfg timeoutCfg
Definition: enetphy.h:611
EnetPhy_setExtendedCfg
void EnetPhy_setExtendedCfg(EnetPhy_Cfg *phyCfg, const void *extendedCfg, uint32_t extendedCfgSize)
Set PHY extended parameters.
EnetPhy_FsmTimeoutCfg::nwayStartStateTicks
uint32_t nwayStartStateTicks
NWAY_START state timeout (in ticks)
Definition: enetphy.h:319
EnetPhy_readExtReg
int32_t EnetPhy_readExtReg(EnetPhy_Handle hPhy, uint32_t reg, uint16_t *val)
Read PHY extended register.
EnetPhy_FsmTimeoutCfg::findingStateTicks
uint32_t findingStateTicks
FINDING state timeout (in ticks)
Definition: enetphy.h:310
EnetPhy_Cfg::extClkSource
bool extClkSource
Definition: enetphy.h:360
EnetPhy_Cfg::loopbackEn
bool loopbackEn
Definition: enetphy.h:354
EnetPhy_Obj::hMdio
EnetPhy_MdioHandle hMdio
Definition: enetphy.h:596
EnetPhy_Obj::addr
uint32_t addr
Definition: enetphy.h:620
EnetPhy_rmwC45Reg
int32_t EnetPhy_rmwC45Reg(EnetPhy_Handle hPhy, uint8_t mmd, uint32_t reg, uint16_t mask, uint16_t val)
Read-modify-write PHY register using Clause-45 frame.
EnetPhy_Cfg::timeoutCfg
EnetPhy_FsmTimeoutCfg timeoutCfg
Definition: enetphy.h:366
ENETPHY_SPEED_10MBIT
@ ENETPHY_SPEED_10MBIT
Definition: enetphy.h:232
EnetPhy_State::residenceTime
uint32_t residenceTime
Definition: enetphy.h:560
ENETPHY_FSM_STATE_FOUND
@ ENETPHY_FSM_STATE_FOUND
FOUND state.
Definition: enetphy.h:521
EnetPhy_Cfg::phyAddr
uint32_t phyAddr
Definition: enetphy.h:340
ENETPHY_FSM_STATE_NWAY_WAIT
@ ENETPHY_FSM_STATE_NWAY_WAIT
NWAY_WAIT state (auto-negotiation path)
Definition: enetphy.h:527
EnetPhy_State::speed
EnetPhy_Speed speed
Definition: enetphy.h:551
EnetPhy_getLinkCfg
int32_t EnetPhy_getLinkCfg(EnetPhy_Handle hPhy, EnetPhy_LinkCfg *linkCfg)
Get link configuration.
EnetPhy_readC45Reg
int32_t EnetPhy_readC45Reg(EnetPhy_Handle hPhy, uint8_t mmd, uint32_t reg, uint16_t *val)
Read PHY register using Clause-45 frame.
EnetPhy_rmwExtReg
int32_t EnetPhy_rmwExtReg(EnetPhy_Handle hPhy, uint32_t reg, uint16_t mask, uint16_t val)
Read-modify-write PHY extended register.
EnetPhyDrv_Handle
struct EnetPhy_Drv_s * EnetPhyDrv_Handle
PHY specific driver handle.
Definition: enetphy.h:501
EnetPhy_printRegs
void EnetPhy_printRegs(EnetPhy_Handle hPhy)
Print all PHY registers.
ENETPHY_FSM_STATE_LINK_WAIT
@ ENETPHY_FSM_STATE_LINK_WAIT
LINK_WAIT state.
Definition: enetphy.h:530
EnetPhy_Mii
EnetPhy_Mii
MAC Media-Independent Interface (MII).
Definition: enetphy.h:206
EnetPhy_Obj::hDrv
EnetPhyDrv_Handle hDrv
Definition: enetphy.h:626
ENETPHY_MAGIC
@ ENETPHY_MAGIC
Definition: enetphy.h:196
ENETPHY_LINK_DOWN
@ ENETPHY_LINK_DOWN
Definition: enetphy.h:289
ENETPHY_FSM_STATE_ENABLE
@ ENETPHY_FSM_STATE_ENABLE
ENABLE state.
Definition: enetphy.h:518
EnetPhy_State::linkCaps
uint32_t linkCaps
Definition: enetphy.h:575
ENETPHY_MAC_MII_RMII
@ ENETPHY_MAC_MII_RMII
RMII interface.
Definition: enetphy.h:211
ENETPHY_MAC_MII_GMII
@ ENETPHY_MAC_MII_GMII
GMII interface.
Definition: enetphy.h:214
EnetPhy_Cfg::skipExtendedCfg
bool skipExtendedCfg
Definition: enetphy.h:363
ENETPHY_SPEED_AUTO
@ ENETPHY_SPEED_AUTO
Definition: enetphy.h:241
EnetPhy_Version::revision
uint32_t revision
Definition: enetphy.h:271
EnetPhy_LinkCfg::duplexity
EnetPhy_Duplexity duplexity
Definition: enetphy.h:301
EnetPhy_State::needsManualCfg
bool needsManualCfg
Definition: enetphy.h:569
EnetPhy_readReg
int32_t EnetPhy_readReg(EnetPhy_Handle hPhy, uint32_t reg, uint16_t *val)
Read PHY register.
EnetPhy_Cfg
PHY configuration parameters.
Definition: enetphy.h:335
EnetPhy_FsmState
EnetPhy_FsmState
PHY driver state-machine states.
Definition: enetphy.h:507
EnetPhy_getId
int32_t EnetPhy_getId(EnetPhy_Handle hPhy, EnetPhy_Version *version)
Get PHY id.
ENETPHY_MAC_MII_MII
@ ENETPHY_MAC_MII_MII
MII interface.
Definition: enetphy.h:208
EnetPhy_isAlive
bool EnetPhy_isAlive(EnetPhy_Handle hPhy)
Get PHY alive status.
EnetPhy_FsmTimeoutCfg::mdixTicks
uint32_t mdixTicks
Timeout if MDIX is enabled (in ticks)
Definition: enetphy.h:328
ENETPHY_DUPLEX_HALF
@ ENETPHY_DUPLEX_HALF
Definition: enetphy.h:250
EnetPhy_State::needsMdixSwitch
bool needsMdixSwitch
Definition: enetphy.h:584
EnetPhy_Version
PHY version (ID).
Definition: enetphy.h:263
EnetPhy_FsmTimeoutCfg::resetWaitStateTicks
uint32_t resetWaitStateTicks
RESET_WAIT state timeout (in ticks)
Definition: enetphy.h:313
ENETPHY_DUPLEX_FULL
@ ENETPHY_DUPLEX_FULL
Definition: enetphy.h:253
EnetPhy_Obj::state
EnetPhy_State state
Definition: enetphy.h:614
EnetPhy_close
void EnetPhy_close(EnetPhy_Handle hPhy)
Close the PHY driver.
EnetPhy_Obj::linkCfg
EnetPhy_LinkCfg linkCfg
Definition: enetphy.h:608
ENETPHY_SPEED_1GBIT
@ ENETPHY_SPEED_1GBIT
Definition: enetphy.h:238
EnetPhy_MdioHandle
EnetPhy_Mdio * EnetPhy_MdioHandle
MDIO driver handle.
Definition: enetphy.h:496
ENETPHY_FSM_STATE_LOOPBACK
@ ENETPHY_FSM_STATE_LOOPBACK
LOOPBACK state.
Definition: enetphy.h:536
EnetPhy_open
EnetPhy_Handle EnetPhy_open(const EnetPhy_Cfg *phyCfg, EnetPhy_Mii mii, const EnetPhy_LinkCfg *linkCfg, uint32_t macPortCaps, EnetPhy_MdioHandle hMdio, void *mdioArgs)
Open the PHY driver.
EnetPhy_LinkCfg::speed
EnetPhy_Speed speed
Definition: enetphy.h:298
EnetPhy_FsmTimeoutCfg
PHY State-Machine time-out values.
Definition: enetphy.h:308
EnetPhy_Handle
struct EnetPhy_Obj_s * EnetPhy_Handle
PHY driver object handle.
Definition: enetphy.h:640
EnetPhy_isLinked
bool EnetPhy_isLinked(EnetPhy_Handle hPhy)
Get link status.
ENETPHY_LOST_LINK
@ ENETPHY_LOST_LINK
Definition: enetphy.h:286
EnetPhy_writeC45Reg
int32_t EnetPhy_writeC45Reg(EnetPhy_Handle hPhy, uint8_t mmd, uint32_t reg, uint16_t val)
Write PHY register using Clause-45 frame.
ENETPHY_NO_MAGIC
@ ENETPHY_NO_MAGIC
Definition: enetphy.h:199
ENETPHY_GOT_LINK
@ ENETPHY_GOT_LINK
Definition: enetphy.h:280
EnetPhy_Obj::magic
EnetPhy_Magic magic
Definition: enetphy.h:629
EnetPhy_Obj::mdioArgs
void * mdioArgs
Definition: enetphy.h:632
EnetPhy_Version::model
uint32_t model
Definition: enetphy.h:268
ENETPHY_FSM_STATE_NWAY_START
@ ENETPHY_FSM_STATE_NWAY_START
NWAY_START state (auto-negotiation path)
Definition: enetphy.h:524
EnetPhy_writeReg
int32_t EnetPhy_writeReg(EnetPhy_Handle hPhy, uint32_t reg, uint16_t val)
Write PHY register.
ENETPHY_DUPLEX_AUTO
@ ENETPHY_DUPLEX_AUTO
Definition: enetphy.h:256
EnetPhy_Obj::mii
EnetPhy_Mii mii
Definition: enetphy.h:602
ENETPHY_LINK_UP
@ ENETPHY_LINK_UP
Definition: enetphy.h:283
EnetPhy_State
PHY driver FSM state.
Definition: enetphy.h:543
EnetPhy_FsmTimeoutCfg::nwayWaitStateTicks
uint32_t nwayWaitStateTicks
NWAY_WAIT state timeout (in ticks)
Definition: enetphy.h:322
EnetPhy_FsmTimeoutCfg::resetWaitStateResidenceTicks
uint32_t resetWaitStateResidenceTicks
RESET_WAIT state residence time (in ticks)
Definition: enetphy.h:316
ENETPHY_SPEED_100MBIT
@ ENETPHY_SPEED_100MBIT
Definition: enetphy.h:235
ENETPHY_FSM_STATE_FINDING
@ ENETPHY_FSM_STATE_FINDING
FINDING state.
Definition: enetphy.h:512
ENETPHY_MAC_MII_SGMII
@ ENETPHY_MAC_MII_SGMII
SGMII interface.
Definition: enetphy.h:220
EnetPhy_Cfg::mdixEn
bool mdixEn
Definition: enetphy.h:346
EnetPhy_Cfg::extendedCfgSize
uint32_t extendedCfgSize
Definition: enetphy.h:372
EnetPhy_Cfg::masterMode
bool masterMode
Definition: enetphy.h:357
ENETPHY_FSM_STATE_INIT
@ ENETPHY_FSM_STATE_INIT
INIT state.
Definition: enetphy.h:509
EnetPhy_State::isNwayCapable
bool isNwayCapable
Definition: enetphy.h:563
ENETPHY_EXTENDED_CFG_SIZE_MAX
#define ENETPHY_EXTENDED_CFG_SIZE_MAX
Max extended configuration size, arbitrarily chosen.
Definition: enetphy.h:178
EnetPhy_State::needsNwayCfg
bool needsNwayCfg
Definition: enetphy.h:572
ENETPHY_MAC_MII_QSGMII
@ ENETPHY_MAC_MII_QSGMII
QSGMII interface.
Definition: enetphy.h:223
EnetPhy_Version::oui
uint32_t oui
Definition: enetphy.h:265
EnetPhy_LinkCfg
Link speed and duplexity configuration.
Definition: enetphy.h:296
EnetPhy_initCfg
void EnetPhy_initCfg(EnetPhy_Cfg *phyCfg)
Initialize PHY config params.
EnetPhy_State::fsmState
EnetPhy_FsmState fsmState
Definition: enetphy.h:545
EnetPhy_State::duplexity
EnetPhy_Duplexity duplexity
Definition: enetphy.h:554
EnetPhy_State::fsmStateChanged
bool fsmStateChanged
Definition: enetphy.h:548
EnetPhy_Cfg::nwayCaps
uint32_t nwayCaps
Definition: enetphy.h:343
EnetPhy_writeExtReg
int32_t EnetPhy_writeExtReg(EnetPhy_Handle hPhy, uint32_t reg, uint16_t val)
Write PHY extended register.
EnetPhy_FsmTimeoutCfg::linkWaitStateTicks
uint32_t linkWaitStateTicks
LINK_WAIT state timeout (in ticks)
Definition: enetphy.h:325
EnetPhy_Duplexity
EnetPhy_Duplexity
MAC interface duplexity.
Definition: enetphy.h:248
ENETPHY_MAC_MII_RGMII
@ ENETPHY_MAC_MII_RGMII
RGMII interface.
Definition: enetphy.h:217
EnetPhy_rmwReg
int32_t EnetPhy_rmwReg(EnetPhy_Handle hPhy, uint32_t reg, uint16_t mask, uint16_t val)
Read-modify-write PHY register.
EnetPhy_State::loopbackEn
bool loopbackEn
Definition: enetphy.h:581
EnetPhy_State::enableNway
bool enableNway
Definition: enetphy.h:566
EnetPhy_Obj
PHY driver object.
Definition: enetphy.h:594
EnetPhy_Obj::group
uint32_t group
Definition: enetphy.h:617
EnetPhy_Obj::macCaps
uint32_t macCaps
Definition: enetphy.h:605
EnetPhy_State::phyLinkCaps
uint32_t phyLinkCaps
Definition: enetphy.h:578
EnetPhy_Obj::reqLinkCaps
uint32_t reqLinkCaps
Definition: enetphy.h:623
EnetPhy_Cfg::phyGroup
uint32_t phyGroup
Definition: enetphy.h:337
EnetPhy_tick
EnetPhy_LinkStatus EnetPhy_tick(EnetPhy_Handle hPhy)
Run PHY state machine.
EnetPhy_Speed
EnetPhy_Speed
MAC interface speed.
Definition: enetphy.h:230
EnetPhy_Cfg::isStrapped
bool isStrapped
Definition: enetphy.h:351
EnetPhy_Mdio
MDIO driver.
Definition: enetphy.h:379
ENETPHY_FSM_STATE_RESET_WAIT
@ ENETPHY_FSM_STATE_RESET_WAIT
RESET_WAIT state.
Definition: enetphy.h:515
EnetPhy_Obj::phyCfg
EnetPhy_Cfg phyCfg
Definition: enetphy.h:599
ENETPHY_FSM_STATE_LINKED
@ ENETPHY_FSM_STATE_LINKED
LINKED state.
Definition: enetphy.h:533
EnetPhy_Magic
EnetPhy_Magic
EnetPhy driver magic value, used to indicate if driver is open or not.
Definition: enetphy.h:194
version
uint16_t version
Definition: tisci_core.h:2
EnetPhy_State::timeout
uint32_t timeout
Definition: enetphy.h:557
EnetPhy_LinkStatus
EnetPhy_LinkStatus
PHY link status.
Definition: enetphy.h:278