Introduction

EtherNet/IP Adapter FWHAL(Firmware and Hardware Abstraction Layer) APIs implement the key interface between EtherNet/IP firmware and slave stack.

Sub Modules
	DLR APIs

	EtherNet/IP FWHAL APIs

Data Structures
struct	clockClass_t
	Specifies the properties of a clock. More...

struct	descr_t
	Description in unicode. More...

struct	portProfileIdentity_t
	Specifies the PTP profile of each port of the device. More...

struct	portPhysAddr_t
	Specifies the physical protocol and physical address (e.g. IEEE 802.3) of each port of the device (e.g. MAC address). The maximum number of characters is 16. Unused array elements are zero-filled. More...

struct	portProtAddr_t
	Specifies the specifies the network and protocol address of each port of the device (e.g. IP address). The Network Protocol specifies the protocol for the network. More...

struct	sysTimeOffset_t
	Specifies the system time in microseconds and the Offset to the local clock value. More...

struct	cipSyncConfig_t
	CIP Sync configuration. Instance Attribute for PTP Class (Class Code 0x43. CIP Spec Vol 1) More...

struct	eip_Config

Typedefs
typedef struct eip_Config_s *	EIP_Handle

Enumerations
enum	clockType { ORDINARY_CLOCK = 0, TRANSPARENT_CLOCK = 1, BOUNDARY_CLOCK = 2 }
	Type of clock supported by PTP Implementation. This is not specified by standard. More...

Macros
#define	IEP_CMP_DEFAULT_VAL 0x11

#define	IEP_CMP4_DEFAULT_VAL 0x5000

#define	IEP_CMP0_DEFAULT_VAL 0xffffffff

#define	PRU_IEP_CMP_CFG_REG 0x40

#define	PRU_IEP_CMP0_REG 0x48

#define	EIP_TICK_PERIOD 1 /in milliseconds/

#define	LOOPBK_PKT_SEND_PERIOD 1000

#define	DEFAULT_BC_PKT_SIZE 60

#define	ONE_SECOND_INTERVAL 1000 /in milliseconds/

#define	TWO_MINUTE_INTERVAL 120000 /in milliseconds/

#define	CRS_STATUS_MASK 0x2

#define	CRS_STATUS_SHIFT 0x1

#define	PTP_PROT_TYPE 0x88F7

#define	DLR_MDIO_PHY0 1

#define	DLR_MDIO_PHY1 2

#define	PHYBMSR_OFFSET 0x1

#define	PHYSTS_OFFSET 0x10

#define	PHY_LINK_STATUS_MASK 0x4

#define	PHY_LINK_STATUS_SHIFT 0x2

Macro Definition Documentation

◆ IEP_CMP_DEFAULT_VAL

#define IEP_CMP_DEFAULT_VAL 0x11

◆ IEP_CMP4_DEFAULT_VAL

#define IEP_CMP4_DEFAULT_VAL 0x5000

◆ IEP_CMP0_DEFAULT_VAL

#define IEP_CMP0_DEFAULT_VAL 0xffffffff

◆ PRU_IEP_CMP_CFG_REG

#define PRU_IEP_CMP_CFG_REG 0x40

IEP Compare Register

◆ PRU_IEP_CMP0_REG

#define PRU_IEP_CMP0_REG 0x48

◆ EIP_TICK_PERIOD

#define EIP_TICK_PERIOD 1 /*in milliseconds*/

EIP Tick duration, used for DLR link detection as well as Half Duplex

◆ LOOPBK_PKT_SEND_PERIOD

#define LOOPBK_PKT_SEND_PERIOD 1000

◆ DEFAULT_BC_PKT_SIZE

#define DEFAULT_BC_PKT_SIZE 60

◆ ONE_SECOND_INTERVAL

#define ONE_SECOND_INTERVAL 1000 /*in milliseconds*/

◆ TWO_MINUTE_INTERVAL

#define TWO_MINUTE_INTERVAL 120000 /*in milliseconds*/

◆ CRS_STATUS_MASK

#define CRS_STATUS_MASK 0x2

Mask for carrier sense status on MII RT for Half Duplex

◆ CRS_STATUS_SHIFT

#define CRS_STATUS_SHIFT 0x1

Shift Val for carrier sense status on MII RT for Half Duplex

◆ PTP_PROT_TYPE

#define PTP_PROT_TYPE 0x88F7

PTP Protocol type

◆ DLR_MDIO_PHY0

#define DLR_MDIO_PHY0 1

◆ DLR_MDIO_PHY1

#define DLR_MDIO_PHY1 2

◆ PHYBMSR_OFFSET

#define PHYBMSR_OFFSET 0x1

◆ PHYSTS_OFFSET

#define PHYSTS_OFFSET 0x10

◆ PHY_LINK_STATUS_MASK

#define PHY_LINK_STATUS_MASK 0x4

◆ PHY_LINK_STATUS_SHIFT

#define PHY_LINK_STATUS_SHIFT 0x2

Typedef Documentation

◆ EIP_Handle

typedef struct eip_Config_s* EIP_Handle

Enumeration Type Documentation

◆ clockType

enum clockType

Type of clock supported by PTP Implementation. This is not specified by standard.

Enumerator
ORDINARY_CLOCK	Ordinary clock/End Node
TRANSPARENT_CLOCK	Transparent clock
BOUNDARY_CLOCK	Transparent clock