Detailed Description

LCD Configuration for Time Division Multiplexing.

Data Fields
uint32_t	tdmEnable

uint32_t	tdmUnusedBitsLevel

uint32_t	tdmCycleFormat

uint32_t	tdmParallelMode

uint32_t	numBitsPixel1Cycle0

uint32_t	numBitsPixel1Cycle1

uint32_t	numBitsPixel1Cycle2

uint32_t	bitAlignPixel1Cycle0

uint32_t	bitAlignPixel1Cycle1

uint32_t	bitAlignPixel1Cycle2

uint32_t	numBitsPixel2Cycle0

uint32_t	numBitsPixel2Cycle1

uint32_t	numBitsPixel2Cycle2

uint32_t	bitAlignPixel2Cycle0

uint32_t	bitAlignPixel2Cycle1

uint32_t	bitAlignPixel2Cycle2

Field Documentation

◆ tdmEnable

uint32_t CSL_DssVpLcdTdmCfg::tdmEnable

Enable the multiple cycle format for the VP output FALSE: Disable TDM TRUE: Enable TDM

◆ tdmUnusedBitsLevel

uint32_t CSL_DssVpLcdTdmCfg::tdmUnusedBitsLevel

State of unused bits (TDM mode only) for the VP output. For valid values see CSL_DssVpTdmUnusedBitsLevel

◆ tdmCycleFormat

uint32_t CSL_DssVpLcdTdmCfg::tdmCycleFormat

Cycle format (TDM mode only) for the VP output. For valid values see CSL_DssVpTdmCycleFormat

◆ tdmParallelMode

uint32_t CSL_DssVpLcdTdmCfg::tdmParallelMode

Output interface width (TDM mode only) for the VP output. For valid values see CSL_DssVpTdmParallelMode

◆ numBitsPixel1Cycle0

uint32_t CSL_DssVpLcdTdmCfg::numBitsPixel1Cycle0

Number of bits from the pixel 1 for cycle 0(value from 0 to 16 bits). The values from 17 to 31 are invalid

◆ numBitsPixel1Cycle1

uint32_t CSL_DssVpLcdTdmCfg::numBitsPixel1Cycle1

Number of bits from the pixel 1 for cycle 1(value from 0 to 16 bits). The values from 17 to 31 are invalid

◆ numBitsPixel1Cycle2

uint32_t CSL_DssVpLcdTdmCfg::numBitsPixel1Cycle2

Number of bits from the pixel 1 for cycle 2(value from 0 to 16 bits). The values from 17 to 31 are invalid

◆ bitAlignPixel1Cycle0

uint32_t CSL_DssVpLcdTdmCfg::bitAlignPixel1Cycle0

Alignment of the bits from pixel 1 for cycle0 on the output interface

◆ bitAlignPixel1Cycle1

uint32_t CSL_DssVpLcdTdmCfg::bitAlignPixel1Cycle1

Alignment of the bits from pixel 1 for cycle1 on the output interface

◆ bitAlignPixel1Cycle2

uint32_t CSL_DssVpLcdTdmCfg::bitAlignPixel1Cycle2

Alignment of the bits from pixel 1 for cycle2 on the output interface

◆ numBitsPixel2Cycle0

uint32_t CSL_DssVpLcdTdmCfg::numBitsPixel2Cycle0

Number of bits from the pixel 2 for cycle 0(value from 0 to 16 bits). The values from 17 to 31 are invalid

◆ numBitsPixel2Cycle1

uint32_t CSL_DssVpLcdTdmCfg::numBitsPixel2Cycle1

Number of bits from the pixel 2 for cycle 1(value from 0 to 16 bits). The values from 17 to 31 are invalid

◆ numBitsPixel2Cycle2

uint32_t CSL_DssVpLcdTdmCfg::numBitsPixel2Cycle2

Number of bits from the pixel 2 for cycle 2(value from 0 to 16 bits). The values from 17 to 31 are invalid

◆ bitAlignPixel2Cycle0

uint32_t CSL_DssVpLcdTdmCfg::bitAlignPixel2Cycle0

Alignment of the bits from pixel 2 for cycle 0 on the output interface

◆ bitAlignPixel2Cycle1

uint32_t CSL_DssVpLcdTdmCfg::bitAlignPixel2Cycle1

Alignment of the bits from pixel 2 for cycle 1 on the output interface

◆ bitAlignPixel2Cycle2

uint32_t CSL_DssVpLcdTdmCfg::bitAlignPixel2Cycle2

Alignment of the bits from pixel 2 for cycle 2 on the output interface