Introduction

This is hardware include layer for DSS video port region.

Files
file	csl_dssVideoPort.h
	DSS Video Port layer interface file.

Data Structures
struct	CSL_DssVpGammaCfg
	Gamma Correction configuration for DSS Video Port Output. More...

struct	CSL_DssVpLcdTdmCfg
	LCD Configuration for Time Division Multiplexing. More...

struct	CSL_DssVpLcdSignalPolarityCfg
	Polarity of Active Video, Pixel Clock, HSync and VSync signals for the LCD. More...

struct	CSL_DssVpLcdAdvSignalCfg
	Advance Signal Configuration for the LCD. More...

struct	CSL_DssVpLcdOpTimingCfg
	Timing configuration for the LCD output. More...

struct	CSL_DssVpLcdBlankTimingCfg
	Blanking Timing parameters for the LCD. More...

struct	CSL_DssVpOldiCfg
	OLDI Configuration. More...

Functions
void	CSL_dssVpEnable (CSL_dss_vpRegs *vpRegs, uint32_t enable)
	Enable the DSS Video Port. More...

void	CSL_dssVpSetGoBit (CSL_dss_vpRegs *vpRegs)
	GO Command for the VP output. It is used to synchronize the pipelines associated with the VP output. More...

void	CSL_dssVpSetLcdTdmConfig (CSL_dss_vpRegs vpRegs, const CSL_DssVpLcdTdmCfg lcdTdmCfg)
	Configure the LCD TDM(Time division multiplexing) parameters. More...

void	CSL_dssVpSetLcdLineNum (CSL_dss_vpRegs *vpRegs, uint32_t lineNum)
	Set the Line Number at which the interrupt should be generated. More...

int32_t	CSL_dssVpSetLcdOpTimingConfig (CSL_dss_vpRegs vpRegs, const CSL_DssVpLcdOpTimingCfg lcdCfg)
	Configure the LCD Timing parameters. More...

int32_t	CSL_dssVpSetLcdBlankTiming (CSL_dss_vpRegs vpRegs, const CSL_DssVpLcdBlankTimingCfg blankCfg, uint32_t dvoFormat, uint32_t scanFormat, uint32_t isCustomTiming)
	Configure the LCD Blank Timing parameters. More...

void	CSL_dssVpSetLcdAdvSignalConfig (CSL_dss_vpRegs vpRegs, const CSL_DssVpLcdAdvSignalCfg advSignalCfg)
	Configure the advance LCD Signal parameters. More...

void	CSL_dssVpSetLcdSignalPolarityConfig (CSL_dss_vpRegs vpRegs, const CSL_DssVpLcdSignalPolarityCfg polarityCfg)
	Configure the Polarity of LCD signals(HSYNC, VSYNC, PCLK, Data) More...

void	CSL_dssVpEnableTvGamma (CSL_dss_vpRegs vpRegs, const CSL_DssVpGammaCfg gammaCfg)
	Enable/Bypass TV Gamma Table. More...

void	CSL_dssVpSetCSCCoeff (CSL_dss_vpRegs vpRegs, const CSL_DssCscCoeff cscCoeff, uint32_t cscPos, uint32_t cscEnable)
	Configure the coefficients for Color Space Conversion. More...

void	CSL_dssVpSetSafetySignSeedVal (CSL_dss_vpRegs *vpRegs, uint32_t signSeedVal)
	Set the seed value for the signature calculation. More...

void	CSL_dssVpSetSafetyReferenceSign (CSL_dss_vpRegs *vpRegs, uint32_t referenceSign, uint32_t regionId)
	Set the reference safety signature for data correctness check. More...

void	CSL_dssVpSetSafetyChkConfig (CSL_dss_vpRegs vpRegs, const CSL_DssSafetyChkCfg safetyCfg, uint32_t regionId)
	Configure the Safety Check parameters. More...

uint32_t	CSL_dssVpGetSafetySign (const CSL_dss_vpRegs *vpRegs, uint32_t regionId)
	Get the Safety Signature of the sub region. More...

void	CSL_dssVpOldiReset (const CSL_dss_vpRegs *vpRegs)
	Reset the OLDI Module. More...

void	CSL_dssVpSetOldiConfig (CSL_dss_vpRegs vpRegs, const CSL_DssVpOldiCfg oldiCfg)
	Set the OLDI configuration. More...

void	CSL_dssVpOldiEnable (CSL_dss_vpRegs *vpRegs, uint32_t enable)
	Enable/disable the OLDI Module. More...

static void	CSL_dssVpGammaCfgInit (CSL_DssVpGammaCfg *gammaCfg)
	CSL_DssVpGammaCfg structure init function. More...

static void	CSL_dssVpLcdTdmCfgInit (CSL_DssVpLcdTdmCfg *tdmCfg)
	CSL_DssVpLcdTdmCfg structure init function. More...

static void	CSL_dssVpLcdSignalPolarityCfgInit (CSL_DssVpLcdSignalPolarityCfg *polarityCfg)
	CSL_DssVpLcdSignalPolarityCfg structure init function. More...

static void	CSL_dssVpLcdAdvSignalCfgInit (CSL_DssVpLcdAdvSignalCfg *advSignalCfg)
	CSL_DssVpLcdAdvSignalCfg structure init function. More...

static void	CSL_dssVpLcdOpTimingCfgInit (CSL_DssVpLcdOpTimingCfg *lcdCfg)
	CSL_DssVpLcdOpTimingCfg structure init function. More...

static void	CSL_dssVpLcdBlankTimingCfgInit (CSL_DssVpLcdBlankTimingCfg *blankCfg)
	CSL_DssVpLcdBlankTimingCfg structure init function. More...

static void	CSL_dssVpOldiCfgInit (CSL_DssVpOldiCfg *oldiCfg)
	CSL_DssVpOldiCfg structure init function. More...

Typedefs
typedef CSL_dss_vp1Regs	CSL_dss_vpRegs
	DSS Video Port Registers. More...

Video Port CSC Position
DSS Video Port Color Space Conversion block position wrt Gamma block
#define	CSL_DSS_VP_CSC_POS_AFTER_GAMMA ((uint32_t) CSL_DSS_VP1_CONFIG_COLORCONVPOS_VAL_AFTERGAMMA)
	CSC block is after GAMMA correction. More...

#define	CSL_DSS_VP_CSC_POS_BEFORE_GAMMA ((uint32_t) CSL_DSS_VP1_CONFIG_COLORCONVPOS_VAL_BEFOREGAMMA)
	CSC block is before GAMMA correction. More...

TDM Mode Unused Bits Level
State of unused bits in TDM mode for the VP output
#define	CSL_DSS_VP_TDM_UNUSED_BITS_LEVEL_LOW ((uint32_t) CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_VAL_LOWLEVEL)
	Low level. More...

#define	CSL_DSS_VP_TDM_UNUSED_BITS_LEVEL_HIGH ((uint32_t) CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_VAL_HIGHLEVEL)
	High level. More...

#define	CSL_DSS_VP_TDM_UNUSED_BITS_LEVEL_UNCHANGED ((uint32_t) CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_VAL_UNCHANGED)
	Unchanged level. More...

TDM Cycle format

#define	CSL_DSS_VP_TDM_CYCLE_1PERPIXEL ((uint32_t) CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_1CYCPERPIX)
	1 cycle per pixel More...

#define	CSL_DSS_VP_TDM_CYCLE_2PERPIXEL ((uint32_t) CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_2CYCPERPIX)
	2 cycles per pixel More...

#define	CSL_DSS_VP_TDM_CYCLE_3PERPIXEL ((uint32_t) CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_3CYCPERPIX)
	3 cycles per pixel More...

#define	CSL_DSS_VP_TDM_CYCLE_3PER2PIXEL ((uint32_t) CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_3CYCPER2PIX)
	3 cycles per 2 pixels More...

Output interface width in TDM mode

#define	CSL_DSS_VP_TDM_PARALLEL_OUTPUT_8BIT ((uint32_t) CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_8BPARAINT)
	8-bit parallel output interface selected More...

#define	CSL_DSS_VP_TDM_PARALLEL_OUTPUT_9BIT ((uint32_t) CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_9BPARAINT)
	9-bit parallel output interface selected More...

#define	CSL_DSS_VP_TDM_PARALLEL_OUTPUT_12BIT ((uint32_t) CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_12BPARAINT)
	12-bit parallel output interface selected More...

#define	CSL_DSS_VP_TDM_PARALLEL_OUTPUT_16BIT ((uint32_t) CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_16BPARAINT)
	16-bit parallel output interface selected More...

LCD HSync VSync Alignment

#define	CSL_DSS_VP_HVSYNC_NOT_ALIGNED ((uint32_t) CSL_DSS_VP1_POL_FREQ_ALIGN_VAL_NOTALIGNED)
	HSYNC and VSYNC are not aligned. More...

#define	CSL_DSS_VP_HVSYNC_ALIGNED ((uint32_t) CSL_DSS_VP1_POL_FREQ_ALIGN_VAL_ALIGNED)
	HSYNC and VSYNC assertions are aligned. More...

LCD HSYNC/VSYNC pixel clock control

#define	CSL_DSS_VP_HVCLK_CONTROL_OFF ((uint32_t) CSL_DSS_VP1_POL_FREQ_ONOFF_VAL_DOPEDPCK)
	HSYNC and VSYNC are driven on opposite edges of the pixel clock than pixel data. More...

#define	CSL_DSS_VP_HVCLK_CONTROL_ON ((uint32_t) CSL_DSS_VP1_POL_FREQ_ONOFF_VAL_DBIT16)
	HSYNC and VSYNC are driven according to hVClkRiseFall value. More...

Delta Lines Per Panel
Delta size value of the odd field compared to the even field
#define	CSL_DSS_VP_LPP_DELTA_ZERO ((uint32_t) CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_VAL_SAME)
	Odd field has same size as even. More...

#define	CSL_DSS_VP_LPP_DELTA_PLUSONE ((uint32_t) CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_VAL_PLUSONE)
	Odd field is equal to even field + 1. More...

#define	CSL_DSS_VP_LPP_DELTA_MINUSONE ((uint32_t) CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_VAL_MINUSONE)
	Odd field is equal to even field - 1. More...

Video Port First Field
First Field to Video Port output in case of interlace mode
#define	CSL_DSS_VP_FID_FIRST_EVEN ((uint32_t) CSL_DSS_VP1_CONFIG_FIDFIRST_VAL_EVEN)
	First field is even. More...

#define	CSL_DSS_VP_FID_FIRST_ODD ((uint32_t) CSL_DSS_VP1_CONFIG_FIDFIRST_VAL_ODD)
	First field is odd. More...

DSS Video Port Safety Region Id

#define	CSL_DSS_VP_SAFETY_REGION_0 ((uint32_t) 0x0U)
	Safety Region 0. More...

#define	CSL_DSS_VP_SAFETY_REGION_1 ((uint32_t) 0x1U)
	Safety Region 1. More...

#define	CSL_DSS_VP_SAFETY_REGION_2 ((uint32_t) 0x2U)
	Safety Region 2. More...

#define	CSL_DSS_VP_SAFETY_REGION_3 ((uint32_t) 0x3U)
	Safety Region 3. More...

#define	CSL_DSS_VP_SAFETY_REGION_MAX ((uint32_t) 0x4U)
	Safety Region Max. More...

#define	CSL_DSS_VP_SAFETY_REGION_INVALID ((uint32_t) 0xFFU)
	Invalid Safety Region. More...

OLDI Map Type
Configuration of OLDI mapping. Specifies different data formats.
#define	CSL_DSS_VP_OLDI_MAP_TYPE_A ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_A)
	Map Type A is Single Link 18 bit. More...

#define	CSL_DSS_VP_OLDI_MAP_TYPE_B ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_B)
	Map Type B is Single Link 24 bit JEIDA. More...

#define	CSL_DSS_VP_OLDI_MAP_TYPE_C ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_C)
	Map Type C is Single Link 24 bit VESA. More...

#define	CSL_DSS_VP_OLDI_MAP_TYPE_D ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_D)
	Map Type D is Dual-link 18-bit. More...

#define	CSL_DSS_VP_OLDI_MAP_TYPE_E ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_E)
	Map Type E is Dual-link 24-bit JEIDA. More...

#define	CSL_DSS_VP_OLDI_MAP_TYPE_F ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_F)
	Map Type F is Dual-link 24-bit VESA. More...

Input RGB data Bit Depth from DSS
18 bit LVDS output mapping is supported both from 24 bit input and 18 bit input. In case of 24 bit input mapping is R[7:2], G[7:2] and B[7:2]. In case of 18 bit input mapping is R[5:0], G[5:0] and B[5:0].
#define	CSL_DSS_VP_OLDI_BIT_DEPTH_18_BITS ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_MSB_VAL_18B)
	Input RGB data's bit depth is 18. More...

#define	CSL_DSS_VP_OLDI_BIT_DEPTH_24_BITS ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_MSB_VAL_24B)
	Input RGB data's bit depth is 24. More...

OLDI dual mode operation
Dual mode operation is used for high resolution on OLDI.
#define	CSL_DSS_VP_OLDI_DUALMODESYNC_ENABLE ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_DUALMODESYNC_VAL_ENABLE)
	Enable dual mode operation. More...

#define	CSL_DSS_VP_OLDI_DUALMODESYNC_DISABLE ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_DUALMODESYNC_VAL_DISABLE)
	Disable dual mode operation. More...

Macro Definition Documentation

◆ CSL_DSS_VP_CSC_POS_AFTER_GAMMA

#define CSL_DSS_VP_CSC_POS_AFTER_GAMMA ((uint32_t) CSL_DSS_VP1_CONFIG_COLORCONVPOS_VAL_AFTERGAMMA)

CSC block is after GAMMA correction.

◆ CSL_DSS_VP_CSC_POS_BEFORE_GAMMA

#define CSL_DSS_VP_CSC_POS_BEFORE_GAMMA ((uint32_t) CSL_DSS_VP1_CONFIG_COLORCONVPOS_VAL_BEFOREGAMMA)

CSC block is before GAMMA correction.

◆ CSL_DSS_VP_TDM_UNUSED_BITS_LEVEL_LOW

#define CSL_DSS_VP_TDM_UNUSED_BITS_LEVEL_LOW ((uint32_t) CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_VAL_LOWLEVEL)

Low level.

◆ CSL_DSS_VP_TDM_UNUSED_BITS_LEVEL_HIGH

#define CSL_DSS_VP_TDM_UNUSED_BITS_LEVEL_HIGH ((uint32_t) CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_VAL_HIGHLEVEL)

High level.

◆ CSL_DSS_VP_TDM_UNUSED_BITS_LEVEL_UNCHANGED

#define CSL_DSS_VP_TDM_UNUSED_BITS_LEVEL_UNCHANGED ((uint32_t) CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_VAL_UNCHANGED)

Unchanged level.

◆ CSL_DSS_VP_TDM_CYCLE_1PERPIXEL

#define CSL_DSS_VP_TDM_CYCLE_1PERPIXEL ((uint32_t) CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_1CYCPERPIX)

1 cycle per pixel

◆ CSL_DSS_VP_TDM_CYCLE_2PERPIXEL

#define CSL_DSS_VP_TDM_CYCLE_2PERPIXEL ((uint32_t) CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_2CYCPERPIX)

2 cycles per pixel

◆ CSL_DSS_VP_TDM_CYCLE_3PERPIXEL

#define CSL_DSS_VP_TDM_CYCLE_3PERPIXEL ((uint32_t) CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_3CYCPERPIX)

3 cycles per pixel

◆ CSL_DSS_VP_TDM_CYCLE_3PER2PIXEL

#define CSL_DSS_VP_TDM_CYCLE_3PER2PIXEL ((uint32_t) CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_3CYCPER2PIX)

3 cycles per 2 pixels

◆ CSL_DSS_VP_TDM_PARALLEL_OUTPUT_8BIT

#define CSL_DSS_VP_TDM_PARALLEL_OUTPUT_8BIT ((uint32_t) CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_8BPARAINT)

8-bit parallel output interface selected

◆ CSL_DSS_VP_TDM_PARALLEL_OUTPUT_9BIT

#define CSL_DSS_VP_TDM_PARALLEL_OUTPUT_9BIT ((uint32_t) CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_9BPARAINT)

9-bit parallel output interface selected

◆ CSL_DSS_VP_TDM_PARALLEL_OUTPUT_12BIT

#define CSL_DSS_VP_TDM_PARALLEL_OUTPUT_12BIT ((uint32_t) CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_12BPARAINT)

12-bit parallel output interface selected

◆ CSL_DSS_VP_TDM_PARALLEL_OUTPUT_16BIT

#define CSL_DSS_VP_TDM_PARALLEL_OUTPUT_16BIT ((uint32_t) CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_16BPARAINT)

16-bit parallel output interface selected

◆ CSL_DSS_VP_HVSYNC_NOT_ALIGNED

#define CSL_DSS_VP_HVSYNC_NOT_ALIGNED ((uint32_t) CSL_DSS_VP1_POL_FREQ_ALIGN_VAL_NOTALIGNED)

HSYNC and VSYNC are not aligned.

◆ CSL_DSS_VP_HVSYNC_ALIGNED

#define CSL_DSS_VP_HVSYNC_ALIGNED ((uint32_t) CSL_DSS_VP1_POL_FREQ_ALIGN_VAL_ALIGNED)

HSYNC and VSYNC assertions are aligned.

◆ CSL_DSS_VP_HVCLK_CONTROL_OFF

#define CSL_DSS_VP_HVCLK_CONTROL_OFF ((uint32_t) CSL_DSS_VP1_POL_FREQ_ONOFF_VAL_DOPEDPCK)

HSYNC and VSYNC are driven on opposite edges of the pixel clock than pixel data.

◆ CSL_DSS_VP_HVCLK_CONTROL_ON

#define CSL_DSS_VP_HVCLK_CONTROL_ON ((uint32_t) CSL_DSS_VP1_POL_FREQ_ONOFF_VAL_DBIT16)

HSYNC and VSYNC are driven according to hVClkRiseFall value.

◆ CSL_DSS_VP_LPP_DELTA_ZERO

#define CSL_DSS_VP_LPP_DELTA_ZERO ((uint32_t) CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_VAL_SAME)

Odd field has same size as even.

◆ CSL_DSS_VP_LPP_DELTA_PLUSONE

#define CSL_DSS_VP_LPP_DELTA_PLUSONE ((uint32_t) CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_VAL_PLUSONE)

Odd field is equal to even field + 1.

◆ CSL_DSS_VP_LPP_DELTA_MINUSONE

#define CSL_DSS_VP_LPP_DELTA_MINUSONE ((uint32_t) CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_VAL_MINUSONE)

Odd field is equal to even field - 1.

◆ CSL_DSS_VP_FID_FIRST_EVEN

#define CSL_DSS_VP_FID_FIRST_EVEN ((uint32_t) CSL_DSS_VP1_CONFIG_FIDFIRST_VAL_EVEN)

First field is even.

◆ CSL_DSS_VP_FID_FIRST_ODD

#define CSL_DSS_VP_FID_FIRST_ODD ((uint32_t) CSL_DSS_VP1_CONFIG_FIDFIRST_VAL_ODD)

First field is odd.

◆ CSL_DSS_VP_SAFETY_REGION_0

#define CSL_DSS_VP_SAFETY_REGION_0 ((uint32_t) 0x0U)

Safety Region 0.

◆ CSL_DSS_VP_SAFETY_REGION_1

#define CSL_DSS_VP_SAFETY_REGION_1 ((uint32_t) 0x1U)

Safety Region 1.

◆ CSL_DSS_VP_SAFETY_REGION_2

#define CSL_DSS_VP_SAFETY_REGION_2 ((uint32_t) 0x2U)

Safety Region 2.

◆ CSL_DSS_VP_SAFETY_REGION_3

#define CSL_DSS_VP_SAFETY_REGION_3 ((uint32_t) 0x3U)

Safety Region 3.

◆ CSL_DSS_VP_SAFETY_REGION_MAX

#define CSL_DSS_VP_SAFETY_REGION_MAX ((uint32_t) 0x4U)

Safety Region Max.

◆ CSL_DSS_VP_SAFETY_REGION_INVALID

#define CSL_DSS_VP_SAFETY_REGION_INVALID ((uint32_t) 0xFFU)

Invalid Safety Region.

◆ CSL_DSS_VP_OLDI_MAP_TYPE_A

#define CSL_DSS_VP_OLDI_MAP_TYPE_A ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_A)

Map Type A is Single Link 18 bit.

◆ CSL_DSS_VP_OLDI_MAP_TYPE_B

#define CSL_DSS_VP_OLDI_MAP_TYPE_B ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_B)

Map Type B is Single Link 24 bit JEIDA.

◆ CSL_DSS_VP_OLDI_MAP_TYPE_C

#define CSL_DSS_VP_OLDI_MAP_TYPE_C ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_C)

Map Type C is Single Link 24 bit VESA.

◆ CSL_DSS_VP_OLDI_MAP_TYPE_D

#define CSL_DSS_VP_OLDI_MAP_TYPE_D ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_D)

Map Type D is Dual-link 18-bit.

◆ CSL_DSS_VP_OLDI_MAP_TYPE_E

#define CSL_DSS_VP_OLDI_MAP_TYPE_E ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_E)

Map Type E is Dual-link 24-bit JEIDA.

◆ CSL_DSS_VP_OLDI_MAP_TYPE_F

#define CSL_DSS_VP_OLDI_MAP_TYPE_F ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_F)

Map Type F is Dual-link 24-bit VESA.

◆ CSL_DSS_VP_OLDI_BIT_DEPTH_18_BITS

#define CSL_DSS_VP_OLDI_BIT_DEPTH_18_BITS ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_MSB_VAL_18B)

Input RGB data's bit depth is 18.

◆ CSL_DSS_VP_OLDI_BIT_DEPTH_24_BITS

#define CSL_DSS_VP_OLDI_BIT_DEPTH_24_BITS ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_MSB_VAL_24B)

Input RGB data's bit depth is 24.

◆ CSL_DSS_VP_OLDI_DUALMODESYNC_ENABLE

#define CSL_DSS_VP_OLDI_DUALMODESYNC_ENABLE ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_DUALMODESYNC_VAL_ENABLE)

Enable dual mode operation.

◆ CSL_DSS_VP_OLDI_DUALMODESYNC_DISABLE

#define CSL_DSS_VP_OLDI_DUALMODESYNC_DISABLE ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_DUALMODESYNC_VAL_DISABLE)

Disable dual mode operation.

Typedef Documentation

◆ CSL_dss_vpRegs

typedef CSL_dss_vp1Regs CSL_dss_vpRegs

DSS Video Port Registers.

DSS7 UL has two identical VP blocks, hence define a generic structure to have common APIs

Function Documentation

◆ CSL_dssVpEnable()

void CSL_dssVpEnable	(	CSL_dss_vpRegs *	vpRegs,
		uint32_t	enable
	)

Enable the DSS Video Port.

Parameters

vpRegs	Pointer to a CSL_dss_vpRegs structure containing the video port configuration
enable	Enable or disable the Video Port TRUE: Enable FALSE: Disable

◆ CSL_dssVpSetGoBit()

void CSL_dssVpSetGoBit ( CSL_dss_vpRegs * vpRegs )

GO Command for the VP output. It is used to synchronize the pipelines associated with the VP output.

Parameters

vpRegs Pointer to a CSL_dss_vpRegs structure containing the video port configuration

◆ CSL_dssVpSetLcdTdmConfig()

void CSL_dssVpSetLcdTdmConfig	(	CSL_dss_vpRegs *	vpRegs,
		const CSL_DssVpLcdTdmCfg *	lcdTdmCfg
	)

Configure the LCD TDM(Time division multiplexing) parameters.

Parameters

vpRegs	Pointer to a CSL_dss_vpRegs structure containing the video port configuration
lcdTdmCfg	Pointer to the CSL_DssVpLcdTdmCfg structure. This parameter should not be NULL

◆ CSL_dssVpSetLcdLineNum()

void CSL_dssVpSetLcdLineNum	(	CSL_dss_vpRegs *	vpRegs,
		uint32_t	lineNum
	)

Set the Line Number at which the interrupt should be generated.

Parameters

vpRegs	Pointer to a CSL_dss_vpRegs structure containing the video port configuration
lineNum	Line Number that should be programmed in the register

◆ CSL_dssVpSetLcdOpTimingConfig()

int32_t CSL_dssVpSetLcdOpTimingConfig	(	CSL_dss_vpRegs *	vpRegs,
		const CSL_DssVpLcdOpTimingCfg *	lcdCfg
	)

Configure the LCD Timing parameters.

Parameters

vpRegs	Pointer to a CSL_dss_vpRegs structure containing the video port configuration
lcdCfg	Pointer to the CSL_DssVpLcdOpTimingCfg structure. This parameter should not be NULL

Returns: CSL_ErrType_t

◆ CSL_dssVpSetLcdBlankTiming()

int32_t CSL_dssVpSetLcdBlankTiming	(	CSL_dss_vpRegs *	vpRegs,
		const CSL_DssVpLcdBlankTimingCfg *	blankCfg,
		uint32_t	dvoFormat,
		uint32_t	scanFormat,
		uint32_t	isCustomTiming
	)

Configure the LCD Blank Timing parameters.

Parameters

vpRegs	Pointer to a CSL_dss_vpRegs structure containing the video port configuration
blankCfg	Pointer to the CSL_DssVpLcdBlankTimingCfg structure. This parameter should not be NULL
dvoFormat	Digital output format. For valid values see Fvid2_DVFormat
scanFormat	Scan format. For valid values see Fvid2_ScanFormat
isCustomTiming	Variable to determine whether custom timing is used. It should always be set to TRUE when this API is called by application.

Returns: CSL_ErrType_t

◆ CSL_dssVpSetLcdAdvSignalConfig()

void CSL_dssVpSetLcdAdvSignalConfig	(	CSL_dss_vpRegs *	vpRegs,
		const CSL_DssVpLcdAdvSignalCfg *	advSignalCfg
	)

Configure the advance LCD Signal parameters.

Parameters

vpRegs	Pointer to a CSL_dss_vpRegs structure containing the video port configuration
advSignalCfg	Pointer to CSL_DssVpLcdAdvSignalCfg structure. This parameter should not be NULL

◆ CSL_dssVpSetLcdSignalPolarityConfig()

void CSL_dssVpSetLcdSignalPolarityConfig	(	CSL_dss_vpRegs *	vpRegs,
		const CSL_DssVpLcdSignalPolarityCfg *	polarityCfg
	)

Configure the Polarity of LCD signals(HSYNC, VSYNC, PCLK, Data)

Parameters

vpRegs	Pointer to a CSL_dss_vpRegs structure containing the video port configuration
polarityCfg	Pointer to CSL_DssVpLcdSignalPolarityCfg structure. This parameter should not be NULL

◆ CSL_dssVpEnableTvGamma()

void CSL_dssVpEnableTvGamma	(	CSL_dss_vpRegs *	vpRegs,
		const CSL_DssVpGammaCfg *	gammaCfg
	)

Enable/Bypass TV Gamma Table.

Parameters

vpRegs	Pointer to a CSL_dss_vpRegs structure containing the video port configuration
gammaCfg	Pointer to CSL_DssVpGammaCfg structure. This parameter should not be NULL

◆ CSL_dssVpSetCSCCoeff()

void CSL_dssVpSetCSCCoeff	(	CSL_dss_vpRegs *	vpRegs,
		const CSL_DssCscCoeff *	cscCoeff,
		uint32_t	cscPos,
		uint32_t	cscEnable
	)

Configure the coefficients for Color Space Conversion.

Parameters

vpRegs	Pointer to a CSL_dss_vpRegs structure containing the video port configuration
cscCoeff	Pointer to CSL_DssCscCoeff structure. This parameter should not be NULL
cscPos	Position of CSC block wrt GAMMA module. Refer CSL_DssVpCscPos for value
cscEnable	CSC Enable TRUE: Enable CSC FALSE: Disable CSC

◆ CSL_dssVpSetSafetySignSeedVal()

void CSL_dssVpSetSafetySignSeedVal	(	CSL_dss_vpRegs *	vpRegs,
		uint32_t	signSeedVal
	)

Set the seed value for the signature calculation.

Parameters

vpRegs	Pointer to a CSL_dss_vpRegs structure containing the video port configuration
signSeedVal	Signature Seed Value to be Set

◆ CSL_dssVpSetSafetyReferenceSign()

void CSL_dssVpSetSafetyReferenceSign	(	CSL_dss_vpRegs *	vpRegs,
		uint32_t	referenceSign,
		uint32_t	regionId
	)

Set the reference safety signature for data correctness check.

Parameters

vpRegs	Pointer to a CSL_dss_vpRegs structure containing the video port configuration
referenceSign	Reference Safety Signature
regionId	Region for which safety check should be done. Refer CSL_DssVpSafetyRegionId for values

◆ CSL_dssVpSetSafetyChkConfig()

void CSL_dssVpSetSafetyChkConfig	(	CSL_dss_vpRegs *	vpRegs,
		const CSL_DssSafetyChkCfg *	safetyCfg,
		uint32_t	regionId
	)

Configure the Safety Check parameters.

Parameters

vpRegs	Pointer to a CSL_dss_vpRegs structure containing the video port configuration
safetyCfg	Pointer to CSL_DssSafetyChkCfg structure. This parameter should not be NULL
regionId	Region for which safety check should be done. Refer CSL_DssVpSafetyRegionId for values

◆ CSL_dssVpGetSafetySign()

uint32_t CSL_dssVpGetSafetySign	(	const CSL_dss_vpRegs *	vpRegs,
		uint32_t	regionId
	)

Get the Safety Signature of the sub region.

Parameters

vpRegs	Pointer to a CSL_dss_vpRegs structure containing the video port configuration
regionId	Region for which safety check should be done. Refer CSL_DssVpSafetyRegionId for values

Returns: Signature Value

◆ CSL_dssVpOldiReset()

void CSL_dssVpOldiReset ( const CSL_dss_vpRegs * vpRegs )

Reset the OLDI Module.

Parameters

vpRegs Pointer to a CSL_dss_vpRegs structure containing the video port configuration

◆ CSL_dssVpSetOldiConfig()

void CSL_dssVpSetOldiConfig	(	CSL_dss_vpRegs *	vpRegs,
		const CSL_DssVpOldiCfg *	oldiCfg
	)

Set the OLDI configuration.

Parameters

vpRegs	Pointer to a CSL_dss_vpRegs structure containing the video port configuration
oldiCfg	Pointer to CSL_DssVpOldiCfg structure. This parameter should not be NULL

◆ CSL_dssVpOldiEnable()

void CSL_dssVpOldiEnable	(	CSL_dss_vpRegs *	vpRegs,
		uint32_t	enable
	)

Enable/disable the OLDI Module.

Parameters

vpRegs	Pointer to a CSL_dss_vpRegs structure containing the video port configuration
enable	Enable or disable OLDI TRUE: Enable FALSE: Disable

◆ CSL_dssVpGammaCfgInit()

static void CSL_dssVpGammaCfgInit ( CSL_DssVpGammaCfg * gammaCfg )

inlinestatic

CSL_DssVpGammaCfg structure init function.

Parameters

gammaCfg Pointer to CSL_DssVpGammaCfg structure

◆ CSL_dssVpLcdTdmCfgInit()

static void CSL_dssVpLcdTdmCfgInit ( CSL_DssVpLcdTdmCfg * tdmCfg )

inlinestatic

CSL_DssVpLcdTdmCfg structure init function.

Parameters

tdmCfg Pointer to CSL_DssVpLcdTdmCfg structure

◆ CSL_dssVpLcdSignalPolarityCfgInit()

static void CSL_dssVpLcdSignalPolarityCfgInit ( CSL_DssVpLcdSignalPolarityCfg * polarityCfg )

inlinestatic

CSL_DssVpLcdSignalPolarityCfg structure init function.

Parameters

polarityCfg Pointer to CSL_DssVpLcdSignalPolarityCfg structure

◆ CSL_dssVpLcdAdvSignalCfgInit()

static void CSL_dssVpLcdAdvSignalCfgInit ( CSL_DssVpLcdAdvSignalCfg * advSignalCfg )

inlinestatic

CSL_DssVpLcdAdvSignalCfg structure init function.

Parameters

advSignalCfg Pointer to CSL_DssVpLcdAdvSignalCfg structure

◆ CSL_dssVpLcdOpTimingCfgInit()

static void CSL_dssVpLcdOpTimingCfgInit ( CSL_DssVpLcdOpTimingCfg * lcdCfg )

inlinestatic

CSL_DssVpLcdOpTimingCfg structure init function.

Parameters

lcdCfg Pointer to CSL_DssVpLcdOpTimingCfg structure

◆ CSL_dssVpLcdBlankTimingCfgInit()

static void CSL_dssVpLcdBlankTimingCfgInit ( CSL_DssVpLcdBlankTimingCfg * blankCfg )

inlinestatic

CSL_DssVpLcdBlankTimingCfg structure init function.

Parameters

blankCfg Pointer to CSL_DssVpLcdBlankTimingCfg structure

◆ CSL_dssVpOldiCfgInit()

static void CSL_dssVpOldiCfgInit ( CSL_DssVpOldiCfg * oldiCfg )

inlinestatic

CSL_DssVpOldiCfg structure init function.

Parameters

oldiCfg Pointer to CSL_DssVpOldiCfg structure

Introduction

Files

Data Structures

Functions

Typedefs

Video Port CSC Position

TDM Mode Unused Bits Level

TDM Cycle format

Output interface width in TDM mode

LCD HSync VSync Alignment

LCD HSYNC/VSYNC pixel clock control

Delta Lines Per Panel

Video Port First Field

DSS Video Port Safety Region Id

OLDI Map Type

Input RGB data Bit Depth from DSS

OLDI dual mode operation

Macro Definition Documentation

◆ CSL_DSS_VP_CSC_POS_AFTER_GAMMA

◆ CSL_DSS_VP_CSC_POS_BEFORE_GAMMA

◆ CSL_DSS_VP_TDM_UNUSED_BITS_LEVEL_LOW

◆ CSL_DSS_VP_TDM_UNUSED_BITS_LEVEL_HIGH

◆ CSL_DSS_VP_TDM_UNUSED_BITS_LEVEL_UNCHANGED

◆ CSL_DSS_VP_TDM_CYCLE_1PERPIXEL

◆ CSL_DSS_VP_TDM_CYCLE_2PERPIXEL

◆ CSL_DSS_VP_TDM_CYCLE_3PERPIXEL

◆ CSL_DSS_VP_TDM_CYCLE_3PER2PIXEL

◆ CSL_DSS_VP_TDM_PARALLEL_OUTPUT_8BIT

◆ CSL_DSS_VP_TDM_PARALLEL_OUTPUT_9BIT

◆ CSL_DSS_VP_TDM_PARALLEL_OUTPUT_12BIT

◆ CSL_DSS_VP_TDM_PARALLEL_OUTPUT_16BIT

◆ CSL_DSS_VP_HVSYNC_NOT_ALIGNED

◆ CSL_DSS_VP_HVSYNC_ALIGNED

◆ CSL_DSS_VP_HVCLK_CONTROL_OFF

◆ CSL_DSS_VP_HVCLK_CONTROL_ON

◆ CSL_DSS_VP_LPP_DELTA_ZERO

◆ CSL_DSS_VP_LPP_DELTA_PLUSONE

◆ CSL_DSS_VP_LPP_DELTA_MINUSONE

◆ CSL_DSS_VP_FID_FIRST_EVEN

◆ CSL_DSS_VP_FID_FIRST_ODD

◆ CSL_DSS_VP_SAFETY_REGION_0

◆ CSL_DSS_VP_SAFETY_REGION_1

◆ CSL_DSS_VP_SAFETY_REGION_2

◆ CSL_DSS_VP_SAFETY_REGION_3

◆ CSL_DSS_VP_SAFETY_REGION_MAX

◆ CSL_DSS_VP_SAFETY_REGION_INVALID

◆ CSL_DSS_VP_OLDI_MAP_TYPE_A

◆ CSL_DSS_VP_OLDI_MAP_TYPE_B

◆ CSL_DSS_VP_OLDI_MAP_TYPE_C

◆ CSL_DSS_VP_OLDI_MAP_TYPE_D

◆ CSL_DSS_VP_OLDI_MAP_TYPE_E

◆ CSL_DSS_VP_OLDI_MAP_TYPE_F

◆ CSL_DSS_VP_OLDI_BIT_DEPTH_18_BITS

◆ CSL_DSS_VP_OLDI_BIT_DEPTH_24_BITS

◆ CSL_DSS_VP_OLDI_DUALMODESYNC_ENABLE

◆ CSL_DSS_VP_OLDI_DUALMODESYNC_DISABLE

Typedef Documentation

◆ CSL_dss_vpRegs

Function Documentation

◆ CSL_dssVpEnable()

◆ CSL_dssVpSetGoBit()

◆ CSL_dssVpSetLcdTdmConfig()

◆ CSL_dssVpSetLcdLineNum()

◆ CSL_dssVpSetLcdOpTimingConfig()

◆ CSL_dssVpSetLcdBlankTiming()

◆ CSL_dssVpSetLcdAdvSignalConfig()

◆ CSL_dssVpSetLcdSignalPolarityConfig()

◆ CSL_dssVpEnableTvGamma()

◆ CSL_dssVpSetCSCCoeff()

◆ CSL_dssVpSetSafetySignSeedVal()

◆ CSL_dssVpSetSafetyReferenceSign()

◆ CSL_dssVpSetSafetyChkConfig()

◆ CSL_dssVpGetSafetySign()

◆ CSL_dssVpOldiReset()

◆ CSL_dssVpSetOldiConfig()

◆ CSL_dssVpOldiEnable()

◆ CSL_dssVpGammaCfgInit()

◆ CSL_dssVpLcdTdmCfgInit()

◆ CSL_dssVpLcdSignalPolarityCfgInit()

◆ CSL_dssVpLcdAdvSignalCfgInit()