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Data Structures
struct	Sciclient_RomFirmwareLoadHdr_t
	Header that prefixes all TISCI messages. More...

struct	tisci_sec_header
	Header that prefixes all TISCI messages sent via secure transport. More...

Macros
#define	TISCI_MSG_FLAG_RESERVED0 TISCI_BIT(0)
	This file contains: More...

#define	TISCI_MSG_FLAG_AOP TISCI_BIT(1)

#define	TISCI_MSG_FLAG_SEC TISCI_BIT(2)

#define	TISCI_MSG_FLAG_ACK TISCI_BIT(1)

#define	TISCI_MSG_VERSION (0x0002U)

#define	TISCI_MSG_BOOT_NOTIFICATION (0x000AU)

#define	TISCI_MSG_BOARD_CONFIG (0x000BU)

#define	TISCI_MSG_BOARD_CONFIG_RM (0x000CU)

#define	TISCI_MSG_BOARD_CONFIG_SECURITY (0x000DU)

#define	TISCI_MSG_BOARD_CONFIG_PM (0x000EU)

#define	TISCI_MSG_ENABLE_WDT (0x0000U)

#define	TISCI_MSG_WAKE_RESET (0x0001U)

#define	TISCI_MSG_WAKE_REASON (0x0003U)

#define	TISCI_MSG_GOODBYE (0x0004U)

#define	TISCI_MSG_SYS_RESET (0x0005U)

#define	TISCI_MSG_QUERY_MSMC (0x0020U)

#define	TISCI_MSG_GET_TRACE_CONFIG (0x0021U)

#define	TISCI_MSG_QUERY_FW_CAPS (0x0022U)

#define	TISCI_MSG_SET_CLOCK (0x0100U)

#define	TISCI_MSG_GET_CLOCK (0x0101U)

#define	TISCI_MSG_SET_CLOCK_PARENT (0x0102U)

#define	TISCI_MSG_GET_CLOCK_PARENT (0x0103U)

#define	TISCI_MSG_GET_NUM_CLOCK_PARENTS (0x0104U)

#define	TISCI_MSG_SET_FREQ (0x010cU)

#define	TISCI_MSG_QUERY_FREQ (0x010dU)

#define	TISCI_MSG_GET_FREQ (0x010eU)

#define	TISCI_MSG_SET_DEVICE (0x0200U)

#define	TISCI_MSG_GET_DEVICE (0x0201U)

#define	TISCI_MSG_SET_DEVICE_RESETS (0x0202U)

#define	TISCI_MSG_DEVICE_DROP_POWERUP_REF (0x0203U)

#define	TISCI_MSG_PREPARE_SLEEP (0x0300U)

#define	TISCI_MSG_ENTER_SLEEP (0x0301U)

#define	TISCI_MSG_SYNC_RESUME (0x0302U)

#define	TISCI_MSG_CONTINUE_RESUME (0x0303U)

#define	TISCI_MSG_CORE_RESUME (0x0304U)

#define	TISCI_MSG_ABORT_ENTER_SLEEP (0x0305U)

#define	TISCI_MSG_LPM_WAKE_REASON (0x0306U)

#define	TISCI_MSG_SET_IO_ISOLATION (0x0307U)

#define	TISCI_MSG_MIN_CONTEXT_RESTORE (0x0308U)

#define	TISCI_MSG_LPM_SET_DEVICE_CONSTRAINT (0x0309U)

#define	TISCI_MSG_LPM_SET_LATENCY_CONSTRAINT (0x030AU)

#define	TISCI_MSG_LPM_GET_DEVICE_CONSTRAINT (0x030BU)

#define	TISCI_MSG_LPM_GET_LATENCY_CONSTRAINT (0x030CU)

#define	TISCI_MSG_LPM_GET_NEXT_SYS_MODE (0x030DU)

#define	TISCI_MSG_LPM_GET_NEXT_HOST_STATE (0x030EU)

#define	TISCI_MSG_FIRMWARE_LOAD (0x8105U)

#define	MSG_FIRMWARE_LOAD_RESULT (0x8805U)

#define	TISCI_MSG_SET_FWL_REGION (0x9000U)

#define	TISCI_MSG_GET_FWL_REGION (0x9001U)

#define	TISCI_MSG_CHANGE_FWL_OWNER (0x9002U)

#define	TISCI_MSG_SA2UL_SET_DKEK (0x9003U)

#define	TISCI_MSG_SA2UL_RELEASE_DKEK (0x9004U)

#define	TISCI_MSG_KEYSTORE_IMPORT_SKEY (0x9005U)

#define	TISCI_MSG_KEYSTORE_ERASE_SKEY (0x9006U)

#define	TISCI_MSG_SEC_RESERVED_9007 (0x9007U)

#define	TISCI_MSG_SEC_RESERVED_9008 (0x9008U)

#define	TISCI_MSG_SET_ISC_REGION (0x9009U)

#define	TISCI_MSG_GET_ISC_REGION (0x900AU)

#define	TISCI_MSG_FWL_EXCP_NOTIFICATION (0x900BU)

#define	TISCI_MSG_OPEN_DEBUG_FWLS (0x900CU)

#define	TISCI_MSG_KEYSTORE_WRITE (0x900DU)

#define	TISCI_MSG_KEYSTORE_EXPORT_ALL (0x900EU)

#define	TISCI_MSG_KEYSTORE_IMPORT_ALL (0x900FU)

#define	TISCI_MSG_SEC_RESERVED_9010 (0x9010U)

#define	TISCI_MSG_SEC_RESERVED_9011 (0x9011U)

#define	TISCI_MSG_SEC_RESERVED_9012 (0x9012U)

#define	TISCI_MSG_SEC_RESERVED_9013 (0x9013U)

#define	TISCI_MSG_SEC_RESERVED_9014 (0x9014U)

#define	TISCI_MSG_SEC_RESERVED_9015 (0x9015U)

#define	TISCI_MSG_SEC_RESERVED_9016 (0x9016U)

#define	TISCI_MSG_SA2UL_AUTH_RES_ACQUIRE (0x9017U)

#define	TISCI_MSG_SA2UL_AUTH_RES_RELEASE (0x9018U)

#define	TISCI_MSG_SEC_RESERVED_9020 (0x9020U)

#define	TISCI_MSG_GET_SOC_UID (0x9021U)

#define	TISCI_MSG_READ_OTP_MMR (0x9022U)

#define	TISCI_MSG_WRITE_OTP_ROW (0x9023U)

#define	TISCI_MSG_LOCK_OTP_ROW (0x9024U)

#define	TISCI_MSG_SOFT_LOCK_OTP_WRITE_GLOBAL (0x9025U)

#define	TISCI_MSG_GET_OTP_ROW_LOCK_STATUS (0x9026U)

#define	TISCI_MSG_RSVD_OTP_1 (0x9027U)

#define	TISCI_MSG_RSVD_OTP_2 (0x9028U)

#define	TISCI_MSG_SA2UL_GET_DKEK (0x9029U)

#define	TISCI_MSG_ALLOW_FWL_CTRL_READ (0x902CU)

#define	TISCI_MSG_FORBID_FWL_CTRL_READ (0x902DU)

#define	TISCI_MSG_SEC_HANDOVER (0x9030U)

#define	TISCI_MSG_KEY_WRITER (0x9031U)

#define	TISCI_MSG_WRITE_SWREV (0x9032U)

#define	TISCI_MSG_READ_SWREV (0x9033U)

#define	TISCI_MSG_READ_KEYCNT_KEYREV (0x9034U)

#define	TISCI_MSG_WRITE_KEYREV (0x9035U)

#define	TISCI_MSG_SA2UL_GET_DSMEK (0x9036U)

#define	TISCI_MSG_SA2UL_SET_DSMEK (0x9037U)

#define	TISCI_MSG_SA2UL_RELEASE_DSMEK (0x9038U)

#define	TISCI_MSG_KEYRING_IMPORT (0X9039U)

#define	TISCI_MSG_SA2UL_SET_DKEK_CONST (0x902AU)

#define	TISCI_MSG_SA2UL_GET_DKEK_CONST (0x902BU)

#define	TISCI_MSG_SA2UL_AES_ENCRYPT (0x9040U)

#define	TISCI_MSG_SA2UL_AES_DECRYPT (0x9041U)

#define	TISCI_MSG_PROC_REQUEST (0xC000U)

#define	TISCI_MSG_PROC_RELEASE (0xC001U)

#define	TISCI_MSG_PROC_HANDOVER (0xC005U)

#define	TISCI_MSG_PROC_SET_CONFIG (0xC100U)

#define	TISCI_MSG_PROC_SET_CONTROL (0xC101U)

#define	TISCI_MSG_PROC_GET_STATUS (0xC400U)

#define	TISCI_MSG_PROC_WAIT_STATUS (0xC401U)

#define	TISCI_MSG_PROC_AUTH_BOOT (0xC120U)

#define	TISCI_MSG_RM_GET_RESOURCE_RANGE (0x1500U)

#define	TISCI_MSG_RM_IRQ_SET (0x1000U)

#define	TISCI_MSG_RM_IRQ_RELEASE (0x1001U)

#define	TISCI_MSG_RM_RESERVED_1100 (0x1100U)

#define	TISCI_MSG_RM_RESERVED_1101 (0x1101U)

#define	TISCI_MSG_RM_RESERVED_1102 (0x1102U)

#define	TISCI_MSG_RM_RESERVED_1103 (0x1103U)

#define	TISCI_MSG_RM_RING_CFG (0x1110U)

#define	TISCI_MSG_RM_RESERVED_1111 (0x1111U)

#define	TISCI_MSG_RM_RING_MON_CFG (0x1120U)

#define	TISCI_MSG_RM_RESERVED_1200 (0x1200U)

#define	TISCI_MSG_RM_RESERVED_1201 (0x1201U)

#define	TISCI_MSG_RM_UDMAP_TX_CH_CFG (0x1205U)

#define	TISCI_MSG_RM_RESERVED_1206 (0x1206U)

#define	TISCI_MSG_RM_RESERVED_1210 (0x1210U)

#define	TISCI_MSG_RM_RESERVED_1211 (0x1211U)

#define	TISCI_MSG_RM_UDMAP_RX_CH_CFG (0x1215U)

#define	TISCI_MSG_RM_RESERVED_1216 (0x1216U)

#define	TISCI_MSG_RM_RESERVED_1220 (0x1220U)

#define	TISCI_MSG_RM_RESERVED_1221 (0x1221U)

#define	TISCI_MSG_RM_UDMAP_FLOW_CFG (0x1230U)

#define	TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_CFG (0x1231U)

#define	TISCI_MSG_RM_RESERVED_1232 (0x1232U)

#define	TISCI_MSG_RM_RESERVED_1233 (0x1233U)

#define	TISCI_MSG_RM_UDMAP_FLOW_DELEGATE (0x1234U)

#define	TISCI_MSG_RM_UDMAP_GCFG_CFG (0x1240U)

#define	TISCI_MSG_RM_RESERVED_1241 (0x1241U)

#define	TISCI_MSG_RM_PSIL_PAIR (0x1280U)

#define	TISCI_MSG_RM_PSIL_UNPAIR (0x1281U)

#define	TISCI_MSG_RM_PSIL_READ (0x1282U)

#define	TISCI_MSG_RM_PSIL_WRITE (0x1283U)

#define	TISCI_MSG_RM_PROXY_CFG (0x1300U)

Data Structures

Macros