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AM62Px MCU+ SDK
10.01.00
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Go to the documentation of this file.
54 #ifndef TISCI_PROTOCOL_H
55 #define TISCI_PROTOCOL_H
67 #define TISCI_MSG_FLAG_RESERVED0 TISCI_BIT(0)
75 #define TISCI_MSG_FLAG_AOP TISCI_BIT(1)
78 #define TISCI_MSG_FLAG_SEC TISCI_BIT(2)
84 #define TISCI_MSG_FLAG_ACK TISCI_BIT(1)
129 #define TISCI_MSG_VERSION (0x0002U)
130 #define TISCI_MSG_BOOT_NOTIFICATION (0x000AU)
131 #define TISCI_MSG_BOARD_CONFIG (0x000BU)
132 #define TISCI_MSG_BOARD_CONFIG_RM (0x000CU)
133 #define TISCI_MSG_BOARD_CONFIG_SECURITY (0x000DU)
134 #define TISCI_MSG_BOARD_CONFIG_PM (0x000EU)
136 #define TISCI_MSG_ENABLE_WDT (0x0000U)
137 #define TISCI_MSG_WAKE_RESET (0x0001U)
138 #define TISCI_MSG_WAKE_REASON (0x0003U)
139 #define TISCI_MSG_GOODBYE (0x0004U)
140 #define TISCI_MSG_SYS_RESET (0x0005U)
142 #define TISCI_MSG_QUERY_MSMC (0x0020U)
143 #define TISCI_MSG_GET_TRACE_CONFIG (0x0021U)
144 #define TISCI_MSG_QUERY_FW_CAPS (0x0022U)
146 #define TISCI_MSG_SET_CLOCK (0x0100U)
147 #define TISCI_MSG_GET_CLOCK (0x0101U)
148 #define TISCI_MSG_SET_CLOCK_PARENT (0x0102U)
149 #define TISCI_MSG_GET_CLOCK_PARENT (0x0103U)
150 #define TISCI_MSG_GET_NUM_CLOCK_PARENTS (0x0104U)
151 #define TISCI_MSG_SET_FREQ (0x010cU)
152 #define TISCI_MSG_QUERY_FREQ (0x010dU)
153 #define TISCI_MSG_GET_FREQ (0x010eU)
155 #define TISCI_MSG_SET_DEVICE (0x0200U)
156 #define TISCI_MSG_GET_DEVICE (0x0201U)
157 #define TISCI_MSG_SET_DEVICE_RESETS (0x0202U)
158 #define TISCI_MSG_DEVICE_DROP_POWERUP_REF (0x0203U)
160 #define TISCI_MSG_PREPARE_SLEEP (0x0300U)
161 #define TISCI_MSG_ENTER_SLEEP (0x0301U)
167 #define TISCI_MSG_SYNC_RESUME (0x0302U)
168 #define TISCI_MSG_CONTINUE_RESUME (0x0303U)
169 #define TISCI_MSG_CORE_RESUME (0x0304U)
170 #define TISCI_MSG_ABORT_ENTER_SLEEP (0x0305U)
171 #define TISCI_MSG_LPM_WAKE_REASON (0x0306U)
172 #define TISCI_MSG_SET_IO_ISOLATION (0x0307U)
173 #define TISCI_MSG_MIN_CONTEXT_RESTORE (0x0308U)
174 #define TISCI_MSG_LPM_SET_DEVICE_CONSTRAINT (0x0309U)
175 #define TISCI_MSG_LPM_SET_LATENCY_CONSTRAINT (0x030AU)
176 #define TISCI_MSG_LPM_GET_DEVICE_CONSTRAINT (0x030BU)
177 #define TISCI_MSG_LPM_GET_LATENCY_CONSTRAINT (0x030CU)
178 #define TISCI_MSG_LPM_GET_NEXT_SYS_MODE (0x030DU)
179 #define TISCI_MSG_LPM_GET_NEXT_HOST_STATE (0x030EU)
181 #define TISCI_MSG_FIRMWARE_LOAD (0x8105U)
182 #define MSG_FIRMWARE_LOAD_RESULT (0x8805U)
185 #define TISCI_MSG_SET_FWL_REGION (0x9000U)
187 #define TISCI_MSG_GET_FWL_REGION (0x9001U)
189 #define TISCI_MSG_CHANGE_FWL_OWNER (0x9002U)
191 #define TISCI_MSG_SA2UL_SET_DKEK (0x9003U)
193 #define TISCI_MSG_SA2UL_RELEASE_DKEK (0x9004U)
195 #define TISCI_MSG_KEYSTORE_IMPORT_SKEY (0x9005U)
197 #define TISCI_MSG_KEYSTORE_ERASE_SKEY (0x9006U)
199 #define TISCI_MSG_SEC_RESERVED_9007 (0x9007U)
201 #define TISCI_MSG_SEC_RESERVED_9008 (0x9008U)
203 #define TISCI_MSG_SET_ISC_REGION (0x9009U)
205 #define TISCI_MSG_GET_ISC_REGION (0x900AU)
207 #define TISCI_MSG_FWL_EXCP_NOTIFICATION (0x900BU)
209 #define TISCI_MSG_OPEN_DEBUG_FWLS (0x900CU)
214 #define TISCI_MSG_KEYSTORE_WRITE (0x900DU)
219 #define TISCI_MSG_KEYSTORE_EXPORT_ALL (0x900EU)
221 #define TISCI_MSG_KEYSTORE_IMPORT_ALL (0x900FU)
223 #define TISCI_MSG_SEC_RESERVED_9010 (0x9010U)
225 #define TISCI_MSG_SEC_RESERVED_9011 (0x9011U)
227 #define TISCI_MSG_SEC_RESERVED_9012 (0x9012U)
229 #define TISCI_MSG_SEC_RESERVED_9013 (0x9013U)
231 #define TISCI_MSG_SEC_RESERVED_9014 (0x9014U)
233 #define TISCI_MSG_SEC_RESERVED_9015 (0x9015U)
236 #define TISCI_MSG_SEC_RESERVED_9016 (0x9016U)
239 #define TISCI_MSG_SA2UL_AUTH_RES_ACQUIRE (0x9017U)
242 #define TISCI_MSG_SA2UL_AUTH_RES_RELEASE (0x9018U)
245 #define TISCI_MSG_SEC_RESERVED_9020 (0x9020U)
248 #define TISCI_MSG_GET_SOC_UID (0x9021U)
254 #define TISCI_MSG_READ_OTP_MMR (0x9022U)
257 #define TISCI_MSG_WRITE_OTP_ROW (0x9023U)
260 #define TISCI_MSG_LOCK_OTP_ROW (0x9024U)
263 #define TISCI_MSG_SOFT_LOCK_OTP_WRITE_GLOBAL (0x9025U)
266 #define TISCI_MSG_GET_OTP_ROW_LOCK_STATUS (0x9026U)
269 #define TISCI_MSG_RSVD_OTP_1 (0x9027U)
272 #define TISCI_MSG_RSVD_OTP_2 (0x9028U)
275 #define TISCI_MSG_SA2UL_GET_DKEK (0x9029U)
278 #define TISCI_MSG_ALLOW_FWL_CTRL_READ (0x902CU)
281 #define TISCI_MSG_FORBID_FWL_CTRL_READ (0x902DU)
286 #define TISCI_MSG_SEC_HANDOVER (0x9030U)
291 #define TISCI_MSG_KEY_WRITER (0x9031U)
294 #define TISCI_MSG_WRITE_SWREV (0x9032U)
297 #define TISCI_MSG_READ_SWREV (0x9033U)
300 #define TISCI_MSG_READ_KEYCNT_KEYREV (0x9034U)
303 #define TISCI_MSG_WRITE_KEYREV (0x9035U)
306 #define TISCI_MSG_SA2UL_GET_DSMEK (0x9036U)
309 #define TISCI_MSG_SA2UL_SET_DSMEK (0x9037U)
312 #define TISCI_MSG_SA2UL_RELEASE_DSMEK (0x9038U)
315 #define TISCI_MSG_KEYRING_IMPORT (0X9039U)
318 #define TISCI_MSG_SA2UL_SET_DKEK_CONST (0x902AU)
321 #define TISCI_MSG_SA2UL_GET_DKEK_CONST (0x902BU)
324 #define TISCI_MSG_SA2UL_AES_ENCRYPT (0x9040U)
327 #define TISCI_MSG_SA2UL_AES_DECRYPT (0x9041U)
332 #define TISCI_MSG_PROC_REQUEST (0xC000U)
334 #define TISCI_MSG_PROC_RELEASE (0xC001U)
336 #define TISCI_MSG_PROC_HANDOVER (0xC005U)
339 #define TISCI_MSG_PROC_SET_CONFIG (0xC100U)
341 #define TISCI_MSG_PROC_SET_CONTROL (0xC101U)
344 #define TISCI_MSG_PROC_GET_STATUS (0xC400U)
347 #define TISCI_MSG_PROC_WAIT_STATUS (0xC401U)
350 #define TISCI_MSG_PROC_AUTH_BOOT (0xC120U)
357 #define TISCI_MSG_RM_GET_RESOURCE_RANGE (0x1500U)
361 #define TISCI_MSG_RM_IRQ_SET (0x1000U)
365 #define TISCI_MSG_RM_IRQ_RELEASE (0x1001U)
367 #define TISCI_MSG_RM_RESERVED_1100 (0x1100U)
369 #define TISCI_MSG_RM_RESERVED_1101 (0x1101U)
371 #define TISCI_MSG_RM_RESERVED_1102 (0x1102U)
373 #define TISCI_MSG_RM_RESERVED_1103 (0x1103U)
377 #define TISCI_MSG_RM_RING_CFG (0x1110U)
379 #define TISCI_MSG_RM_RESERVED_1111 (0x1111U)
383 #define TISCI_MSG_RM_RING_MON_CFG (0x1120U)
385 #define TISCI_MSG_RM_RESERVED_1200 (0x1200U)
387 #define TISCI_MSG_RM_RESERVED_1201 (0x1201U)
391 #define TISCI_MSG_RM_UDMAP_TX_CH_CFG (0x1205U)
393 #define TISCI_MSG_RM_RESERVED_1206 (0x1206U)
395 #define TISCI_MSG_RM_RESERVED_1210 (0x1210U)
397 #define TISCI_MSG_RM_RESERVED_1211 (0x1211U)
401 #define TISCI_MSG_RM_UDMAP_RX_CH_CFG (0x1215U)
402 #define TISCI_MSG_RM_RESERVED_1216 (0x1216U)
404 #define TISCI_MSG_RM_RESERVED_1220 (0x1220U)
406 #define TISCI_MSG_RM_RESERVED_1221 (0x1221U)
410 #define TISCI_MSG_RM_UDMAP_FLOW_CFG (0x1230U)
415 #define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_CFG (0x1231U)
417 #define TISCI_MSG_RM_RESERVED_1232 (0x1232U)
419 #define TISCI_MSG_RM_RESERVED_1233 (0x1233U)
423 #define TISCI_MSG_RM_UDMAP_FLOW_DELEGATE (0x1234U)
428 #define TISCI_MSG_RM_UDMAP_GCFG_CFG (0x1240U)
430 #define TISCI_MSG_RM_RESERVED_1241 (0x1241U)
434 #define TISCI_MSG_RM_PSIL_PAIR (0x1280U)
438 #define TISCI_MSG_RM_PSIL_UNPAIR (0x1281U)
442 #define TISCI_MSG_RM_PSIL_READ (0x1282U)
446 #define TISCI_MSG_RM_PSIL_WRITE (0x1283U)
451 #define TISCI_MSG_RM_PROXY_CFG (0x1300U)