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Macros | |
#define | TISCI_HOST_ID_TIFS (0U) |
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#define | TISCI_HOST_ID_DM (254U) |
#define | TISCI_HOST_ID_WKUP_0_R5_0 (35U) |
#define | TISCI_HOST_ID_WKUP_0_R5_1 (36U) |
#define | TISCI_HOST_ID_GPU_0 (31U) |
#define | TISCI_HOST_ID_GPU_1 (32U) |
#define | TISCI_HOST_ID_A53_0 (10U) |
#define | TISCI_HOST_ID_A53_1 (11U) |
#define | TISCI_HOST_ID_A53_2 (12U) |
#define | TISCI_HOST_ID_A53_3 (13U) |
#define | TISCI_HOST_ID_A53_4 (14U) |
#define | TISCI_HOST_ID_MCU_0_R5_0 (30U) |
#define | TISCI_HOST_ID_DM2TIFS (250U) |
#define | TISCI_HOST_ID_TIFS2DM (251U) |
#define | TISCI_HOST_ID_HSM (253U) |
#define | TISCI_HOST_ID_ALL (128U) |
#define | TISCI_HOST_ID_CNT (15U) |