|
AM62Px MCU+ SDK
09.02.01
|
|
Go to the documentation of this file.
48 #ifndef CSL_DSSVIDEOPORT_H_
49 #define CSL_DSSVIDEOPORT_H_
80 #define CSL_DSS_VP_CSC_POS_AFTER_GAMMA \
81 ((uint32_t) CSL_DSS_VP1_CONFIG_COLORCONVPOS_VAL_AFTERGAMMA)
83 #define CSL_DSS_VP_CSC_POS_BEFORE_GAMMA \
84 ((uint32_t) CSL_DSS_VP1_CONFIG_COLORCONVPOS_VAL_BEFOREGAMMA)
95 #define CSL_DSS_VP_TDM_UNUSED_BITS_LEVEL_LOW \
96 ((uint32_t) CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_VAL_LOWLEVEL)
98 #define CSL_DSS_VP_TDM_UNUSED_BITS_LEVEL_HIGH \
99 ((uint32_t) CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_VAL_HIGHLEVEL)
101 #define CSL_DSS_VP_TDM_UNUSED_BITS_LEVEL_UNCHANGED \
102 ((uint32_t) CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_VAL_UNCHANGED)
112 #define CSL_DSS_VP_TDM_CYCLE_1PERPIXEL \
113 ((uint32_t) CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_1CYCPERPIX)
115 #define CSL_DSS_VP_TDM_CYCLE_2PERPIXEL \
116 ((uint32_t) CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_2CYCPERPIX)
118 #define CSL_DSS_VP_TDM_CYCLE_3PERPIXEL \
119 ((uint32_t) CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_3CYCPERPIX)
121 #define CSL_DSS_VP_TDM_CYCLE_3PER2PIXEL \
122 ((uint32_t) CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_3CYCPER2PIX)
132 #define CSL_DSS_VP_TDM_PARALLEL_OUTPUT_8BIT \
133 ((uint32_t) CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_8BPARAINT)
135 #define CSL_DSS_VP_TDM_PARALLEL_OUTPUT_9BIT \
136 ((uint32_t) CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_9BPARAINT)
138 #define CSL_DSS_VP_TDM_PARALLEL_OUTPUT_12BIT \
139 ((uint32_t) CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_12BPARAINT)
141 #define CSL_DSS_VP_TDM_PARALLEL_OUTPUT_16BIT \
142 ((uint32_t) CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_16BPARAINT)
152 #define CSL_DSS_VP_HVSYNC_NOT_ALIGNED \
153 ((uint32_t) CSL_DSS_VP1_POL_FREQ_ALIGN_VAL_NOTALIGNED)
155 #define CSL_DSS_VP_HVSYNC_ALIGNED \
156 ((uint32_t) CSL_DSS_VP1_POL_FREQ_ALIGN_VAL_ALIGNED)
167 #define CSL_DSS_VP_HVCLK_CONTROL_OFF \
168 ((uint32_t) CSL_DSS_VP1_POL_FREQ_ONOFF_VAL_DOPEDPCK)
170 #define CSL_DSS_VP_HVCLK_CONTROL_ON \
171 ((uint32_t) CSL_DSS_VP1_POL_FREQ_ONOFF_VAL_DBIT16)
182 #define CSL_DSS_VP_LPP_DELTA_ZERO \
183 ((uint32_t) CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_VAL_SAME)
185 #define CSL_DSS_VP_LPP_DELTA_PLUSONE \
186 ((uint32_t) CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_VAL_PLUSONE)
188 #define CSL_DSS_VP_LPP_DELTA_MINUSONE \
189 ((uint32_t) CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_VAL_MINUSONE)
200 #define CSL_DSS_VP_FID_FIRST_EVEN \
201 ((uint32_t) CSL_DSS_VP1_CONFIG_FIDFIRST_VAL_EVEN)
203 #define CSL_DSS_VP_FID_FIRST_ODD \
204 ((uint32_t) CSL_DSS_VP1_CONFIG_FIDFIRST_VAL_ODD)
214 #define CSL_DSS_VP_SAFETY_REGION_0 ((uint32_t) 0x0U)
216 #define CSL_DSS_VP_SAFETY_REGION_1 ((uint32_t) 0x1U)
218 #define CSL_DSS_VP_SAFETY_REGION_2 ((uint32_t) 0x2U)
220 #define CSL_DSS_VP_SAFETY_REGION_3 ((uint32_t) 0x3U)
222 #define CSL_DSS_VP_SAFETY_REGION_MAX ((uint32_t) 0x4U)
224 #define CSL_DSS_VP_SAFETY_REGION_INVALID ((uint32_t) 0xFFU)
235 #define CSL_DSS_VP_OLDI_MAP_TYPE_A \
236 ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_A)
238 #define CSL_DSS_VP_OLDI_MAP_TYPE_B \
239 ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_B)
241 #define CSL_DSS_VP_OLDI_MAP_TYPE_C \
242 ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_C)
244 #define CSL_DSS_VP_OLDI_MAP_TYPE_D \
245 ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_D)
247 #define CSL_DSS_VP_OLDI_MAP_TYPE_E \
248 ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_E)
250 #define CSL_DSS_VP_OLDI_MAP_TYPE_F \
251 ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_F)
265 #define CSL_DSS_VP_OLDI_BIT_DEPTH_18_BITS \
266 ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_MSB_VAL_18B)
268 #define CSL_DSS_VP_OLDI_BIT_DEPTH_24_BITS \
269 ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_MSB_VAL_24B)
280 #define CSL_DSS_VP_OLDI_DUALMODESYNC_ENABLE \
281 ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_DUALMODESYNC_VAL_ENABLE)
283 #define CSL_DSS_VP_OLDI_DUALMODESYNC_DISABLE \
284 ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_DUALMODESYNC_VAL_DISABLE)
666 uint32_t isCustomTiming);
734 uint32_t signSeedVal);
747 uint32_t referenceSign,
921 if(
NULL != polarityCfg)
933 if(
NULL != advSignalCfg)
938 advSignalCfg->
acBI = 0x0U;
939 advSignalCfg->
acB = 0x0U;
uint32_t deltaLinesPerPanel
Definition: csl_dssVideoPort.h:512
int32_t CSL_dssVpSetLcdOpTimingConfig(CSL_dss_vpRegs *vpRegs, const CSL_DssVpLcdOpTimingCfg *lcdCfg)
Configure the LCD Timing parameters.
uint32_t hSyncGated
Definition: csl_dssVideoPort.h:408
static void CSL_dssVpLcdSignalPolarityCfgInit(CSL_DssVpLcdSignalPolarityCfg *polarityCfg)
CSL_DssVpLcdSignalPolarityCfg structure init function.
Definition: csl_dssVideoPort.h:918
uint32_t bitAlignPixel2Cycle1
Definition: csl_dssVideoPort.h:352
uint32_t videoIfWidth
Definition: csl_dssVideoPort.h:503
Configuration for doing safety checks.
Definition: csl_dssTop.h:260
uint32_t tdmEnable
Definition: csl_dssVideoPort.h:309
#define CSL_DSS_VP_FID_FIRST_EVEN
First field is even.
Definition: csl_dssVideoPort.h:200
void CSL_dssVpOldiEnable(CSL_dss_vpRegs *vpRegs, uint32_t enable)
Enable/disable the OLDI Module.
uint32_t vsPolarity
Definition: csl_dssVideoPort.h:375
void CSL_dssVpSetGoBit(CSL_dss_vpRegs *vpRegs)
GO Command for the VP output. It is used to synchronize the pipelines associated with the VP output.
uint32_t fidFirst
Definition: csl_dssVideoPort.h:515
Timing configuration for the LCD output.
Definition: csl_dssVideoPort.h:431
Gamma Correction configuration for DSS Video Port Output.
Definition: csl_dssVideoPort.h:295
void CSL_dssVpSetCSCCoeff(CSL_dss_vpRegs *vpRegs, const CSL_DssCscCoeff *cscCoeff, uint32_t cscPos, uint32_t cscEnable)
Configure the coefficients for Color Space Conversion.
uint32_t numBitsPixel2Cycle1
Definition: csl_dssVideoPort.h:343
uint32_t CSL_dssVpGetSafetySign(const CSL_dss_vpRegs *vpRegs, uint32_t regionId)
Get the Safety Signature of the sub region.
uint32_t hFrontPorch
Definition: csl_dssVideoPort.h:526
void CSL_dssVpEnableTvGamma(CSL_dss_vpRegs *vpRegs, const CSL_DssVpGammaCfg *gammaCfg)
Enable/Bypass TV Gamma Table.
#define FVID2_DV_GENERIC_DISCSYNC
Video format is for any discrete sync.
Definition: fvid2_dataTypes.h:230
uint32_t numBitsPixel1Cycle1
Definition: csl_dssVideoPort.h:325
uint32_t pixelGated
Definition: csl_dssVideoPort.h:420
Structure containing coefficients for Color Space Conversion.
Definition: csl_dssTop.h:220
#define CSL_DSS_CSC_RANGE_FULL
Full range selected.
Definition: csl_dssTop.h:168
void CSL_dssVpOldiReset(const CSL_dss_vpRegs *vpRegs)
Reset the OLDI Module.
Blanking Timing parameters for the LCD.
Definition: csl_dssVideoPort.h:525
#define FVID2_EDGE_POL_FALLING
Falling Edge.
Definition: fvid2_dataTypes.h:819
OLDI Configuration.
Definition: csl_dssVideoPort.h:569
#define NULL
Define NULL if not defined.
Definition: csl_types.h:100
#define CSL_DSS_VP_TDM_CYCLE_1PERPIXEL
1 cycle per pixel
Definition: csl_dssVideoPort.h:112
static void CSL_dssVpLcdBlankTimingCfgInit(CSL_DssVpLcdBlankTimingCfg *blankCfg)
CSL_DssVpLcdBlankTimingCfg structure init function.
Definition: csl_dssVideoPort.h:962
void CSL_dssVpSetSafetyReferenceSign(CSL_dss_vpRegs *vpRegs, uint32_t referenceSign, uint32_t regionId)
Set the reference safety signature for data correctness check.
static void CSL_dssVpOldiCfgInit(CSL_DssVpOldiCfg *oldiCfg)
CSL_DssVpOldiCfg structure init function.
Definition: csl_dssVideoPort.h:976
uint32_t hVAlign
Definition: csl_dssVideoPort.h:385
Definition: cslr_dss.h:4274
static void Fvid2ModeInfo_init(Fvid2_ModeInfo *modeInfo)
Fvid2_ModeInfo structure init function. This defaults to 1080p60.
Definition: fvid2_dataTypes.h:2273
uint32_t pixelClockGated
Definition: csl_dssVideoPort.h:412
int32_t CSL_dssVpSetLcdBlankTiming(CSL_dss_vpRegs *vpRegs, const CSL_DssVpLcdBlankTimingCfg *blankCfg, uint32_t dvoFormat, uint32_t scanFormat, uint32_t isCustomTiming)
Configure the LCD Blank Timing parameters.
void CSL_dssVpSetLcdTdmConfig(CSL_dss_vpRegs *vpRegs, const CSL_DssVpLcdTdmCfg *lcdTdmCfg)
Configure the LCD TDM(Time division multiplexing) parameters.
uint32_t oldiMapType
Definition: csl_dssVideoPort.h:570
void CSL_dssVpSetSafetySignSeedVal(CSL_dss_vpRegs *vpRegs, uint32_t signSeedVal)
Set the seed value for the signature calculation.
#define CSL_DSS_VP_HVSYNC_NOT_ALIGNED
HSYNC and VSYNC are not aligned.
Definition: csl_dssVideoPort.h:152
#define CSL_DSS_VP_HVCLK_CONTROL_OFF
HSYNC and VSYNC are driven on opposite edges of the pixel clock than pixel data.
Definition: csl_dssVideoPort.h:167
uint32_t vBackPorch
Definition: csl_dssVideoPort.h:549
Polarity of Active Video, Pixel Clock, HSync and VSync signals for the LCD.
Definition: csl_dssVideoPort.h:365
#define FVID2_VIFW_12BIT
12-bit interface.
Definition: fvid2_dataTypes.h:941
void CSL_dssVpSetLcdSignalPolarityConfig(CSL_dss_vpRegs *vpRegs, const CSL_DssVpLcdSignalPolarityCfg *polarityCfg)
Configure the Polarity of LCD signals(HSYNC, VSYNC, PCLK, Data)
uint32_t hsPolarity
Definition: csl_dssVideoPort.h:372
uint32_t bitAlignPixel1Cycle0
Definition: csl_dssVideoPort.h:331
uint32_t tdmCycleFormat
Definition: csl_dssVideoPort.h:316
static void CSL_dssVpLcdTdmCfgInit(CSL_DssVpLcdTdmCfg *tdmCfg)
CSL_DssVpLcdTdmCfg structure init function.
Definition: csl_dssVideoPort.h:894
#define CSL_DSS_NUM_LUT_ENTRIES
Number of entries for CLUT/Gamma Correction.
Definition: csl_dssTop.h:207
uint32_t acB
Definition: csl_dssVideoPort.h:398
uint32_t acBI
Definition: csl_dssVideoPort.h:394
uint32_t hVClkControl
Definition: csl_dssVideoPort.h:388
uint32_t dualModeSync
Definition: csl_dssVideoPort.h:578
void CSL_dssVpSetOldiConfig(CSL_dss_vpRegs *vpRegs, const CSL_DssVpOldiCfg *oldiCfg)
Set the OLDI configuration.
FVID2 Mode information structure.
Definition: fvid2_dataTypes.h:1307
uint32_t cscRange
Definition: csl_dssVideoPort.h:501
#define CSL_DSS_VP_OLDI_MAP_TYPE_C
Map Type C is Single Link 24 bit VESA.
Definition: csl_dssVideoPort.h:241
uint32_t numBitsPixel2Cycle0
Definition: csl_dssVideoPort.h:340
#define CSL_DSS_VP_OLDI_BIT_DEPTH_24_BITS
Input RGB data's bit depth is 24.
Definition: csl_dssVideoPort.h:268
uint32_t dvoFormat
Definition: csl_dssVideoPort.h:499
void CSL_dssVpSetLcdAdvSignalConfig(CSL_dss_vpRegs *vpRegs, const CSL_DssVpLcdAdvSignalCfg *advSignalCfg)
Configure the advance LCD Signal parameters.
void CSL_dssVpSetLcdLineNum(CSL_dss_vpRegs *vpRegs, uint32_t lineNum)
Set the Line Number at which the interrupt should be generated.
uint32_t bitAlignPixel2Cycle0
Definition: csl_dssVideoPort.h:349
uint32_t numBitsPixel1Cycle0
Definition: csl_dssVideoPort.h:322
uint32_t bitAlignPixel2Cycle2
Definition: csl_dssVideoPort.h:355
uint32_t vFrontPorch
Definition: csl_dssVideoPort.h:543
uint32_t gammaEnable
Definition: csl_dssVideoPort.h:296
uint32_t hSyncLen
Definition: csl_dssVideoPort.h:538
#define CSL_DSS_VP_LPP_DELTA_ZERO
Odd field has same size as even.
Definition: csl_dssVideoPort.h:182
uint32_t dataEnablePolarity
Definition: csl_dssVideoPort.h:572
uint32_t numBitsPixel1Cycle2
Definition: csl_dssVideoPort.h:328
#define CSL_DSS_VP_TDM_PARALLEL_OUTPUT_8BIT
8-bit parallel output interface selected
Definition: csl_dssVideoPort.h:132
#define CSL_DSS_VP_OLDI_DUALMODESYNC_DISABLE
Disable dual mode operation.
Definition: csl_dssVideoPort.h:283
void CSL_dssVpSetSafetyChkConfig(CSL_dss_vpRegs *vpRegs, const CSL_DssSafetyChkCfg *safetyCfg, uint32_t regionId)
Configure the Safety Check parameters.
#define FVID2_POL_HIGH
High Polarity.
Definition: fvid2_dataTypes.h:804
static void CSL_dssVpLcdAdvSignalCfgInit(CSL_DssVpLcdAdvSignalCfg *advSignalCfg)
CSL_DssVpLcdAdvSignalCfg structure init function.
Definition: csl_dssVideoPort.h:930
#define FVID2_EDGE_POL_RISING
Rising Edge.
Definition: fvid2_dataTypes.h:817
uint32_t tdmParallelMode
Definition: csl_dssVideoPort.h:319
uint32_t gammaData[CSL_DSS_NUM_LUT_ENTRIES]
Definition: csl_dssVideoPort.h:300
uint32_t vSyncLen
Definition: csl_dssVideoPort.h:556
static void CSL_dssVpGammaCfgInit(CSL_DssVpGammaCfg *gammaCfg)
CSL_DssVpGammaCfg structure init function.
Definition: csl_dssVideoPort.h:880
void CSL_dssVpEnable(CSL_dss_vpRegs *vpRegs, uint32_t enable)
Enable the DSS Video Port.
Fvid2_ModeInfo mInfo
Definition: csl_dssVideoPort.h:432
uint32_t dssBitDepth
Definition: csl_dssVideoPort.h:575
#define CSL_DSS_VP_TDM_UNUSED_BITS_LEVEL_LOW
Low level.
Definition: csl_dssVideoPort.h:95
static void CSL_dssVpLcdOpTimingCfgInit(CSL_DssVpLcdOpTimingCfg *lcdCfg)
CSL_DssVpLcdOpTimingCfg structure init function.
Definition: csl_dssVideoPort.h:948
uint32_t pixelClkPolarity
Definition: csl_dssVideoPort.h:369
uint32_t vSyncGated
Definition: csl_dssVideoPort.h:404
uint32_t bitAlignPixel1Cycle2
Definition: csl_dssVideoPort.h:337
uint32_t hBackPorch
Definition: csl_dssVideoPort.h:532
Advance Signal Configuration for the LCD.
Definition: csl_dssVideoPort.h:384
uint32_t tdmUnusedBitsLevel
Definition: csl_dssVideoPort.h:313
uint32_t actVidPolarity
Definition: csl_dssVideoPort.h:366
uint32_t bitAlignPixel1Cycle1
Definition: csl_dssVideoPort.h:334
LCD Configuration for Time Division Multiplexing.
Definition: csl_dssVideoPort.h:308
uint32_t numBitsPixel2Cycle2
Definition: csl_dssVideoPort.h:346
#define FALSE
Definition: csl_types.h:62
uint32_t pixelDataGated
Definition: csl_dssVideoPort.h:416
CSL_dss_vp1Regs CSL_dss_vpRegs
DSS Video Port Registers.
Definition: csl_dssVideoPort.h:70
uint32_t hVClkRiseFall
Definition: csl_dssVideoPort.h:391