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AM62Px MCU+ SDK
09.01.00
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41 #ifndef SCICLIENT_FMWMSGPARAMS_H_
42 #define SCICLIENT_FMWMSGPARAMS_H_
59 #define TISCI_PARAM_UNDEF (0xFFFFFFFFU)
69 #define SCICLIENT_FIRMWARE_ABI_MAJOR (3U)
74 #define SCICLIENT_FIRMWARE_ABI_MINOR (5U)
84 #define SCICLIENT_CONTEXT_R5_SEC_0 (0U)
86 #define SCICLIENT_CONTEXT_R5_NONSEC_0 (1U)
88 #define SCICLIENT_CONTEXT_GPU_NONSEC_0 (2U)
90 #define SCICLIENT_CONTEXT_GPU_NONSEC_1 (3U)
92 #define SCICLIENT_CONTEXT_A53_SEC_0 (4U)
94 #define SCICLIENT_CONTEXT_A53_SEC_1 (5U)
96 #define SCICLIENT_CONTEXT_A53_NONSEC_1 (6U)
98 #define SCICLIENT_CONTEXT_A53_NONSEC_2 (7U)
100 #define SCICLIENT_CONTEXT_A53_NONSEC_3 (8U)
102 #define SCICLIENT_CONTEXT_MCU_R5_0_NONSEC_0 (9U)
105 #define SCICLIENT_CONTEXT_MAX_NUM (10U)
117 #define SCICLIENT_PROC_ID_A53SS0_CORE_0 (0x20U)
122 #define SCICLIENT_PROC_ID_A53SS0_CORE_1 (0x21U)
127 #define SCICLIENT_PROC_ID_A53SS0_CORE_2 (0x22U)
132 #define SCICLIENT_PROC_ID_A53SS0_CORE_3 (0x23U)
137 #define SCICLIENT_PROC_ID_MCU_R5FSS0_CORE0 (0x03U)
142 #define SCICLIENT_PROC_ID_WKUP_R5FSS0_CORE0 (0x01U)
147 #define SCICLIENT_PROC_ID_HSM_M4FSS0_CORE0 (0x80U)
152 #define SOC_NUM_SCICLIENT_PROCESSORS (0x07U)
158 #define TISCI_MSG_VALUE_RM_NULL_RING_TYPE (0xFFFFu)
159 #define TISCI_MSG_VALUE_RM_NULL_RING_INDEX (0xFFFFFFFFu)
160 #define TISCI_MSG_VALUE_RM_NULL_RING_ADDR (0xFFFFFFFFu)
161 #define TISCI_MSG_VALUE_RM_NULL_RING_COUNT (0xFFFFFFFFu)
167 #define TISCI_MSG_VALUE_RM_NULL_RING_MODE (0xFFu)
168 #define TISCI_MSG_VALUE_RM_NULL_RING_SIZE (0xFFu)
169 #define TISCI_MSG_VALUE_RM_NULL_ORDER_ID (0xFFu)
170 #define TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_TYPE (0xFFu)
171 #define TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_INDEX (0xFFFFFFFFu)
199 #define SCICLIENT_DEV_MCU_R5FSS0_CORE0 (TISCI_DEV_WKUP_R5FSS0_CORE0)
200 #define SCICLIENT_DEV_MCU_R5FSS0_CORE1 (TISCI_DEV_WKUP_R5FSS0_CORE0)
206 #define TISCI_ISC_CC_ID (160U)
215 #define TISCI_RINGACC0_OES_IRQ_SRC_IDX_START (0U)
216 #define TISCI_RINGACC0_MON_IRQ_SRC_IDX_START (1024U)
217 #define TISCI_RINGACC0_EOES_IRQ_SRC_IDX_START (2048U)
218 #define TISCI_UDMAP0_TX_OES_IRQ_SRC_IDX_START (0U)
219 #define TISCI_UDMAP0_TX_EOES_IRQ_SRC_IDX_START (512U)
220 #define TISCI_UDMAP0_RX_OES_IRQ_SRC_IDX_START (1024U)
221 #define TISCI_UDMAP0_RX_EOES_IRQ_SRC_IDX_START (1280U)
222 #define TISCI_UDMAP0_RX_FLOW_EOES_IRQ_SRC_IDX_START (1536U)
223 #define TISCI_BCDMA0_BC_RC_OES_IRQ_SRC_IDX_START (9216U)
224 #define TISCI_BCDMA0_TX_RC_OES_IRQ_SRC_IDX_START (10752U)
225 #define TISCI_BCDMA0_RX_RC_OES_IRQ_SRC_IDX_START (12288U)
226 #define TISCI_BCDMA0_BC_DC_OES_IRQ_SRC_IDX_START (8704U)
227 #define TISCI_BCDMA0_TX_DC_OES_IRQ_SRC_IDX_START (10240U)
228 #define TISCI_BCDMA0_RX_DC_OES_IRQ_SRC_IDX_START (11776U)
229 #define TISCI_PKTDMA0_TX_FLOW_OES_IRQ_SRC_IDX_START (4608U)
230 #define TISCI_PKTDMA0_RX_FLOW_OES_IRQ_SRC_IDX_START (5632U)
239 #define SCICLIENT_DEV_MCU_R5FSS0_CORE0_PROCID \
240 (SCICLIENT_PROC_ID_WKUP_R5FSS0_CORE0)
241 #define SCICLIENT_DEV_MCU_R5FSS0_CORE1_PROCID \
242 (SCICLIENT_PROC_ID_WKUP_R5FSS0_CORE0)
246 #define SCICLIENT_ALLOWED_BOARDCFG_BASE_START 1
248 #define SCICLIENT_ALLOWED_BOARDCFG_BASE_END 0xFFFFFFFF