Introduction

UDMA Low Level Driver AM62Lx SOC specific file.

Macros
#define	UDMA_NUM_MAPPED_TX_GROUP (2U)
	Number of Mapped TX Group. More...

#define	UDMA_NUM_MAPPED_RX_GROUP (2U)
	Number of Mapped RX Group. More...

#define	UDMA_PSIL_DEST_THREAD_OFFSET (0x8000U)
	Destination thread offset. More...

UDMA Instance ID specific to SOC
UDMA instance ID - BCDMA/PKTDMA
#define	UDMA_INST_ID_BCDMA_0 (UDMA_INST_ID_2)
	BCDMA instance. More...

#define	UDMA_INST_ID_PKTDMA_0 (UDMA_INST_ID_3)
	PKTDMA instance. More...

#define	UDMA_INST_ID_START (UDMA_INST_ID_2)
	Start of UDMA instance. More...

#define	UDMA_INST_ID_MAX (UDMA_INST_ID_3)
	Maximum number of UDMA instance. More...

#define	UDMA_NUM_INST_ID (UDMA_INST_ID_MAX - UDMA_INST_ID_START + 1U)
	Total number of UDMA instances. More...

#define	UDMA_SOC_TOTAL_CHAN_NUM (79U)
	Number of pktdma and bcdma PDMA channels. More...

#define	UDMA_SOC_PKTDMA_TOTAL_TX_RX_CHAN (97U)
	Number of pktdma and bcdma PDMA channels. More...

#define	UDMA_SOC_BCDMA_TOTAL_TX_RX_CHAN (82U)
	Number of pktdma and bcdma PDMA channels. More...

#define	UDMA_SOC_MAX_TIMEOUT (1U * 1000U) /1ms/
	Autopair Maximum timeout value. More...

UDMA SOC Configuration
UDMA Soc Cfg - Flags to indicate the presnce of various SOC specific modules.
#define	UDMA_SOC_CFG_LCDMA_PRESENT (1U)
	Flag to indicate LCDMA module is present or not in the SOC. More...

#define	UDMA_SOC_CFG_RA_LCDMA_PRESENT (1U)
	Flag to indicate LCDMA RA is present or not in the SOC. More...

#define	UDMA_SOC_CFG_UDMAP_PRESENT (0U)

#define	UDMA_SOC_CFG_PROXY_PRESENT (0U)
	Flag to indicate Proxy is present or not in the SOC. More...

#define	UDMA_SOC_CFG_CLEC_PRESENT (0U)
	Flag to indicate Clec is present or not in the SOC. More...

#define	UDMA_SOC_CFG_RA_NORMAL_PRESENT (0U)
	Flag to indicate Normal RA is present or not in the SOC. More...

#define	UDMA_SOC_CFG_RING_MON_PRESENT (0U)
	Flag to indicate Ring Monitor is present or not in the SOC. More...

#define	UDMA_SOC_CFG_APPLY_RING_WORKAROUND (0U)
	Flag to indicate the SOC needs ring reset workaround. More...

UDMA Tx Channels FDEPTH
UDMA Tx Ch Fdepth - Fdepth of various types of channels present in the SOC.
#define	UDMA_TX_UHC_CHANS_FDEPTH (0U)
	Tx Ultra High Capacity Channel FDEPTH. More...

#define	UDMA_TX_HC_CHANS_FDEPTH (0U)
	Tx High Capacity Channel FDEPTH. More...

#define	UDMA_TX_CHANS_FDEPTH (192U)
	Tx Normal Channel FDEPTH. More...

UDMA Ringacc address select (asel) endpoint
List of all valid address select (asel) endpoints in the SOC.
#define	UDMA_RINGACC_ASEL_ENDPOINT_PHYSADDR ((uint32_t) 0U)
	Physical address (normal) More...

#define	UDMA_RINGACC_ASEL_ENDPOINT_PCIE0 ((uint32_t) 1U)
	PCIE0. More...

#define	UDMA_RINGACC_ASEL_ENDPOINT_ACP_WR_ALLOC ((uint32_t) 14U)
	ARM ACP port: write-allocate cacheable, bufferable. More...

#define	UDMA_RINGACC_ASEL_ENDPOINT_ACP_RD_ALLOC ((uint32_t) 15U)
	ARM ACP port: read-allocate, cacheable, bufferable. More...

Mapped TX Group specific to a SOC
List of all mapped TX groups present in the SOC.
#define	UDMA_MAPPED_TX_GROUP_CPSW (UDMA_MAPPED_GROUP0)

#define	UDMA_MAPPED_TX_GROUP_DTHE (UDMA_MAPPED_GROUP1)

Mapped RX Group specific to a SOC
List of all mapped RX groups present in the SOC.
#define	UDMA_MAPPED_RX_GROUP_CPSW (UDMA_MAPPED_GROUP2)

#define	UDMA_MAPPED_RX_GROUP_DTHE (UDMA_MAPPED_GROUP3)

UDMA Resources ID
List of all UDMA Resources Id's.
#define	UDMA_RM_RES_ID_BC_UHC (0U)
	Ultra High Capacity Block Copy Channels. More...

#define	UDMA_RM_RES_ID_BC_HC (1U)
	High Capacity Block Copy Channels. More...

#define	UDMA_RM_RES_ID_BC (2U)
	Normal Capacity Block Copy Channels. More...

#define	UDMA_RM_RES_ID_TX_UHC (3U)
	Ultra High Capacity TX Channels. More...

#define	UDMA_RM_RES_ID_TX_HC (4U)
	High Capacity TX Channels. More...

#define	UDMA_RM_RES_ID_TX (5U)
	Normal Capacity TX Channels. More...

#define	UDMA_RM_RES_ID_RX_UHC (6U)
	Ultra High Capacity RX Channels. More...

#define	UDMA_RM_RES_ID_RX_HC (7U)
	High Capacity RX Channels. More...

#define	UDMA_RM_RES_ID_RX (8U)
	Normal Capacity RX Channels. More...

#define	UDMA_RM_RES_ID_MAPPED_TX_CPSW (11U)
	[Pktdma Only] Mapped TX Channels for CPSW More...

#define	UDMA_RM_RES_ID_MAPPED_RX_CPSW (16U)
	[Pktdma Only] Mapped RX Channels for CPSW More...

#define	UDMA_RM_RES_ID_MAPPED_TX_RING_CPSW (23U)
	[Pktdma Only] Mapped TX Rings for CPSW More...

#define	UDMA_RM_NUM_BCDMA_RES (11U)
	Total number of BCDMA resources. More...

#define	UDMA_RM_NUM_PKTDMA_RES (35U)
	Total number of PKTDMA resources. More...

#define	UDMA_RM_NUM_RES (35U)
	Total number of resources. More...

#define	UDMA_RM_BLKCPY_START (128U)
	Start of block copy BC channel. More...

#define	UDMA_RM_SPLIT_TX_START (1U)
	Start of split Tx channel. More...

#define	UDMA_RM_SPLIT_RX_START (0U)
	Start of split Rx channel. More...

#define	UDMA_RM_TOTAL_CH_INT (229U)
	Total number of bcdma/pktdma channel interrupts. More...

#define	UDMA_RM_BLKCPY_BC_CH_INT_OFFSET (420U)
	Offset to be added to block copy channel interrupts. More...

#define	UDMA_RM_CH_INT_START (352U)
	Start index of bcdma/pktdma channel interrupts. More...

PSIL Channels
List of all PSIL channels and the corresponding counts
#define	UDMA_PSIL_CH_CPSW2_RX (0x4600U)

#define	UDMA_PSIL_CH_DTHE_RX (0x4000U)

#define	UDMA_PSIL_CH_CPSW2_TX0 (UDMA_PSIL_CH_CPSW2_RX \| UDMA_PSIL_DEST_THREAD_OFFSET)

#define	UDMA_PSIL_CH_CPSW2_TX1 (0xC601U)

#define	UDMA_PSIL_CH_CPSW2_TX2 (0xC602U)

#define	UDMA_PSIL_CH_CPSW2_TX3 (0xC603U)

#define	UDMA_PSIL_CH_CPSW2_TX4 (0xC604U)

#define	UDMA_PSIL_CH_CPSW2_TX5 (0xC605U)

#define	UDMA_PSIL_CH_CPSW2_TX6 (0xC606U)

#define	UDMA_PSIL_CH_CPSW2_TX7 (0xC607U)

#define	UDMA_PSIL_CH_DTHE_TX (UDMA_PSIL_CH_DTHE_RX \| UDMA_PSIL_DEST_THREAD_OFFSET)

#define	UDMA_PSIL_CH_CPSW2_TX_CNT (8U)

#define	UDMA_PSIL_CH_CPSW2_RX_CNT (1U)

#define	UDMA_PSIL_CH_DTHE_RX_CNT (4U)

Main0 RX PDMA Channels
List of all Main0 PDMA RX channels
#define	UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_RX (0x4300U + 0U)

#define	UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_RX (0x4300U + 0U)

#define	UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_RX (0x4300U + 0U)

#define	UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_RX (0x4300U + 0U)

#define	UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_RX (0x4300U + 1U)

#define	UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_RX (0x4300U + 1U)

#define	UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_RX (0x4300U + 1U)

#define	UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_RX (0x4300U + 1U)

#define	UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_RX (0x4300U + 2U)

#define	UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_RX (0x4300U + 2U)

#define	UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_RX (0x4300U + 2U)

#define	UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_RX (0x4300U + 2U)

#define	UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_RX (0x4300U + 3U)

#define	UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_RX (0x4300U + 3U)

#define	UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_RX (0x4300U + 3U)

#define	UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_RX (0x4300U + 3U)

#define	UDMA_PDMA_CH_MAIN0_UART0_RX (0x4400U + 0U)

#define	UDMA_PDMA_CH_MAIN0_UART1_RX (0x4400U + 1U)

#define	UDMA_PDMA_CH_MAIN0_MCASP0_RX (0x4500U + 0U)

#define	UDMA_PDMA_CH_MAIN0_MCASP1_RX (0x4500U + 1U)

#define	UDMA_PDMA_CH_MAIN0_MCASP2_RX (0x4500U + 2U)

Main0 TX PDMA Channels
List of all Main0 PDMA TX channels
#define	UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_TX (UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_RX \| UDMA_PSIL_DEST_THREAD_OFFSET)

#define	UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_TX (UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_RX \| UDMA_PSIL_DEST_THREAD_OFFSET)

#define	UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_TX (UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_RX \| UDMA_PSIL_DEST_THREAD_OFFSET)

#define	UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_TX (UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_RX \| UDMA_PSIL_DEST_THREAD_OFFSET)

#define	UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_TX (UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_RX \| UDMA_PSIL_DEST_THREAD_OFFSET)

#define	UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_TX (UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_RX \| UDMA_PSIL_DEST_THREAD_OFFSET)

#define	UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_TX (UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_RX \| UDMA_PSIL_DEST_THREAD_OFFSET)

#define	UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_TX (UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_RX \| UDMA_PSIL_DEST_THREAD_OFFSET)

#define	UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_TX (UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_RX \| UDMA_PSIL_DEST_THREAD_OFFSET)

#define	UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_TX (UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_RX \| UDMA_PSIL_DEST_THREAD_OFFSET)

#define	UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_TX (UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_RX \| UDMA_PSIL_DEST_THREAD_OFFSET)

#define	UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_TX (UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_RX \| UDMA_PSIL_DEST_THREAD_OFFSET)

#define	UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_TX (UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_RX \| UDMA_PSIL_DEST_THREAD_OFFSET)

#define	UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_TX (UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_RX \| UDMA_PSIL_DEST_THREAD_OFFSET)

#define	UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_TX (UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_RX \| UDMA_PSIL_DEST_THREAD_OFFSET)

#define	UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_TX (UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_RX \| UDMA_PSIL_DEST_THREAD_OFFSET)

#define	UDMA_PDMA_CH_MAIN0_UART0_TX (UDMA_PDMA_CH_MAIN0_UART0_RX \| UDMA_PSIL_DEST_THREAD_OFFSET)

#define	UDMA_PDMA_CH_MAIN0_UART1_TX (UDMA_PDMA_CH_MAIN0_UART1_RX \| UDMA_PSIL_DEST_THREAD_OFFSET)

#define	UDMA_PDMA_CH_MAIN0_MCASP0_TX (UDMA_PDMA_CH_MAIN0_MCASP0_RX \| UDMA_PSIL_DEST_THREAD_OFFSET)

#define	UDMA_PDMA_CH_MAIN0_MCASP1_TX (UDMA_PDMA_CH_MAIN0_MCASP1_RX \| UDMA_PSIL_DEST_THREAD_OFFSET)

#define	UDMA_PDMA_CH_MAIN0_MCASP2_TX (UDMA_PDMA_CH_MAIN0_MCASP2_RX \| UDMA_PSIL_DEST_THREAD_OFFSET)

Main1 RX PDMA Channels
List of all Main1 PDMA RX channels
#define	UDMA_PDMA_CH_MAIN1_UART2_RX (0x4400U + 2U)

#define	UDMA_PDMA_CH_MAIN1_UART3_RX (0x4400U + 3U)

#define	UDMA_PDMA_CH_MAIN1_UART4_RX (0x4400U + 4U)

#define	UDMA_PDMA_CH_MAIN1_UART5_RX (0x4400U + 5U)

#define	UDMA_PDMA_CH_MAIN1_UART6_RX (0x4400U + 6U)

#define	UDMA_PDMA_CH_MAIN1_ADC0_CH0_RX (0x4503U)

#define	UDMA_PDMA_CH_MAIN1_ADC0_CH1_RX (0x4504U)

Main1 TX PDMA Channels
List of all Main1 PDMA TX channels
#define	UDMA_PDMA_CH_MAIN1_UART2_TX (UDMA_PDMA_CH_MAIN1_UART2_RX \| UDMA_PSIL_DEST_THREAD_OFFSET)

#define	UDMA_PDMA_CH_MAIN1_UART3_TX (UDMA_PDMA_CH_MAIN1_UART3_RX \| UDMA_PSIL_DEST_THREAD_OFFSET)

#define	UDMA_PDMA_CH_MAIN1_UART4_TX (UDMA_PDMA_CH_MAIN1_UART4_RX \| UDMA_PSIL_DEST_THREAD_OFFSET)

#define	UDMA_PDMA_CH_MAIN1_UART5_TX (UDMA_PDMA_CH_MAIN1_UART5_RX \| UDMA_PSIL_DEST_THREAD_OFFSET)

#define	UDMA_PDMA_CH_MAIN1_UART6_TX (UDMA_PDMA_CH_MAIN1_UART6_RX \| UDMA_PSIL_DEST_THREAD_OFFSET)

Functions
uint32_t	Udma_isCacheCoherent (void)
	Returns TRUE if the memory is cache coherent. More...

Function Documentation

◆ Udma_isCacheCoherent()

uint32_t Udma_isCacheCoherent ( void )

Returns TRUE if the memory is cache coherent.

Returns: TRUE/FALSE

Introduction

Macros

Functions

Function Documentation

◆ Udma_isCacheCoherent()