udma_soc.h

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/*
 *  Copyright (C) 2025 Texas Instruments Incorporated
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef UDMA_SOC_H_
#define UDMA_SOC_H_
 
/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */
 
/* None */
 
#ifdef __cplusplus
extern "C" {
#endif
 
/* ========================================================================== */
/*                           Macros & Typedefs                                */
/* ========================================================================== */
 
#define UDMA_INST_ID_BCDMA_0             (UDMA_INST_ID_2)
 
#define UDMA_INST_ID_PKTDMA_0            (UDMA_INST_ID_3)
 
#define UDMA_INST_ID_START               (UDMA_INST_ID_2)
 
#define UDMA_INST_ID_MAX                 (UDMA_INST_ID_3)
 
#define UDMA_NUM_INST_ID                 (UDMA_INST_ID_MAX - UDMA_INST_ID_START + 1U) 
 
#define UDMA_SOC_TOTAL_CHAN_NUM            (79U)    
 
#define UDMA_SOC_PKTDMA_TOTAL_TX_RX_CHAN   (97U)   
 
#define UDMA_SOC_BCDMA_TOTAL_TX_RX_CHAN    (82U)  
 
#define UDMA_SOC_MAX_TIMEOUT               (1U * 1000U) /*1ms*/  
 
#define UDMA_SOC_CFG_LCDMA_PRESENT      (1U)
 
#define UDMA_SOC_CFG_RA_LCDMA_PRESENT   (1U)
 
#define UDMA_SOC_CFG_UDMAP_PRESENT               (0U)
 
#define UDMA_SOC_CFG_PROXY_PRESENT               (0U)
 
#define UDMA_SOC_CFG_CLEC_PRESENT                (0U)
 
#define UDMA_SOC_CFG_RA_NORMAL_PRESENT           (0U)
 
#define UDMA_SOC_CFG_RING_MON_PRESENT            (0U)
 
#define UDMA_SOC_CFG_APPLY_RING_WORKAROUND       (0U)
 
#define UDMA_TX_UHC_CHANS_FDEPTH        (0U)
 
#define UDMA_TX_HC_CHANS_FDEPTH         (0U)
 
#define UDMA_TX_CHANS_FDEPTH            (192U)
 
#define UDMA_RINGACC_ASEL_ENDPOINT_PHYSADDR          ((uint32_t) 0U)
 
#define UDMA_RINGACC_ASEL_ENDPOINT_PCIE0             ((uint32_t) 1U)
 
#define UDMA_RINGACC_ASEL_ENDPOINT_ACP_WR_ALLOC      ((uint32_t) 14U)
 
#define UDMA_RINGACC_ASEL_ENDPOINT_ACP_RD_ALLOC      ((uint32_t) 15U)
 
#define UDMA_NUM_MAPPED_TX_GROUP        (2U)
 
#define UDMA_MAPPED_TX_GROUP_CPSW       (UDMA_MAPPED_GROUP0)
#define UDMA_MAPPED_TX_GROUP_DTHE       (UDMA_MAPPED_GROUP1)
 
#define UDMA_NUM_MAPPED_RX_GROUP        (2U)
 
#define UDMA_MAPPED_RX_GROUP_CPSW       (UDMA_MAPPED_GROUP2)
#define UDMA_MAPPED_RX_GROUP_DTHE       (UDMA_MAPPED_GROUP3)
 
#define UDMA_RM_RES_ID_BC_UHC                   (0U)
 
#define UDMA_RM_RES_ID_BC_HC                    (1U)
 
#define UDMA_RM_RES_ID_BC                       (2U)
 
#define UDMA_RM_RES_ID_TX_UHC                   (3U)
 
#define UDMA_RM_RES_ID_TX_HC                    (4U)
 
#define UDMA_RM_RES_ID_TX                       (5U)
 
#define UDMA_RM_RES_ID_RX_UHC                   (6U)
 
#define UDMA_RM_RES_ID_RX_HC                    (7U)
 
#define UDMA_RM_RES_ID_RX                       (8U)
 
#define UDMA_RM_RES_ID_MAPPED_TX_CPSW           (11U)
 
#define UDMA_RM_RES_ID_MAPPED_RX_CPSW           (16U)
 
#define UDMA_RM_RES_ID_MAPPED_TX_RING_CPSW      (23U)
 
#define UDMA_RM_NUM_BCDMA_RES                   (11U)
 
#define UDMA_RM_NUM_PKTDMA_RES                  (35U)
 
#define UDMA_RM_NUM_RES                         (35U)
 
#define UDMA_RM_BLKCPY_START                    (128U)
 
#define UDMA_RM_SPLIT_TX_START                   (1U)
 
#define UDMA_RM_SPLIT_RX_START                   (0U)
 
#define UDMA_RM_TOTAL_CH_INT                     (229U)
 
#define UDMA_RM_BLKCPY_BC_CH_INT_OFFSET          (420U)
 
#define UDMA_RM_CH_INT_START                     (352U)
 
#define UDMA_PSIL_DEST_THREAD_OFFSET    (0x8000U)
 
#define UDMA_PSIL_CH_CPSW2_RX           (0x4600U)
#define UDMA_PSIL_CH_DTHE_RX            (0x4000U)
 
#define UDMA_PSIL_CH_CPSW2_TX0           (UDMA_PSIL_CH_CPSW2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
#define UDMA_PSIL_CH_CPSW2_TX1           (0xC601U)
#define UDMA_PSIL_CH_CPSW2_TX2           (0xC602U)
#define UDMA_PSIL_CH_CPSW2_TX3           (0xC603U)
#define UDMA_PSIL_CH_CPSW2_TX4           (0xC604U)
#define UDMA_PSIL_CH_CPSW2_TX5           (0xC605U)
#define UDMA_PSIL_CH_CPSW2_TX6           (0xC606U)
#define UDMA_PSIL_CH_CPSW2_TX7           (0xC607U)
#define UDMA_PSIL_CH_DTHE_TX             (UDMA_PSIL_CH_DTHE_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
#define UDMA_PSIL_CH_CPSW2_TX_CNT       (8U)
 
#define UDMA_PSIL_CH_CPSW2_RX_CNT       (1U)
#define UDMA_PSIL_CH_DTHE_RX_CNT        (4U)
 
/*
 * PDMA MAIN0 MCSPI RX Channels
 */
#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_RX    (0x4300U + 0U)
#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_RX    (0x4300U + 0U)
#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_RX    (0x4300U + 0U)
#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_RX    (0x4300U + 0U)
#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_RX    (0x4300U + 1U)
#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_RX    (0x4300U + 1U)
#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_RX    (0x4300U + 1U)
#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_RX    (0x4300U + 1U)
#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_RX    (0x4300U + 2U)
#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_RX    (0x4300U + 2U)
#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_RX    (0x4300U + 2U)
#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_RX    (0x4300U + 2U)
#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_RX    (0x4300U + 3U)
#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_RX    (0x4300U + 3U)
#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_RX    (0x4300U + 3U)
#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_RX    (0x4300U + 3U)
/*
 * PDMA MAIN0 UART RX Channels
 */
#define UDMA_PDMA_CH_MAIN0_UART0_RX         (0x4400U + 0U)
#define UDMA_PDMA_CH_MAIN0_UART1_RX         (0x4400U + 1U)
 
/*
 * PDMA MAIN0 MCASP RX Channels
 */
#define UDMA_PDMA_CH_MAIN0_MCASP0_RX        (0x4500U + 0U)
#define UDMA_PDMA_CH_MAIN0_MCASP1_RX        (0x4500U + 1U)
#define UDMA_PDMA_CH_MAIN0_MCASP2_RX        (0x4500U + 2U)
 
/*
 * PDMA MAIN0 MCSPI TX Channels
 */
#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_TX    (UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_TX    (UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_TX    (UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_TX    (UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_TX    (UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_TX    (UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_TX    (UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_TX    (UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_TX    (UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_TX    (UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_TX    (UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_TX    (UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_TX    (UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_TX    (UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_TX    (UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_TX    (UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
/*
 * PDMA MAIN0 UART TX Channels
 */
#define UDMA_PDMA_CH_MAIN0_UART0_TX         (UDMA_PDMA_CH_MAIN0_UART0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
#define UDMA_PDMA_CH_MAIN0_UART1_TX         (UDMA_PDMA_CH_MAIN0_UART1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
/*
 * PDMA MAIN0 MCASP TX Channels
 */
#define UDMA_PDMA_CH_MAIN0_MCASP0_TX        (UDMA_PDMA_CH_MAIN0_MCASP0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
#define UDMA_PDMA_CH_MAIN0_MCASP1_TX        (UDMA_PDMA_CH_MAIN0_MCASP1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
#define UDMA_PDMA_CH_MAIN0_MCASP2_TX        (UDMA_PDMA_CH_MAIN0_MCASP2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
/*
 * PDMA MAIN1 UART RX Channels
 */
#define UDMA_PDMA_CH_MAIN1_UART2_RX         (0x4400U + 2U)
#define UDMA_PDMA_CH_MAIN1_UART3_RX         (0x4400U + 3U)
#define UDMA_PDMA_CH_MAIN1_UART4_RX         (0x4400U + 4U)
#define UDMA_PDMA_CH_MAIN1_UART5_RX         (0x4400U + 5U)
#define UDMA_PDMA_CH_MAIN1_UART6_RX         (0x4400U + 6U)
 
/*
 * PDMA MAIN1 ADC RX Channels
 */
#define UDMA_PDMA_CH_MAIN1_ADC0_CH0_RX      (0x4503U)
#define UDMA_PDMA_CH_MAIN1_ADC0_CH1_RX      (0x4504U) 
 
/*
 * PDMA MAIN1 UART TX Channels
 */
#define UDMA_PDMA_CH_MAIN1_UART2_TX         (UDMA_PDMA_CH_MAIN1_UART2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
#define UDMA_PDMA_CH_MAIN1_UART3_TX         (UDMA_PDMA_CH_MAIN1_UART3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
#define UDMA_PDMA_CH_MAIN1_UART4_TX         (UDMA_PDMA_CH_MAIN1_UART4_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
#define UDMA_PDMA_CH_MAIN1_UART5_TX         (UDMA_PDMA_CH_MAIN1_UART5_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
#define UDMA_PDMA_CH_MAIN1_UART6_TX         (UDMA_PDMA_CH_MAIN1_UART6_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
 
/* ========================================================================== */
/*                         Structure Declarations                             */
/* ========================================================================== */
 
/* None */
 
/* ========================================================================== */
/*                          Function Declarations                             */
/* ========================================================================== */
 
uint32_t Udma_isCacheCoherent(void);
 
/* ========================================================================== */
/*                       Static Function Definitions                          */
/* ========================================================================== */
 
/* None */
 
#ifdef __cplusplus
}
#endif
 
#endif /* #ifndef UDMA_SOC_H_ */