|
| #define | ETHPHYDRV_MAX_OBJ_SIZE (64) /* to meet the size of Phy_Obj_t */ |
| |
| #define | PHY_DIV_ROUNDUP(val, div) (((val) + (div) - 1) / (div)) |
| | Macro to perform round-up division. More...
|
| |
| #define | PHY_BIT(n) (1U << (n)) |
| | Macro to set bit at given bit position. More...
|
| |
| #define | PHY_ON (1U) |
| | Build-time config option is enabled. More...
|
| |
| #define | PHY_OFF (0U) |
| | Build-time config option is disabled. More...
|
| |
| #define | PHY_CFG_IS_ON(name) ((PHY_CFG_ ## name) == PHY_ON) |
| | Preprocessor check if config option is enabled. More...
|
| |
| #define | PHY_CFG_IS_OFF(name) ((PHY_CFG_ ## name) == PHY_OFF) |
| | Preprocessor check if config option is disabled. More...
|
| |
| #define | PHY_BMCR (0x00U) |
| | Basic Mode Control Register (BMCR) More...
|
| |
| #define | PHY_BMSR (0x01U) |
| | Basic Mode Status Register (BMSR) More...
|
| |
| #define | PHY_PHYIDR1 (0x02U) |
| | PHY Identifier Register #1 (PHYIDR1) More...
|
| |
| #define | PHY_PHYIDR2 (0x03U) |
| | PHY Identifier Register #2 (PHYIDR2) More...
|
| |
| #define | PHY_ANAR (0x04U) |
| | Auto-Negotiation Advertisement Register (ANAR) More...
|
| |
| #define | PHY_ANLPAR (0x05U) |
| | Auto-Negotiation Link Partner Abilitiy Register (ANLPAR) More...
|
| |
| #define | PHY_ANER (0x06U) |
| | Auto-Negotiation Expansion Register (ANER) More...
|
| |
| #define | PHY_ANNPTR (0x07U) |
| | Auto-Negotiation NP TX Register (ANNPTR) More...
|
| |
| #define | PHY_ANNPRR (0x08U) |
| | Auto-Neg NP RX Register (ANNPRR) More...
|
| |
| #define | PHY_GIGCR (0x09U) |
| | 1000BASE-T Control Register (GIGCR) More...
|
| |
| #define | PHY_GIGSR (0x0AU) |
| | 1000BASE-T Status Register (GIGSR) More...
|
| |
| #define | PHY_MMD_CR (0x0DU) |
| | MMD Access Control Register. More...
|
| |
| #define | PHY_MMD_DR (0x0EU) |
| | MMD Access Data Register. More...
|
| |
| #define | PHY_GIGESR (0x0FU) |
| | 1000BASE-T Extended Status Register (GIGESR) More...
|
| |
| #define | MMD_CR_ADDR (0x0000U) |
| |
| #define | MMD_CR_DATA_NOPOSTINC (0x4000U) |
| |
| #define | MMD_CR_DATA_POSTINC_RW (0x8000U) |
| |
| #define | MMD_CR_DATA_POSTINC_W (0xC000U) |
| |
| #define | MMD_CR_DEVADDR (0x001FU) |
| |
| #define | PHY_BMCR_RESET PHY_BIT(15) |
| |
| #define | PHY_BMCR_LOOPBACK PHY_BIT(14) |
| |
| #define | PHY_BMCR_SPEED100 PHY_BIT(13) |
| |
| #define | PHY_BMCR_ANEN PHY_BIT(12) |
| |
| #define | PHY_BMCR_PWRDOWN PHY_BIT(11) |
| |
| #define | PHY_BMCR_ISOLATE PHY_BIT(10) |
| |
| #define | PHY_BMCR_ANRESTART PHY_BIT(9) |
| |
| #define | PHY_BMCR_FD PHY_BIT(8) |
| |
| #define | PHY_BMCR_SPEED1000 PHY_BIT(6) |
| |
| #define | PHY_EXTENDED_CFG_SIZE_MAX (128U) |
| | Max extended configuration size, arbitrarily chosen. More...
|
| |
| #define | PHY_LINK_CAP_HD10 PHY_BIT(1) |
| | 10-Mbps, half-duplex capability mask. More...
|
| |
| #define | PHY_LINK_CAP_FD10 PHY_BIT(2) |
| | 10-Mbps, full-duplex capability mask. More...
|
| |
| #define | PHY_LINK_CAP_HD100 PHY_BIT(3) |
| | 100-Mbps, half-duplex capability mask. More...
|
| |
| #define | PHY_LINK_CAP_FD100 PHY_BIT(4) |
| | 100-Mbps, full-duplex capability mask. More...
|
| |
| #define | PHY_LINK_CAP_HD1000 PHY_BIT(5) |
| | 1-Gbps, half-duplex capability mask. More...
|
| |
| #define | PHY_LINK_CAP_FD1000 PHY_BIT(6) |
| | 1-Gbps, full-duplex capability mask. More...
|
| |
| #define | PHY_LINK_CAP_10 (PHY_LINK_CAP_HD10 | PHY_LINK_CAP_FD10) |
| | 10-Mbps, full and half-duplex capability mask. More...
|
| |
| #define | PHY_LINK_CAP_100 (PHY_LINK_CAP_HD100 | PHY_LINK_CAP_FD100) |
| | 100-Mbps, full and half-duplex capability mask. More...
|
| |
| #define | PHY_LINK_CAP_1000 (PHY_LINK_CAP_HD1000 | PHY_LINK_CAP_FD1000) |
| | 1-Gbps, full and half-duplex capability mask. More...
|
| |
| #define | PHY_LINK_CAP_ALL |
| | Auto-negotiation mask with all duplexity and speed values set. More...
|
| |
| #define | PHY_LINK_ADV_HD10 PHY_BIT(1) |
| | 10-Mbps, half-duplex advertisement flag. More...
|
| |
| #define | PHY_LINK_ADV_FD10 PHY_BIT(2) |
| | 10-Mbps, full-duplex advertisement flag. More...
|
| |
| #define | PHY_LINK_ADV_HD100 PHY_BIT(3) |
| | 100-Mbps, half-duplex advertisement flag. More...
|
| |
| #define | PHY_LINK_ADV_FD100 PHY_BIT(4) |
| | 100-Mbps, full-duplex advertisement flag. More...
|
| |
| #define | PHY_LINK_ADV_HD1000 PHY_BIT(5) |
| | 1-Gbps, half-duplex advertisement flag. More...
|
| |
| #define | PHY_LINK_ADV_FD1000 PHY_BIT(6) |
| | 1-Gbps, full-duplex advertisement flag. More...
|
| |
| #define | PHY_FAST_LINK_DOWN_ENERGY_LOST PHY_BIT(0) |
| | Fast link down option - energy lost. More...
|
| |
| #define | PHY_FAST_LINK_DOWN_MSE PHY_BIT(1) |
| | Fast link down option - MSE error. More...
|
| |
| #define | PHY_FAST_LINK_DOWN_MLT3_ERRORS PHY_BIT(2) |
| | Fast link down option - MLT3 errors. More...
|
| |
| #define | PHY_FAST_LINK_DOWN_RX_ERR PHY_BIT(3) |
| | Fast link down option - RX error. More...
|
| |
| #define | PHY_FAST_LINK_DOWN_DESCRAMBLER_SYNC_LOSS PHY_BIT(4) |
| | Fast link down option - decrambler sync lost. More...
|
| |
|
Error codes returned by the Ethernet PHY driver APIs.
|
| #define | PHY_SOK ( (int32_t) (0)) |
| | Success. More...
|
| |
| #define | PHY_EFAIL (-(int32_t) (1)) |
| | Generic failure error condition (typically caused by hardware). More...
|
| |
| #define | PHY_EBADARGS (-(int32_t) (2)) (-(int32_t) (2)) |
| | Bad arguments (i.e. NULL pointer). More...
|
| |
| #define | PHY_EINVALIDPARAMS (-(int32_t) (3)) |
| | Invalid parameters (i.e. value out-of-range). More...
|
| |
| #define | PHY_ETIMEOUT (-(int32_t) (4)) |
| | Time out while waiting for a given condition to happen. More...
|
| |
| #define | PHY_EALLOC (-(int32_t) (8)) |
| | Allocation failure. More...
|
| |
| #define | PHY_EPERM (PHY_EALLOC - 4) |
| | Operation not permitted. More...
|
| |
| #define | PHY_ENOTSUPPORTED (PHY_EALLOC - 5) |
| | Operation not supported. More...
|
| |
1.8.20