Introduction

This file contains the definition of all the parameter IDs for PM, RM, Security.

Macros
#define	TISCI_PARAM_UNDEF (0xFFFFFFFFU)

#define	SCICLIENT_CONTEXT_C7X_NONSEC_0 (10U)

#define	SCICLIENT_CONTEXT_C7X_SEC_0 (9U)

#define	SCICLIENT_C7X_NON_SECURE_INTERRUPT_NUM (9U)

#define	SCICLIENT_C7X_SECURE_INTERRUPT_NUM (10U)

#define	TISCI_MSG_VALUE_RM_NULL_RING_TYPE (0xFFFFu)

#define	TISCI_MSG_VALUE_RM_NULL_RING_INDEX (0xFFFFFFFFu)

#define	TISCI_MSG_VALUE_RM_NULL_RING_ADDR (0xFFFFFFFFu)

#define	TISCI_MSG_VALUE_RM_NULL_RING_COUNT (0xFFFFFFFFu)

#define	TISCI_MSG_VALUE_RM_NULL_RING_MODE (0xFFu)

#define	TISCI_MSG_VALUE_RM_NULL_RING_SIZE (0xFFu)

#define	TISCI_MSG_VALUE_RM_NULL_ORDER_ID (0xFFu)

#define	TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_TYPE (0xFFu)

#define	TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_INDEX (0xFFFFFFFFu)

#define	TISCI_ISC_CC_ID (160U)
	Special ISC ID to refer to compute cluster privid registers. More...

#define	SCICLIENT_ALLOWED_BOARDCFG_BASE_START 1U

#define	SCICLIENT_ALLOWED_BOARDCFG_BASE_END 0xFFFFFFFFU

Sciclient Firmware ABI revisions
ABI revisions for compatibility check.
#define	SCICLIENT_FIRMWARE_ABI_MAJOR (4U)

#define	SCICLIENT_FIRMWARE_ABI_MINOR (0U)

Sciclient Context Ids
Context IDs for Sciclient_ConfigPrms_t .
#define	SCICLIENT_CONTEXT_R5_SEC_0 (0U)

#define	SCICLIENT_CONTEXT_R5_NONSEC_0 (1U)

#define	SCICLIENT_CONTEXT_R5_SEC_1 (2U)

#define	SCICLIENT_CONTEXT_R5_NONSEC_1 (3U)

#define	SCICLIENT_CONTEXT_A53_SEC_0 (4U)

#define	SCICLIENT_CONTEXT_A53_SEC_1 (5U)

#define	SCICLIENT_CONTEXT_A53_NONSEC_1 (6U)

#define	SCICLIENT_CONTEXT_A53_NONSEC_2 (7U)

#define	SCICLIENT_CONTEXT_MCU_R5_0_NONSEC_0 (8U)

#define	SCICLIENT_CONTEXT_A53_NONSEC_3 (9U)

#define	SCICLIENT_CONTEXT_C7_NONSEC_0 (10U)

#define	SCICLIENT_CONTEXT_DM2TIFS (11U)

#define	SCICLIENT_CONTEXT_MAX_NUM (12U)

Sciclient Processor Ids
Processor IDs for the Processor Boot Configuration APIs.
#define	SCICLIENT_PROC_ID_A53SS0_CORE_0 (0x20U)

#define	SCICLIENT_PROC_ID_A53SS0_CORE_1 (0x21U)

#define	SCICLIENT_PROC_ID_A53SS0_CORE_2 (0x22U)

#define	SCICLIENT_PROC_ID_A53SS0_CORE_3 (0x23U)

#define	SCICLIENT_PROC_ID_C7X256V0_C7XV_CORE_0 (0x04U)

#define	SCICLIENT_PROC_ID_MCU_R5FSS0_CORE0 (0x03U)

#define	SCICLIENT_PROC_ID_R5FSS0_CORE0 (0x01U)

#define	SCICLIENT_PROC_ID_HSM_M4FSS0_CORE0 (0x80U)

#define	SOC_NUM_SCICLIENT_PROCESSORS (0x08U)

WKUP Pulsar IDs
WKUP Device CPU IDs.
#define	SCICLIENT_DEV_WKUP_R5FSS0_CORE0 (TISCI_DEV_WKUP_R5FSS0_CORE0)

#define	SCICLIENT_DEV_WKUP_R5FSS0_CORE1 (TISCI_DEV_WKUP_R5FSS0_CORE0)

IRQ source index start
Start offset of IRQ source index.
#define	TISCI_RINGACC0_OES_IRQ_SRC_IDX_START (0U)

#define	TISCI_RINGACC0_MON_IRQ_SRC_IDX_START (1024U)

#define	TISCI_RINGACC0_EOES_IRQ_SRC_IDX_START (2048U)

#define	TISCI_UDMAP0_TX_OES_IRQ_SRC_IDX_START (0U)

#define	TISCI_UDMAP0_TX_EOES_IRQ_SRC_IDX_START (512U)

#define	TISCI_UDMAP0_RX_OES_IRQ_SRC_IDX_START (1024U)

#define	TISCI_UDMAP0_RX_EOES_IRQ_SRC_IDX_START (1280U)

#define	TISCI_UDMAP0_RX_FLOW_EOES_IRQ_SRC_IDX_START (1536U)

#define	TISCI_BCDMA0_BC_RC_OES_IRQ_SRC_IDX_START (9216U)

#define	TISCI_BCDMA0_TX_RC_OES_IRQ_SRC_IDX_START (10752U)

#define	TISCI_BCDMA0_RX_RC_OES_IRQ_SRC_IDX_START (12288U)

#define	TISCI_BCDMA0_BC_DC_OES_IRQ_SRC_IDX_START (8704U)

#define	TISCI_BCDMA0_TX_DC_OES_IRQ_SRC_IDX_START (10240U)

#define	TISCI_BCDMA0_RX_DC_OES_IRQ_SRC_IDX_START (11776U)

#define	TISCI_PKTDMA0_TX_FLOW_OES_IRQ_SRC_IDX_START (4608U)

#define	TISCI_PKTDMA0_RX_FLOW_OES_IRQ_SRC_IDX_START (5632U)

WKUP Pulsar Processor IDs
WKUP Device Processor IDs.
#define	SCICLIENT_DEV_WKUP_R5FSS0_CORE0_PROCID (SCICLIENT_PROC_ID_R5FSS0_CORE0)

#define	SCICLIENT_DEV_WKUP_R5FSS0_CORE1_PROCID (SCICLIENT_PROC_ID_R5FSS0_CORE0)

Introduction

Macros