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AM62Ax MCU+ SDK
10.01.00
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Go to the documentation of this file.
48 #ifndef SCICLIENT_FMWMSGPARAMS_H_
49 #define SCICLIENT_FMWMSGPARAMS_H_
66 #define TISCI_PARAM_UNDEF (0xFFFFFFFFU)
76 #define SCICLIENT_FIRMWARE_ABI_MAJOR (4U)
81 #define SCICLIENT_FIRMWARE_ABI_MINOR (0U)
85 #define SCICLIENT_CONTEXT_C7X_NONSEC_0 (10U)
86 #define SCICLIENT_CONTEXT_C7X_SEC_0 (9U)
88 #define SCICLIENT_C7X_NON_SECURE_INTERRUPT_NUM (9U)
89 #define SCICLIENT_C7X_SECURE_INTERRUPT_NUM (10U)
97 #define SCICLIENT_CONTEXT_R5_SEC_0 (0U)
99 #define SCICLIENT_CONTEXT_R5_NONSEC_0 (1U)
101 #define SCICLIENT_CONTEXT_R5_SEC_1 (2U)
103 #define SCICLIENT_CONTEXT_R5_NONSEC_1 (3U)
105 #define SCICLIENT_CONTEXT_A53_SEC_0 (4U)
107 #define SCICLIENT_CONTEXT_A53_SEC_1 (5U)
109 #define SCICLIENT_CONTEXT_A53_NONSEC_1 (6U)
111 #define SCICLIENT_CONTEXT_A53_NONSEC_2 (7U)
113 #define SCICLIENT_CONTEXT_MCU_R5_0_NONSEC_0 (8U)
115 #define SCICLIENT_CONTEXT_A53_NONSEC_3 (9U)
117 #define SCICLIENT_CONTEXT_C7_NONSEC_0 (10U)
119 #define SCICLIENT_CONTEXT_DM2TIFS (11U)
122 #define SCICLIENT_CONTEXT_MAX_NUM (12U)
135 #define SCICLIENT_PROC_ID_A53SS0_CORE_0 (0x20U)
140 #define SCICLIENT_PROC_ID_A53SS0_CORE_1 (0x21U)
145 #define SCICLIENT_PROC_ID_A53SS0_CORE_2 (0x22U)
150 #define SCICLIENT_PROC_ID_A53SS0_CORE_3 (0x23U)
155 #define SCICLIENT_PROC_ID_C7X256V0_C7XV_CORE_0 (0x04U)
160 #define SCICLIENT_PROC_ID_MCU_R5FSS0_CORE0 (0x03U)
165 #define SCICLIENT_PROC_ID_R5FSS0_CORE0 (0x01U)
170 #define SCICLIENT_PROC_ID_HSM_M4FSS0_CORE0 (0x80U)
175 #define SOC_NUM_SCICLIENT_PROCESSORS (0x08U)
181 #define TISCI_MSG_VALUE_RM_NULL_RING_TYPE (0xFFFFu)
182 #define TISCI_MSG_VALUE_RM_NULL_RING_INDEX (0xFFFFFFFFu)
183 #define TISCI_MSG_VALUE_RM_NULL_RING_ADDR (0xFFFFFFFFu)
184 #define TISCI_MSG_VALUE_RM_NULL_RING_COUNT (0xFFFFFFFFu)
190 #define TISCI_MSG_VALUE_RM_NULL_RING_MODE (0xFFu)
191 #define TISCI_MSG_VALUE_RM_NULL_RING_SIZE (0xFFu)
192 #define TISCI_MSG_VALUE_RM_NULL_ORDER_ID (0xFFu)
193 #define TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_TYPE (0xFFu)
194 #define TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_INDEX (0xFFFFFFFFu)
222 #define SCICLIENT_DEV_WKUP_R5FSS0_CORE0 (TISCI_DEV_WKUP_R5FSS0_CORE0)
223 #define SCICLIENT_DEV_WKUP_R5FSS0_CORE1 (TISCI_DEV_WKUP_R5FSS0_CORE0)
229 #define TISCI_ISC_CC_ID (160U)
238 #define TISCI_RINGACC0_OES_IRQ_SRC_IDX_START (0U)
239 #define TISCI_RINGACC0_MON_IRQ_SRC_IDX_START (1024U)
240 #define TISCI_RINGACC0_EOES_IRQ_SRC_IDX_START (2048U)
241 #define TISCI_UDMAP0_TX_OES_IRQ_SRC_IDX_START (0U)
242 #define TISCI_UDMAP0_TX_EOES_IRQ_SRC_IDX_START (512U)
243 #define TISCI_UDMAP0_RX_OES_IRQ_SRC_IDX_START (1024U)
244 #define TISCI_UDMAP0_RX_EOES_IRQ_SRC_IDX_START (1280U)
245 #define TISCI_UDMAP0_RX_FLOW_EOES_IRQ_SRC_IDX_START (1536U)
246 #define TISCI_BCDMA0_BC_RC_OES_IRQ_SRC_IDX_START (9216U)
247 #define TISCI_BCDMA0_TX_RC_OES_IRQ_SRC_IDX_START (10752U)
248 #define TISCI_BCDMA0_RX_RC_OES_IRQ_SRC_IDX_START (12288U)
249 #define TISCI_BCDMA0_BC_DC_OES_IRQ_SRC_IDX_START (8704U)
250 #define TISCI_BCDMA0_TX_DC_OES_IRQ_SRC_IDX_START (10240U)
251 #define TISCI_BCDMA0_RX_DC_OES_IRQ_SRC_IDX_START (11776U)
252 #define TISCI_PKTDMA0_TX_FLOW_OES_IRQ_SRC_IDX_START (4608U)
253 #define TISCI_PKTDMA0_RX_FLOW_OES_IRQ_SRC_IDX_START (5632U)
262 #define SCICLIENT_DEV_WKUP_R5FSS0_CORE0_PROCID \
263 (SCICLIENT_PROC_ID_R5FSS0_CORE0)
264 #define SCICLIENT_DEV_WKUP_R5FSS0_CORE1_PROCID \
265 (SCICLIENT_PROC_ID_R5FSS0_CORE0)
269 #define SCICLIENT_ALLOWED_BOARDCFG_BASE_START 1U
271 #define SCICLIENT_ALLOWED_BOARDCFG_BASE_END 0xFFFFFFFFU