Detailed Description

HYPERBUS instance attributes - used during init time.

Data Fields
uint32_t	deviceType

uint32_t	baseAddr

uint32_t	ssBaseAddr

uint32_t	dataBaseAddr

uint32_t	fssCfgBase

uint32_t	fssFsasBase

uint32_t	fssOtfaBase

uint64_t	fssS0Reg0Base

uint64_t	fssS0Reg1Base

uint64_t	fssS0Reg3Base

uint32_t	inputClkFreq

uint32_t	intrNum

uint32_t	intrEnable

uint8_t	intrPriority

uint32_t	ECCEnable

uint32_t	OTFAEnable

uint32_t	chipSelect

uint32_t	latency

uint32_t	writeCSHold

uint32_t	readCSHold

uint32_t	writeCSSetup

uint32_t	readCSSetup

uint32_t	writeCSHigh

uint32_t	readCSHigh

Field Documentation

◆ deviceType

uint32_t HYPERBUS_Attrs::deviceType

◆ baseAddr

uint32_t HYPERBUS_Attrs::baseAddr

Peripheral base address

◆ ssBaseAddr

uint32_t HYPERBUS_Attrs::ssBaseAddr

Peripheral sys base address

◆ dataBaseAddr

uint32_t HYPERBUS_Attrs::dataBaseAddr

Base address of the HYPERBUS HyperRam

◆ fssCfgBase

uint32_t HYPERBUS_Attrs::fssCfgBase

◆ fssFsasBase

uint32_t HYPERBUS_Attrs::fssFsasBase

◆ fssOtfaBase

uint32_t HYPERBUS_Attrs::fssOtfaBase

◆ fssS0Reg0Base

uint64_t HYPERBUS_Attrs::fssS0Reg0Base

◆ fssS0Reg1Base

uint64_t HYPERBUS_Attrs::fssS0Reg1Base

◆ fssS0Reg3Base

uint64_t HYPERBUS_Attrs::fssS0Reg3Base

◆ inputClkFreq

uint32_t HYPERBUS_Attrs::inputClkFreq

Module input clock frequency

◆ intrNum

uint32_t HYPERBUS_Attrs::intrNum

Peripheral interrupt number

◆ intrEnable

uint32_t HYPERBUS_Attrs::intrEnable

Enable interrupt mode

◆ intrPriority

uint8_t HYPERBUS_Attrs::intrPriority

Interrupt priority

◆ ECCEnable

uint32_t HYPERBUS_Attrs::ECCEnable

Enable ECC

◆ OTFAEnable

uint32_t HYPERBUS_Attrs::OTFAEnable

Enable OTFA

◆ chipSelect

uint32_t HYPERBUS_Attrs::chipSelect

HyperBus Chip select number

◆ latency

uint32_t HYPERBUS_Attrs::latency

Initial latency for read/write access, only applicable for HyperRAM

◆ writeCSHold

uint32_t HYPERBUS_Attrs::writeCSHold

CS# hold time for write to CS# deassertion Range 0 to 15 0 means 1 Cycle 15 means 16 Cycles

◆ readCSHold

uint32_t HYPERBUS_Attrs::readCSHold

CS# hold time for read to CS# deassertion Range 0 to 15 0 means 1 Cycle 15 means 16 Cycles

◆ writeCSSetup

uint32_t HYPERBUS_Attrs::writeCSSetup

CS# setup time for write from CS# assertion Range 0 to 15 0 means 1 Cycle 15 means 16 Cycles

◆ readCSSetup

uint32_t HYPERBUS_Attrs::readCSSetup

CS# setup time for read from CS# assertion Range 0 to 15 0 means 1 Cycle 15 means 16 Cycles

◆ writeCSHigh

uint32_t HYPERBUS_Attrs::writeCSHigh

CS# high time for write between operations Range 0 to 15 0 means 1.5 Cycle 15 means 16.5 Cycles

◆ readCSHigh

uint32_t HYPERBUS_Attrs::readCSHigh

CS# high time for read between operations Range 0 to 15 0 means 1.5 Cycle 15 means 16.5 Cycles