soc.h

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#ifndef SOC_AM273X_H_
#define SOC_AM273X_H_
 
#include <stdint.h>
 
#ifdef __cplusplus
extern "C"
{
#endif
 
#include <kernel/dpl/SystemP.h>
#include <drivers/soc/am273x/soc_rcm.h>
#include <drivers/hw_include/am273x/cslr_soc_baseaddress.h>
#include <drivers/hw_include/cslr_soc.h>
 
#define SOC_DOMAIN_ID_MSS_TOP_RCM       (0U)
#define SOC_DOMAIN_ID_MSS_RCM           (1U)
#define SOC_DOMAIN_ID_DSS_RCM           (2U)
#define SOC_DOMAIN_ID_RCSS_RCM          (3U)
#define SOC_DOMAIN_ID_MSS_CTRL          (4U)
#define SOC_DOMAIN_ID_DSS_CTRL          (5U)
#define SOC_DOMAIN_ID_RCSS_CTRL         (6U)
#define SOC_DOMAIN_ID_MSS_IOMUX         (7U)
 
#define IS_QSPI_BASE_ADDR_VALID(baseAddr)    (baseAddr == CSL_MSS_QSPI_U_BASE)
 
#define IS_QSPI_MEMORY_MAP_ADDR_VALID(baseAddr)    (baseAddr == CSL_EXT_FLASH_U_BASE)
 
#define IS_I2C_BASE_ADDR_VALID(baseAddr)    ((baseAddr == CSL_MSS_I2C_U_BASE) || \
                                             (baseAddr == CSL_RCSS_I2CA_U_BASE) || \
                                             (baseAddr == CSL_RCSS_I2CB_U_BASE))
 
 
int32_t SOC_moduleClockEnable(uint32_t moduleId, uint32_t enable);
 
int32_t SOC_moduleSetClockFrequency(uint32_t moduleId, uint32_t clkId, uint64_t clkRate);
 
const char *SOC_getCoreName(uint16_t coreId);
 
uint64_t SOC_getSelfCpuClk(void);
 
void SOC_controlModuleLockMMR(uint32_t domainId, uint32_t partition);
 
void SOC_controlModuleUnlockMMR(uint32_t domainId, uint32_t partition);
 
void SOC_setEpwmTbClk(uint32_t epwmInstance, uint32_t enable);
 
uint64_t SOC_virtToPhy(void *virtAddr);
 
void *SOC_phyToVirt(uint64_t phyAddr);
 
void SOC_logAllClockHz(void);
 
uint32_t SOC_getFlashDataBaseAddr(void);
 
#ifdef __cplusplus
}
#endif
 
#endif