soc_rcm.h File Reference

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Data Structures
struct	SOC_RcmPllHsDivOutConfig
	Structure to specific PLL HS divider output frequencies. More...
struct	SOC_RcmEfuseQspiConfig
	Efuse value for QSPI config. More...

Macros
#define	SOC_RCM_FREQ_HZ2MHZ(hz)   ((hz)/(1000000U))
#define	SOC_RCM_FREQ_MHZ2HZ(mhz)   ((mhz)*(1000000U))
#define	SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB00   (1U << 0U)
	bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2 More...
#define	SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB01   (1U << 1U)
	bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2 More...
#define	SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB10   (1U << 2U)
	bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2 More...
#define	SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB11   (1U << 3U)
	bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2 More...
#define	SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB20   (1U << 4U)
	bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2 More...
#define	SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB21   (1U << 5U)
	bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2 More...
#define	SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB30   (1U << 6U)
	bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2 More...
#define	SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB31   (1U << 7U)
	bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2 More...
#define	SOC_RCM_MEMINIT_DSSL2_MEMBANK_ALL
	bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2 More...
#define	SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM0   (1U << 0U)
	bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL3(), SOC_rcmWaitMemInitDSSL2 More...
#define	SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM1   (1U << 1U)
	bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL3(), SOC_rcmWaitMemInitDSSL2 More...
#define	SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM2   (1U << 2U)
	bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL3(), SOC_rcmWaitMemInitDSSL2 More...
#define	SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM3   (1U << 3U)
	bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL3(), SOC_rcmWaitMemInitDSSL2 More...
#define	SOC_RCM_MEMINIT_DSSL3_MEMBANK_ALL
	bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL3(), SOC_rcmWaitMemInitDSSL2 More...
#define	SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_0   (1U << 0U)
	HSDIV output enable bitmask, used with SOC_RcmPllHsDivOutConfig. More...
#define	SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_1   (1U << 1U)
	HSDIV output enable bitmask, used with SOC_RcmPllHsDivOutConfig. More...
#define	SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_2   (1U << 2U)
	HSDIV output enable bitmask, used with SOC_RcmPllHsDivOutConfig. More...
#define	SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_3   (1U << 3U)
	HSDIV output enable bitmask, used with SOC_RcmPllHsDivOutConfig. More...
#define	SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_ALL
	HSDIV output enable bitmask, used with SOC_RcmPllHsDivOutConfig. More...
#define	SOC_RCM_PLL_HSDIV_OUTPUT_COUNT   (4U)

Enumerations
enum	SOC_RcmResetCause {   SOC_RcmResetCause_POWER_ON_RESET = 0x0U, SOC_RcmResetCause_WARM_RESET = 0x1U, SOC_RcmResetCause_STC_RESET = 0x2U, SOC_RcmResetCause_MMR_CPU0_VIM0_RESET = 0x3U,   SOC_RcmResetCause_MMR_CPU1_VIM1_RESET = 0x4U, SOC_RcmResetCause_MMR_CPU0_RESET = 0x5U, SOC_RcmResetCause_MMR_CPU1_RESET = 0x6U, SOC_RcmResetCause_DBG_CPU0_RESET = 0x7U,   SOC_RcmResetCause_DBG_CPU1_RESET = 0x8U, SOC_RcmResetCause_FSM_TRIGGER_RESET = 0x9U, SOC_RcmResetCause_RST_CAUSE_UNKNOWN = 0xAU, SOC_RcmResetCause_MAX_VALUE = 0xFFFFFFFFu }
	Reset Causes. More...
enum	SOC_RcmPeripheralId {   SOC_RcmPeripheralId_CSIRX, SOC_RcmPeripheralId_MSS_MCANA, SOC_RcmPeripheralId_MSS_MCANB, SOC_RcmPeripheralId_MSS_QSPI,   SOC_RcmPeripheralId_MSS_RTIA, SOC_RcmPeripheralId_MSS_RTIB, SOC_RcmPeripheralId_MSS_RTIC, SOC_RcmPeripheralId_MSS_WDT,   SOC_RcmPeripheralId_MSS_SPIA, SOC_RcmPeripheralId_MSS_SPIB, SOC_RcmPeripheralId_MSS_I2C, SOC_RcmPeripheralId_MSS_SCIA,   SOC_RcmPeripheralId_MSS_SCIB, SOC_RcmPeripheralId_MSS_CPTS, SOC_RcmPeripheralId_MSS_CPSW, SOC_RcmPeripheralId_DSS_RTIA,   SOC_RcmPeripheralId_DSS_RTIB, SOC_RcmPeripheralId_DSS_WDT, SOC_RcmPeripheralId_DSS_SCIA, SOC_RcmPeripheralId_RCSS_I2CA,   SOC_RcmPeripheralId_RCSS_I2CB, SOC_RcmPeripheralId_RCSS_SCIA, SOC_RcmPeripheralId_RCSS_SPIA, SOC_RcmPeripheralId_RCSS_SPIB,   SOC_RcmPeripheralId_RCSS_ATL, SOC_RcmPeripheralId_RCSS_MCASPA_AUX, SOC_RcmPeripheralId_RCSS_MCASPB_AUX, SOC_RcmPeripheralId_RCSS_MCASPC_AUX,   SOC_RcmPeripheralId_MAX_VALUE = 0xFFFFFFFFu }
	Peripheral IDs. More...
enum	SOC_RcmPeripheralClockSource {   SOC_RcmPeripheralClockSource_XTAL_CLK, SOC_RcmPeripheralClockSource_SYS_CLK, SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT1, SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT2,   SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT1, SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT2, SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT3, SOC_RcmPeripheralClockSource_WUCPU_CLK,   SOC_RcmPeripheralClockSource_XREF_CLK0, SOC_RcmPeripheralClockSource_XREF_CLK1, SOC_RcmPeripheralClockSource_MAX_VALUE = 0xFFFFFFFFu }
	Peripheral Clock Sources. More...
enum	SOC_RcmDspClockSource { SOC_RcmDspClockSource_XTAL_CLK, SOC_RcmDspClockSource_DPLL_DSP_HSDIV0_CLKOUT1, SOC_RcmDspClockSource_DPLL_CORE_HSDIV0_CLKOUT1, SOC_RcmDspClockSource_MAX_VALUE = 0xFFFFFFFFu }
	DSP Clock Sources. More...
enum	SOC_RcmR5ClockSource { SOC_RcmR5ClockSource_DPLL_CORE_HSDIV0_CLKOUT2 }
	R5 Clock Sources. More...
enum	SOC_RcmPllFoutFreqId {   SOC_RcmPllFoutFreqId_CLK_1100MHZ, SOC_RcmPllFoutFreqId_CLK_1650MHZ, SOC_RcmPllFoutFreqId_CLK_800MHZ, SOC_RcmPllFoutFreqId_CLK_900MHZ,   SOC_RcmPllFoutFreqId_CLK_2000MHZ, SOC_RcmPllFoutFreqId_CLK_1800MHZ, SOC_RcmPllFoutFreqId_CLK_1920MHZ, SOC_RcmPllFoutFreqId_CLK_1699p21875MHZ,   SOC_RcmPllFoutFreqId_CLK_1728MHZ, SOC_RcmPllFoutFreqId_CLK_1966p08MHZ, SOC_RcmPllFoutFreqId_CLK_1806p336MHZ, SOC_RcmPllFoutFreqId_MAX_VALUE = 0xFFFFFFFFu }
	PLL Fout values. More...
enum	SOC_RcmQspiClockFreqId { SOC_RcmQspiClockFreqId_CLK_40MHZ = 0x0, SOC_RcmQspiClockFreqId_CLK_60MHZ = 0x1, SOC_RcmQspiClockFreqId_CLK_80MHZ = 0x2, SOC_RcmQspiClockFreqId_MAX_VALUE = 0xFFFFFFFFu }
	QSPI frequency values. More...
enum	SOC_RcmEfuseFlashClkModeId { SOC_RcmEfuseFlashClkModeId_0 = 0x0, SOC_RcmEfuseFlashClkModeId_3 = 0x3, SOC_RcmEfuseFlashClkModeId_MAX_VALUE = 0xFFFFFFFFu }
	Efuse value for flash clock mode. More...
SOC Warm Reset Causes
enum	SOC_WarmResetCause {   SOC_WarmResetCause_POWER_ON_RESET = 0x09U, SOC_WarmResetCause_MSS_WDT = 0x0AU, SOC_WarmResetCause_TOP_RCM_WARM_RESET_CONFIG = 0x0CU, SOC_WarmResetCause_EXT_PAD_RESET = 0x08U,   SOC_WarmResetCause_HSM_WDT = 0x18U }

Functions
void	SOC_rcmCoreApllConfig (SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg)
	Set CORE PLL Config. More...
void	SOC_rcmCoreApllHSDivConfig (SOC_RcmPllHsDivOutConfig *hsDivCfg)
	Set CORE PLL Hs Div Config. More...
void	SOC_rcmDspPllConfig (SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg)
	Set DSP PLL Config. More...
void	SOC_rcmPerPllConfig (SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg)
	Set Peripheral PLL Config. More...
int32_t	SOC_rcmSetR5Clock (uint32_t r5FreqHz, uint32_t sysClkFreqHz)
	Set R5 and SycClk frequency. More...
uint32_t	SOC_rcmGetR5Clock (void)
	Get R5 frequency. More...
int32_t	SOC_rcmSetDspClock (SOC_RcmDspClockSource clkSource, uint32_t freqHz)
	Set DSP frequency. More...
uint32_t	SOC_rcmGetDspClock (void)
	Get DSP frequency. More...
int32_t	SOC_rcmSetPeripheralClock (SOC_RcmPeripheralId periphId, SOC_RcmPeripheralClockSource clkSource, uint32_t freqHz)
	Set peripheral frequency. More...
uint32_t	SOC_rcmGetPeripheralClock (SOC_RcmPeripheralId periphId)
	Get peripheral frequency. More...
void	SOC_rcmDspPowerOnReset (void)
	Reset Dsp Core. More...
void	SOC_rcmR5PowerOnReset (void)
	Reset R5 Core. More...
void	SOC_rcmR5ConfigLockStep (void)
	Configure R5 in lock step mode. More...
void	SOC_rcmR5ConfigDualCore (void)
	Configure R5 in dual core mode. More...
void	SOC_rcmR5TriggerReset (void)
	Trigger R5 core reset. More...
void	SOC_rcmCr5bUnhalt (void)
	Unhalt R5 core 1. More...
void	SOC_rcmC66xStart (void)
	Unhalt C66x Core. More...
void	SOC_rcmGetEfuseQspiConfig (SOC_RcmEfuseQspiConfig *qspiEfuseCfg)
	Get QSPI Efuse configuration. More...
SOC_RcmResetCause	SOC_rcmGetResetCause (void)
	Get SOC reset cause. More...
void	SOC_rcmStartMemInitTCMA (void)
	Start memory initialization for R5 TCMA. More...
void	SOC_rcmWaitMemInitTCMA (void)
	Wait memory initialization to complete for R5 TCMA. More...
void	SOC_rcmStartMemInitTCMB (void)
	Start memory initialization for R5 TCMB. More...
void	SOC_rcmWaitMemInitTCMB (void)
	Wait memory initialization to complete for R5 TCMB. More...
void	SOC_rcmMemInitMssMailboxMemory (void)
	Initialize the MSS mailbox memory. More...
void	SOC_rcmMemInitDssMailboxMemory (void)
	Initialize the DSS mailbox memory. More...
void	SOC_rcmStartMemInitMSSL2 (void)
	Start memory initialization for MSS L2. More...
void	SOC_rcmWaitMemInitMSSL2 (void)
	Wait memory initialization to complete for MSS L2. More...
void	SOC_rcmStartMemInitDSSL2 (uint32_t l2bankMask)
	Start memory initialization for DSS L2. More...
void	SOC_rcmWaitMemInitDSSL2 (uint32_t l2bankMask)
	Wait memory initialization to complete for DSS L2. More...
void	SOC_rcmStartMemInitDSSL3 (uint32_t l3bankMask)
	Start memory initialization for DSS L3. More...
void	SOC_rcmWaitMemInitDSSL3 (uint32_t l3bankMask)
	Wait memory initialization to complete for DSS L3. More...
void	SOC_rcmConfigEthMacIf (void)
	RCM configuration for MAC interface. More...
uint32_t	SOC_rcmIsR5FInLockStepMode (uint32_t r5fClusterGroupId)
	Return R5SS status operating in lockstep or dual core mode. More...
void	SOC_generateSwWarmReset (void)
	Generate SW WARM reset. More...
SOC_WarmResetCause	SOC_getWarmResetCause (void)
	Returns cause of WARM reset. More...
void	SOC_clearWarmResetCause (void)
	Clear Reset Cause register. More...