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AM273x MCU+ SDK
09.02.00
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53 #ifndef SDL_IP_PBIST_H_
54 #define SDL_IP_PBIST_H_
64 #if defined (SUBSYS_R5FSS0) || defined (R5F0_INPUTS)
65 #define PBIST_MAX_NUM_RUNS_1 14
66 #define PBIST_MAX_NUM_RUNS_2 22
67 #elif defined (SUBSYS_R5FSS1) || defined (R5F1_INPUTS)
68 #define PBIST_MAX_NUM_RUNS_1 11
69 #define PBIST_MAX_NUM_RUNS_2 1
uint8_t failureDetected
Definition: sdl_ip_pbist.h:272
uint32_t RAMT
Definition: sdl_ip_pbist.h:170
Definition: sdlr_pbist.h:53
volatile uint32_t doneFlag
Definition: sdl_ip_pbist.h:270
uint32_t I0
Definition: sdl_ip_pbist.h:154
int32_t SDL_PBIST_checkResult(const SDL_pbistRegs *pPBISTRegs, bool *pResult)
PBIST check result.
int32_t SDL_PBIST_Instance(SDL_PBIST_inst instance)
PBIST Instance.
uint32_t I1
Definition: sdl_ip_pbist.h:158
uint64_t scrambleValue
Definition: sdl_ip_pbist.h:98
uint32_t I2
Definition: sdl_ip_pbist.h:162
uint32_t CMS
Definition: sdl_ip_pbist.h:146
SDL_PBIST_configNeg PBISTNegConfigRun
Definition: sdl_ip_pbist.h:271
uint64_t memoryGroupsBitMap
Definition: sdl_ip_pbist.h:94
int32_t SDL_PBIST_releaseTestMode(SDL_pbistRegs *pPBISTRegs)
PBIST Release Test mode.
uint32_t CSR
Definition: sdl_ip_pbist.h:150
This structure contains the different configuration used for PBIST.
Definition: sdl_ip_pbist.h:80
uint32_t CL3
Definition: sdl_ip_pbist.h:142
uint32_t CA2
Definition: sdl_ip_pbist.h:122
SDL_pbistRegs * pPBISTRegs
Definition: sdl_ip_pbist.h:264
uint32_t CA1
Definition: sdl_ip_pbist.h:118
uint32_t CL0
Definition: sdl_ip_pbist.h:130
uint32_t CA0
Definition: sdl_ip_pbist.h:114
int32_t SDL_PBIST_start(SDL_pbistRegs *pPBISTRegs, const SDL_PBIST_config *pConfig)
PBIST Start.
uint32_t CL2
Definition: sdl_ip_pbist.h:138
Definition: sdl_ip_pbist.h:262
uint32_t esmEventNumber
Definition: sdl_ip_pbist.h:269
uint32_t interruptNumber
Definition: sdl_ip_pbist.h:268
uint32_t algorithmsBitMap
Definition: sdl_ip_pbist.h:90
int32_t SDL_PBIST_softReset(SDL_pbistRegs *pPBISTRegs)
PBIST Soft reset.
uint32_t CA3
Definition: sdl_ip_pbist.h:126
uint64_t PBISTRegsHiAddress
Definition: sdl_ip_pbist.h:263
uint32_t CL1
Definition: sdl_ip_pbist.h:134
This structure contains the different configuration used for PBIST for the failure insertion test to ...
Definition: sdl_ip_pbist.h:111
uint32_t I3
Definition: sdl_ip_pbist.h:166
SDL_PBIST_inst
PBIST instance.
Definition: sdl_pbist_soc.h:91
int32_t SDL_PBIST_startNeg(SDL_pbistRegs *pPBISTRegs, const SDL_PBIST_configNeg *pConfig)
PBIST Failure Insertion Test Start.
uint32_t numPBISTRuns
Definition: sdl_ip_pbist.h:265