am273x/sdl_ecc_soc.h File Reference

Go to the source code of this file.

Macros
#define	SDL_ECC_WIDTH_UNDEFINED   0x1
#define	SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (28U)
#define	SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (28U)
#define	SDL_MSS_ECC_AGG_MSS_RAM_IDS_TOTAL_ENTRIES   (8U)
#define	SDL_DSS_ECC_AGG_RAM_IDS_TOTAL_ENTRIES   (22U)
#define	SDL_MSS_MCANA_ECC_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MSS_MCANB_ECC_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (8U)
#define	SDL_ECC_Base_Address_TOTAL_ENTRIES   (7U)
#define	SDL_MSS_CPSW0_ECC_U_BASE   (SDL_MSS_CPSW_U_BASE + 0x3F000u)
#define	SDL_TCM_PARITY_ERRFRC   (0x02120144)
#define	TPCC_PARITY_CTRL   (0x0212015Cu)
#define	SDL_R5FSS0_CORE0_TPCC0_PARITY_STATUS   (0x02120160u)
#define	DSS_TPCCA_PARITY_CTRL   (0x060200BCU)
#define	DSS_TPCCB_PARITY_CTRL   (0x060200C0U)
#define	DSS_TPCCC_PARITY_CTRL   (0x060200C4U)
#define	SDL_R5FSS0_CORE0_TPCCA_PARITY_STATUS   (0x060200C8U)
#define	SDL_R5FSS0_CORE0_TPCCB_PARITY_STATUS   (0x060200CCU)
#define	SDL_R5FSS0_CORE0_TPCCC_PARITY_STATUS   (0x060200D0U)

Variables
static const SDL_MemConfig_t	SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries [SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries [SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
const SDL_MemConfig_t	SDL_MSS_ECC_AGG_MSS_MemEntries [SDL_MSS_ECC_AGG_MSS_RAM_IDS_TOTAL_ENTRIES]
const SDL_MemConfig_t	SDL_DSS_ECC_AGG_MemEntries [SDL_DSS_ECC_AGG_RAM_IDS_TOTAL_ENTRIES]
const SDL_MemConfig_t	SDL_MSS_MCANA_ECC_MemEntries [SDL_MSS_MCANA_ECC_RAM_IDS_TOTAL_ENTRIES]
const SDL_MemConfig_t	SDL_MSS_MCANB_ECC_MemEntries [SDL_MSS_MCANB_ECC_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_CPSW3GCSS_ECC_AGGR_MemEntries [SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_RAMIdEntry_t	SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable [SDL_R5FSS0_CORE0_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable [SDL_R5FSS0_CORE1_ECC_AGGR_NUM_RAMS]
const SDL_RAMIdEntry_t	SDL_MSS_ECC_AGG_MSS_RamIdTable [SDL_MSS_ECC_AGG_MSS_NUM_RAMS]
const SDL_RAMIdEntry_t	SDL_DSS_ECC_AGG_RamIdTable [SDL_DSS_ECC_AGG_NUM_RAMS]
const SDL_RAMIdEntry_t	SDL_MSS_MCANA_ECC_RamIdTable [SDL_MSS_MCANA_ECC_NUM_RAMS]
const SDL_RAMIdEntry_t	SDL_MSS_MCANB_ECC_RamIdTable [SDL_MSS_MCANB_ECC_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_CPSW3GCSS_ECC_AGGR_RamIdTable [SDL_CPSW3GCSS_ECC_AGGR_NUM_RAMS]
static SDL_ecc_aggrRegs *const	SDL_ECC_aggrBaseAddressTable [SDL_ECC_Base_Address_TOTAL_ENTRIES]
SDL_ecc_aggrRegs *	SDL_ECC_aggrTransBaseAddressTable [SDL_ECC_MEMTYPE_MAX]
static const SDL_EccAggrEntry_t	SDL_ECC_aggrTable [SDL_ECC_MEMTYPE_MAX]

Macro Definition Documentation

SDL_ECC_WIDTH_UNDEFINED

#define SDL_ECC_WIDTH_UNDEFINED   0x1

SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (28U)

SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (28U)

SDL_MSS_ECC_AGG_MSS_RAM_IDS_TOTAL_ENTRIES

#define SDL_MSS_ECC_AGG_MSS_RAM_IDS_TOTAL_ENTRIES   (8U)

SDL_DSS_ECC_AGG_RAM_IDS_TOTAL_ENTRIES

#define SDL_DSS_ECC_AGG_RAM_IDS_TOTAL_ENTRIES   (22U)

SDL_MSS_MCANA_ECC_RAM_IDS_TOTAL_ENTRIES

#define SDL_MSS_MCANA_ECC_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MSS_MCANB_ECC_RAM_IDS_TOTAL_ENTRIES

#define SDL_MSS_MCANB_ECC_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (8U)

SDL_ECC_Base_Address_TOTAL_ENTRIES

#define SDL_ECC_Base_Address_TOTAL_ENTRIES   (7U)

SDL_MSS_CPSW0_ECC_U_BASE

#define SDL_MSS_CPSW0_ECC_U_BASE   (SDL_MSS_CPSW_U_BASE + 0x3F000u)

SDL_TCM_PARITY_ERRFRC

#define SDL_TCM_PARITY_ERRFRC   (0x02120144)

TPCC_PARITY_CTRL

#define TPCC_PARITY_CTRL   (0x0212015Cu)

SDL_R5FSS0_CORE0_TPCC0_PARITY_STATUS

#define SDL_R5FSS0_CORE0_TPCC0_PARITY_STATUS   (0x02120160u)

DSS_TPCCA_PARITY_CTRL

#define DSS_TPCCA_PARITY_CTRL   (0x060200BCU)

DSS_TPCCB_PARITY_CTRL

#define DSS_TPCCB_PARITY_CTRL   (0x060200C0U)

DSS_TPCCC_PARITY_CTRL

#define DSS_TPCCC_PARITY_CTRL   (0x060200C4U)

SDL_R5FSS0_CORE0_TPCCA_PARITY_STATUS

#define SDL_R5FSS0_CORE0_TPCCA_PARITY_STATUS   (0x060200C8U)

SDL_R5FSS0_CORE0_TPCCB_PARITY_STATUS

#define SDL_R5FSS0_CORE0_TPCCB_PARITY_STATUS   (0x060200CCU)

SDL_R5FSS0_CORE0_TPCCC_PARITY_STATUS

#define SDL_R5FSS0_CORE0_TPCCC_PARITY_STATUS   (0x060200D0U)

Variable Documentation

SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_R5FSS0_CORE0_ECC_AGGR

SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_R5FSS0_CORE1_ECC_AGGR

SDL_MSS_ECC_AGG_MSS_MemEntries

const SDL_MemConfig_t SDL_MSS_ECC_AGG_MSS_MemEntries[SDL_MSS_ECC_AGG_MSS_RAM_IDS_TOTAL_ENTRIES]

Initial value:

=
{
    { SDL_MSS_ECC_AGG_MSS_MSS_L2RAMA_ECC_RAM_ID, 0x10200000u,
      SDL_MSS_ECC_AGG_MSS_MSS_L2RAMA_ECC_RAM_SIZE, 8u,
      SDL_MSS_ECC_AGG_MSS_MSS_L2RAMA_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_MSS_ECC_AGG_MSS_MSS_L2RAMB_ECC_RAM_ID,  0x10280000u,
      SDL_MSS_ECC_AGG_MSS_MSS_L2RAMB_ECC_RAM_SIZE, 8u,
      SDL_MSS_ECC_AGG_MSS_MSS_L2RAMB_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_MSS_ECC_AGG_MSS_MSS_MBOX_ECC_RAM_ID, 0xC5000000u,
      SDL_MSS_ECC_AGG_MSS_MSS_MBOX_ECC_RAM_SIZE, 8u,
      SDL_MSS_ECC_AGG_MSS_MSS_MBOX_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_MSS_ECC_AGG_MSS_MSS_RETRAM_ECC_RAM_ID, 0xC5010000u,
      SDL_MSS_ECC_AGG_MSS_MSS_RETRAM_ECC_RAM_SIZE, 8u,
      SDL_MSS_ECC_AGG_MSS_MSS_RETRAM_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_MSS_ECC_AGG_MSS_MSS_GPADC_DATA_RAM_ECC_RAM_ID, 0xC5030000u,
      SDL_MSS_ECC_AGG_MSS_MSS_GPADC_DATA_RAM_ECC_RAM_SIZE, 8u,
      SDL_MSS_ECC_AGG_MSS_MSS_GPADC_DATA_RAM_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A0_ECC_RAM_ID, 0u,
      SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A0_ECC_RAM_SIZE, 8u,
      SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A0_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A1_ECC_RAM_ID, 0u,
      SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A1_ECC_RAM_SIZE, 8u,
      SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A1_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_MSS_ECC_AGG_MSS_MSS_TPTC_B0_ECC_RAM_ID, 0u,
      SDL_MSS_ECC_AGG_MSS_MSS_TPTC_B0_ECC_RAM_SIZE, 8u,
      SDL_MSS_ECC_AGG_MSS_MSS_TPTC_B0_ECC_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MSS_ECC_AGG_MSS

SDL_DSS_ECC_AGG_MemEntries

const SDL_MemConfig_t SDL_DSS_ECC_AGG_MemEntries[SDL_DSS_ECC_AGG_RAM_IDS_TOTAL_ENTRIES]

---

This structure holds the memory config for each memory subtype SDL_DSS_ECC_AGG

SDL_MSS_MCANA_ECC_MemEntries

const SDL_MemConfig_t SDL_MSS_MCANA_ECC_MemEntries[SDL_MSS_MCANA_ECC_RAM_IDS_TOTAL_ENTRIES]

Initial value:

=
{
    { SDL_MSS_MCANA_ECC_MSS_MCANA_ECC_RAM_ID, 0u,
      SDL_MSS_MCANA_ECC_MSS_MCANA_ECC_RAM_SIZE, 4u,
      SDL_MSS_MCANA_ECC_MSS_MCANA_ECC_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MSS_MCANA_ECC

SDL_MSS_MCANB_ECC_MemEntries

const SDL_MemConfig_t SDL_MSS_MCANB_ECC_MemEntries[SDL_MSS_MCANB_ECC_RAM_IDS_TOTAL_ENTRIES]

Initial value:

=
{
    { SDL_MSS_MCANB_ECC_MSS_MCANB_ECC_RAM_ID, 0u,
      SDL_MSS_MCANB_ECC_MSS_MCANB_ECC_RAM_SIZE, 4u,
      SDL_MSS_MCANB_ECC_MSS_MCANB_ECC_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MSS_MCANB_ECC

SDL_CPSW3GCSS_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_CPSW3GCSS_ECC_AGGR_MemEntries[SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_RAM_ID, 0x0703E000u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_RAM_SIZE, 71u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_RAM_ID, 0u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_RAM_SIZE, 32u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_RAM_ID, 0u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_RAM_SIZE, 32u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_RAM_ID, 0u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_RAM_SIZE, 32u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_RAM_ID, 0u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_RAM_SIZE, 32u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_RAM_ID, 0u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_RAM_SIZE, 32u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_RAM_ID, 0u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_RAM_SIZE, 32u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_EST_RAM_ECC_RAM_ID, 0x07032000u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_EST_RAM_ECC_RAM_SIZE, 4u,
      SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_CPSW3GCSS_ECC_AGGR

SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE0_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_R5FSS0_CORE0_ECC_AGGR

SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE1_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_R5FSS0_CORE1_ECC_AGGR

SDL_MSS_ECC_AGG_MSS_RamIdTable

const SDL_RAMIdEntry_t SDL_MSS_ECC_AGG_MSS_RamIdTable[SDL_MSS_ECC_AGG_MSS_NUM_RAMS]

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MSS_ECC_AGG_MSS

SDL_DSS_ECC_AGG_RamIdTable

const SDL_RAMIdEntry_t SDL_DSS_ECC_AGG_RamIdTable[SDL_DSS_ECC_AGG_NUM_RAMS]

---

This structure holds the list of Ram Ids for each memory subtype in SDL_DSS_ECC_AGG

SDL_MSS_MCANA_ECC_RamIdTable

const SDL_RAMIdEntry_t SDL_MSS_MCANA_ECC_RamIdTable[SDL_MSS_MCANA_ECC_NUM_RAMS]

Initial value:

=
{
    { SDL_MSS_MCANA_ECC_MSS_MCANA_ECC_RAM_ID,
      SDL_MSS_MCANA_ECC_MSS_MCANA_ECC_INJECT_TYPE,
      SDL_MSS_MCANA_ECC_MSS_MCANA_ECC_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MSS_MCANA_ECC

SDL_MSS_MCANB_ECC_RamIdTable

const SDL_RAMIdEntry_t SDL_MSS_MCANB_ECC_RamIdTable[SDL_MSS_MCANB_ECC_NUM_RAMS]

Initial value:

=
{
    { SDL_MSS_MCANB_ECC_MSS_MCANB_ECC_RAM_ID,
      SDL_MSS_MCANB_ECC_MSS_MCANB_ECC_INJECT_TYPE,
      SDL_MSS_MCANB_ECC_MSS_MCANB_ECC_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MSS_MCANB_ECC

SDL_CPSW3GCSS_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_CPSW3GCSS_ECC_AGGR_RamIdTable[SDL_CPSW3GCSS_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_CPSW3GCSS_ECC_AGGR

SDL_ECC_aggrBaseAddressTable

SDL_ecc_aggrRegs* const SDL_ECC_aggrBaseAddressTable[SDL_ECC_Base_Address_TOTAL_ENTRIES]

static

Initial value:

=
{
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MSS_ECC_AGG_R5A_U_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MSS_ECC_AGG_R5B_U_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MSS_ECC_AGG_MSS_U_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_DSS_ECC_AGG_U_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MSS_MCANA_ECC_U_BASE )),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MSS_MCANB_ECC_U_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MSS_CPSW0_ECC_U_BASE)),
}

SDL_ECC_aggrTransBaseAddressTable

SDL_ecc_aggrRegs* SDL_ECC_aggrTransBaseAddressTable[SDL_ECC_MEMTYPE_MAX]

SDL_ECC_aggrTable

const SDL_EccAggrEntry_t SDL_ECC_aggrTable[SDL_ECC_MEMTYPE_MAX]

static