AM273x MCU+ SDK  09.02.00
am273x/sdl_ecc_soc.h
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1 /*
2  * SDL ECC
3  *
4  * Software Diagnostics Library module for ECC
5  *
6  * Copyright (c) Texas Instruments Incorporated 2022-2023
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  *
12  * Redistributions of source code must retain the above copyright
13  * notice, this list of conditions and the following disclaimer.
14  *
15  * Redistributions in binary form must reproduce the above copyright
16  * notice, this list of conditions and the following disclaimer in the
17  * documentation and/or other materials provided with the
18  * distribution.
19  *
20  * Neither the name of Texas Instruments Incorporated nor the names of
21  * its contributors may be used to endorse or promote products derived
22  * from this software without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35  *
36  */
37 
38 #ifndef INCLUDE_SDL_ECC_SOC_H_
39 #define INCLUDE_SDL_ECC_SOC_H_
40 
41 #include <stdint.h>
42 #include <sdl/sdl_ecc.h>
43 #include <sdl/ecc/sdl_ip_ecc.h>
44 #include <sdl/include/sdl_types.h>
45 #include <sdl/esm/soc/am273x/sdl_esm_core.h>
46 #include <sdl/ecc/sdl_ecc_priv.h>
47 #include <sdl/include/am273x/sdlr_soc_ecc_aggr.h>
48 #include <sdl/include/am273x/soc_config.h>
49 #include <sdl/include/am273x/sdlr_intr_esm_dss.h>
50 #include <sdl/include/am273x/sdlr_intr_esm_mss.h>
51 #include <sdl/include/am273x/sdlr_soc_baseaddress.h>
52 
53 
54 #define SDL_ECC_WIDTH_UNDEFINED 0x1
55 
56 /* define Max memEntries for each aggregator (i.e. the number of RAM ID's with * Wrapper type) */
57 #define SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (28U)
58 #define SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (28U)
59 #define SDL_MSS_ECC_AGG_MSS_RAM_IDS_TOTAL_ENTRIES (8U)
60 #define SDL_DSS_ECC_AGG_RAM_IDS_TOTAL_ENTRIES (22U)
61 #define SDL_MSS_MCANA_ECC_RAM_IDS_TOTAL_ENTRIES (1U)
62 #define SDL_MSS_MCANB_ECC_RAM_IDS_TOTAL_ENTRIES (1U)
63 #define SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (8U)
64 #define SDL_ECC_Base_Address_TOTAL_ENTRIES (7U)
65 
66 #define SDL_MSS_CPSW0_ECC_U_BASE (SDL_MSS_CPSW_U_BASE + 0x3F000u)
67 /* define parity control register addresses */
68 #define SDL_TCM_PARITY_ERRFRC (0x02120144)
69 
70 /* MSS TPCC */
71 #define TPCC_PARITY_CTRL (0x0212015Cu)
72 #define SDL_R5FSS0_CORE0_TPCC0_PARITY_STATUS (0x02120160u)
73 /* DSS TPCC */
74 #define DSS_TPCCA_PARITY_CTRL (0x060200BCU)
75 #define DSS_TPCCB_PARITY_CTRL (0x060200C0U)
76 #define DSS_TPCCC_PARITY_CTRL (0x060200C4U)
77 #define SDL_R5FSS0_CORE0_TPCCA_PARITY_STATUS (0x060200C8U)
78 #define SDL_R5FSS0_CORE0_TPCCB_PARITY_STATUS (0x060200CCU)
79 #define SDL_R5FSS0_CORE0_TPCCC_PARITY_STATUS (0x060200D0U)
80 
84 static const SDL_MemConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
85 {
86  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID, 0u,
87  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_SIZE, 4u,
88  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
89  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID, 0u,
90  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_SIZE, 4u,
91  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
92  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID, 0u,
93  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_SIZE, 4u,
94  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
95  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID, 0u,
96  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_SIZE, 4u,
97  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
98  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID, 0u,
99  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_SIZE, 8u,
100  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_ROW_WIDTH, ((bool)false) },
101  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID, 0u,
102  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_SIZE, 8u,
103  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_ROW_WIDTH, ((bool)false) },
104  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID, 0u,
105  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_SIZE, 8u,
106  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_ROW_WIDTH, ((bool)false) },
107  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID, 0u,
108  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_SIZE, 8u,
109  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_ROW_WIDTH, ((bool)false) },
110  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID, 0u,
111  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_SIZE, 4u,
112  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
113  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID, 0u,
114  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_SIZE, 4u,
115  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
116  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID, 0u,
117  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_SIZE, 4u,
118  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
119  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID, 0u,
120  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_SIZE, 4u,
121  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
122  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID, 0u,
123  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_SIZE, 4u,
124  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
125  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID, 0u,
126  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_SIZE, 4u,
127  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_ROW_WIDTH, ((bool)false) },
128  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID, 0u,
129  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_SIZE, 4u,
130  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_ROW_WIDTH, ((bool)false) },
131  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID, 0u,
132  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_SIZE, 4u,
133  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_ROW_WIDTH, ((bool)false) },
134  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID, 0u,
135  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_SIZE, 4u,
136  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_ROW_WIDTH, ((bool)false) },
137  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID, 0u,
138  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_SIZE, 4u,
139  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_ROW_WIDTH, ((bool)false) },
140  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID, 0u,
141  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_SIZE, 4u,
142  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_ROW_WIDTH, ((bool)false) },
143  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID, 0u,
144  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_SIZE, 4u,
145  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_ROW_WIDTH, ((bool)false) },
146  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID, 0u,
147  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_SIZE, 4u,
148  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_ROW_WIDTH, ((bool)false) },
149  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID, 0x0u,
150  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_SIZE, 4u,
151  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ROW_WIDTH, ((bool)true) },
152  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID, 0x00u,
153  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_SIZE, 4u,
154  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ROW_WIDTH, ((bool)true) },
155  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID, 0x00080000u,
156  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_SIZE, 4u,
157  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ROW_WIDTH, ((bool)true) },
158  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID, 0x00080000u,
159  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_SIZE, 4u,
160  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ROW_WIDTH, ((bool)true) },
161  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID, 0x00080000u,
162  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_SIZE, 4u,
163  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ROW_WIDTH, ((bool)true) },
164  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID, 0x00080000u,
165  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_SIZE, 4u,
166  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ROW_WIDTH, ((bool)true) },
167  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID, 0x02082000u,
168  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_SIZE, 4u,
169  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ROW_WIDTH, ((bool)true) },
170 };
171 
176 static const SDL_MemConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
177 {
178  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_ID, 0u,
179  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_SIZE, 4u,
180  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
181  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_ID, 0u,
182  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_SIZE, 4u,
183  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
184  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_ID, 0u,
185  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_SIZE, 4u,
186  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
187  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_ID, 0u,
188  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_SIZE, 4u,
189  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
190  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_ID, 0u,
191  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_SIZE, 8u,
192  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_ROW_WIDTH, ((bool)false) },
193  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_ID, 0u,
194  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_SIZE, 8u,
195  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_ROW_WIDTH, ((bool)false) },
196  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_ID, 0u,
197  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_SIZE, 8u,
198  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_ROW_WIDTH, ((bool)false) },
199  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_ID, 0u,
200  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_SIZE, 8u,
201  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_ROW_WIDTH, ((bool)false) },
202  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_ID, 0u,
203  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_SIZE, 4u,
204  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
205  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_ID, 0u,
206  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_SIZE, 4u,
207  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
208  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_ID, 0u,
209  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_SIZE, 4u,
210  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
211  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_ID, 0u,
212  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_SIZE, 4u,
213  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
214  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_ID, 0u,
215  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_SIZE, 4u,
216  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
217  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_ID, 0u,
218  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_SIZE, 4u,
219  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_ROW_WIDTH, ((bool)false) },
220  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_ID, 0u,
221  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_SIZE, 4u,
222  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_ROW_WIDTH, ((bool)false) },
223  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_ID, 0u,
224  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_SIZE, 4u,
225  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_ROW_WIDTH, ((bool)false) },
226  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_ID, 0u,
227  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_SIZE, 4u,
228  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_ROW_WIDTH, ((bool)false) },
229  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_ID, 0u,
230  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_SIZE, 4u,
231  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_ROW_WIDTH, ((bool)false) },
232  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_ID, 0u,
233  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_SIZE, 4u,
234  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_ROW_WIDTH, ((bool)false) },
235  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_ID, 0u,
236  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_SIZE, 4u,
237  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_ROW_WIDTH, ((bool)false) },
238  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_ID, 0u,
239  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_SIZE, 4u,
240  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_ROW_WIDTH, ((bool)false) },
241  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_ID, 0x4000u,
242  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_SIZE, 4u,
243  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_ROW_WIDTH, ((bool)true) },
244  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_ID, 0x4000u,
245  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_SIZE, 4u,
246  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_ROW_WIDTH, ((bool)true) },
247  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_ID, 0x00084000u,
248  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_SIZE, 4u,
249  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_ROW_WIDTH, ((bool)true) },
250  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_ID, 0x00084000u,
251  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_SIZE, 4u,
252  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_ROW_WIDTH, ((bool)true) },
253  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_ID, 0x00084000u,
254  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_SIZE, 4u,
255  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_ROW_WIDTH, ((bool)true) },
256  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_ID, 0x00084000u,
257  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_SIZE, 4u,
258  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_ROW_WIDTH, ((bool)true) },
259  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_ID, 0x020A2000u,
260  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_SIZE, 4u,
261  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_ROW_WIDTH, ((bool)true) },
262 };
263 
268 const SDL_MemConfig_t SDL_MSS_ECC_AGG_MSS_MemEntries[SDL_MSS_ECC_AGG_MSS_RAM_IDS_TOTAL_ENTRIES] =
269 {
270  { SDL_MSS_ECC_AGG_MSS_MSS_L2RAMA_ECC_RAM_ID, 0x10200000u,
271  SDL_MSS_ECC_AGG_MSS_MSS_L2RAMA_ECC_RAM_SIZE, 8u,
272  SDL_MSS_ECC_AGG_MSS_MSS_L2RAMA_ECC_ROW_WIDTH, ((bool)true) },
273  { SDL_MSS_ECC_AGG_MSS_MSS_L2RAMB_ECC_RAM_ID, 0x10280000u,
274  SDL_MSS_ECC_AGG_MSS_MSS_L2RAMB_ECC_RAM_SIZE, 8u,
275  SDL_MSS_ECC_AGG_MSS_MSS_L2RAMB_ECC_ROW_WIDTH, ((bool)true) },
276  { SDL_MSS_ECC_AGG_MSS_MSS_MBOX_ECC_RAM_ID, 0xC5000000u,
277  SDL_MSS_ECC_AGG_MSS_MSS_MBOX_ECC_RAM_SIZE, 8u,
278  SDL_MSS_ECC_AGG_MSS_MSS_MBOX_ECC_ROW_WIDTH, ((bool)true) },
279  { SDL_MSS_ECC_AGG_MSS_MSS_RETRAM_ECC_RAM_ID, 0xC5010000u,
280  SDL_MSS_ECC_AGG_MSS_MSS_RETRAM_ECC_RAM_SIZE, 8u,
281  SDL_MSS_ECC_AGG_MSS_MSS_RETRAM_ECC_ROW_WIDTH, ((bool)true) },
282  { SDL_MSS_ECC_AGG_MSS_MSS_GPADC_DATA_RAM_ECC_RAM_ID, 0xC5030000u,
283  SDL_MSS_ECC_AGG_MSS_MSS_GPADC_DATA_RAM_ECC_RAM_SIZE, 8u,
284  SDL_MSS_ECC_AGG_MSS_MSS_GPADC_DATA_RAM_ECC_ROW_WIDTH, ((bool)true) },
285  { SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A0_ECC_RAM_ID, 0u,
286  SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A0_ECC_RAM_SIZE, 8u,
287  SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A0_ECC_ROW_WIDTH, ((bool)false) },
288  { SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A1_ECC_RAM_ID, 0u,
289  SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A1_ECC_RAM_SIZE, 8u,
290  SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A1_ECC_ROW_WIDTH, ((bool)false) },
291  { SDL_MSS_ECC_AGG_MSS_MSS_TPTC_B0_ECC_RAM_ID, 0u,
292  SDL_MSS_ECC_AGG_MSS_MSS_TPTC_B0_ECC_RAM_SIZE, 8u,
293  SDL_MSS_ECC_AGG_MSS_MSS_TPTC_B0_ECC_ROW_WIDTH, ((bool)false) },
294 };
295 
300 const SDL_MemConfig_t SDL_DSS_ECC_AGG_MemEntries[SDL_DSS_ECC_AGG_RAM_IDS_TOTAL_ENTRIES] =
301 {
302  { SDL_DSS_ECC_AGG_DSS_L3RAMA_ECC_RAM_ID, 0x88000000u,
303  SDL_DSS_ECC_AGG_DSS_L3RAMA_ECC_RAM_SIZE, 8u,
304  SDL_DSS_ECC_AGG_DSS_L3RAMA_ECC_ROW_WIDTH, ((bool)true) },
305  { SDL_DSS_ECC_AGG_DSS_L3RAMB_ECC_RAM_ID, 0x88100000u,
306  SDL_DSS_ECC_AGG_DSS_L3RAMB_ECC_RAM_SIZE, 8u,
307  SDL_DSS_ECC_AGG_DSS_L3RAMB_ECC_ROW_WIDTH, ((bool)true) },
308  { SDL_DSS_ECC_AGG_DSS_L3RAMC_ECC_RAM_ID, 0x88200000u,
309  SDL_DSS_ECC_AGG_DSS_L3RAMC_ECC_RAM_SIZE, 8u,
310  SDL_DSS_ECC_AGG_DSS_L3RAMC_ECC_ROW_WIDTH, ((bool)true) },
311  { SDL_DSS_ECC_AGG_DSS_L3RAMD_ECC_RAM_ID, 0x88300000u,
312  SDL_DSS_ECC_AGG_DSS_L3RAMD_ECC_RAM_SIZE, 8u,
313  SDL_DSS_ECC_AGG_DSS_L3RAMD_ECC_ROW_WIDTH, ((bool)true) },
314  { SDL_DSS_ECC_AGG_DSS_MAILBOX_ECC_RAM_ID, 0x83100000u,
315  SDL_DSS_ECC_AGG_DSS_MAILBOX_ECC_RAM_SIZE, 8u,
316  SDL_DSS_ECC_AGG_DSS_MAILBOX_ECC_ROW_WIDTH, ((bool)true) },
317  { SDL_DSS_ECC_AGG_DSS_CM4_RAM_B0_ECC_RAM_ID, 0u,
318  SDL_DSS_ECC_AGG_DSS_CM4_RAM_B0_ECC_RAM_SIZE, 4u,
319  SDL_DSS_ECC_AGG_DSS_CM4_RAM_B0_ECC_ROW_WIDTH, ((bool)true) },
320  { SDL_DSS_ECC_AGG_DSS_CM4_RAM_B1_ECC_RAM_ID, 0u,
321  SDL_DSS_ECC_AGG_DSS_CM4_RAM_B1_ECC_RAM_SIZE, 4u,
322  SDL_DSS_ECC_AGG_DSS_CM4_RAM_B1_ECC_ROW_WIDTH, ((bool)true) },
323  { SDL_DSS_ECC_AGG_DSS_CM4_RAM_B2_ECC_RAM_ID, 0u,
324  SDL_DSS_ECC_AGG_DSS_CM4_RAM_B2_ECC_RAM_SIZE, 4u,
325  SDL_DSS_ECC_AGG_DSS_CM4_RAM_B2_ECC_ROW_WIDTH, ((bool)true) },
326  { SDL_DSS_ECC_AGG_DSS_CM4_MAILBOX_ECC_RAM_ID, 0x48000000u,
327  SDL_DSS_ECC_AGG_DSS_CM4_MAILBOX_ECC_RAM_SIZE, 8u,
328  SDL_DSS_ECC_AGG_DSS_CM4_MAILBOX_ECC_ROW_WIDTH, ((bool)true) },
329  { SDL_DSS_ECC_AGG_DSS_TPTC_A0_FIFO_ECC_RAM_ID, 0u,
330  SDL_DSS_ECC_AGG_DSS_TPTC_A0_FIFO_ECC_RAM_SIZE, 8u,
331  SDL_DSS_ECC_AGG_DSS_TPTC_A0_FIFO_ECC_ROW_WIDTH, ((bool)false) },
332  { SDL_DSS_ECC_AGG_DSS_TPTC_A1_FIFO_ECC_RAM_ID, 0u,
333  SDL_DSS_ECC_AGG_DSS_TPTC_A1_FIFO_ECC_RAM_SIZE, 8u,
334  SDL_DSS_ECC_AGG_DSS_TPTC_A1_FIFO_ECC_ROW_WIDTH, ((bool)false) },
335  { SDL_DSS_ECC_AGG_DSS_TPTC_B0_FIFO_ECC_RAM_ID, 0u,
336  SDL_DSS_ECC_AGG_DSS_TPTC_B0_FIFO_ECC_RAM_SIZE, 8u,
337  SDL_DSS_ECC_AGG_DSS_TPTC_B0_FIFO_ECC_ROW_WIDTH, ((bool)false) },
338  { SDL_DSS_ECC_AGG_DSS_TPTC_B1_FIFO_ECC_RAM_ID, 0u,
339  SDL_DSS_ECC_AGG_DSS_TPTC_B1_FIFO_ECC_RAM_SIZE, 8u,
340  SDL_DSS_ECC_AGG_DSS_TPTC_B1_FIFO_ECC_ROW_WIDTH, ((bool)false) },
341  { SDL_DSS_ECC_AGG_DSS_TPTC_C0_FIFO_ECC_RAM_ID, 0u,
342  SDL_DSS_ECC_AGG_DSS_TPTC_C0_FIFO_ECC_RAM_SIZE, 8u,
343  SDL_DSS_ECC_AGG_DSS_TPTC_C0_FIFO_ECC_ROW_WIDTH, ((bool)false) },
344  { SDL_DSS_ECC_AGG_DSS_TPTC_C1_FIFO_ECC_RAM_ID, 0u,
345  SDL_DSS_ECC_AGG_DSS_TPTC_C1_FIFO_ECC_RAM_SIZE, 8u,
346  SDL_DSS_ECC_AGG_DSS_TPTC_C1_FIFO_ECC_ROW_WIDTH, ((bool)false) },
347  { SDL_DSS_ECC_AGG_DSS_TPTC_C2_FIFO_ECC_RAM_ID, 0u,
348  SDL_DSS_ECC_AGG_DSS_TPTC_C2_FIFO_ECC_RAM_SIZE, 8u,
349  SDL_DSS_ECC_AGG_DSS_TPTC_C2_FIFO_ECC_ROW_WIDTH, ((bool)false) },
350  { SDL_DSS_ECC_AGG_DSS_TPTC_C3_FIFO_ECC_RAM_ID, 0u,
351  SDL_DSS_ECC_AGG_DSS_TPTC_C3_FIFO_ECC_RAM_SIZE, 8u,
352  SDL_DSS_ECC_AGG_DSS_TPTC_C3_FIFO_ECC_ROW_WIDTH, ((bool)false) },
353  { SDL_DSS_ECC_AGG_DSS_TPTC_C4_FIFO_ECC_RAM_ID, 0u,
354  SDL_DSS_ECC_AGG_DSS_TPTC_C4_FIFO_ECC_RAM_SIZE, 8u,
355  SDL_DSS_ECC_AGG_DSS_TPTC_C4_FIFO_ECC_ROW_WIDTH, ((bool)false) },
356  { SDL_DSS_ECC_AGG_DSS_TPTC_C5_FIFO_ECC_RAM_ID, 0u,
357  SDL_DSS_ECC_AGG_DSS_TPTC_C5_FIFO_ECC_RAM_SIZE, 8u,
358  SDL_DSS_ECC_AGG_DSS_TPTC_C5_FIFO_ECC_ROW_WIDTH, ((bool)false) },
359  { SDL_DSS_ECC_AGG_RSS_TPTC_A0_FIFO_ECC_RAM_ID, 0u,
360  SDL_DSS_ECC_AGG_RSS_TPTC_A0_FIFO_ECC_RAM_SIZE, 8u,
361  SDL_DSS_ECC_AGG_RSS_TPTC_A0_FIFO_ECC_ROW_WIDTH, ((bool)false) },
362  { SDL_DSS_ECC_AGG_RSS_TPTC_A1_FIFO_ECC_RAM_ID, 0u,
363  SDL_DSS_ECC_AGG_RSS_TPTC_A1_FIFO_ECC_RAM_SIZE, 8u,
364  SDL_DSS_ECC_AGG_RSS_TPTC_A1_FIFO_ECC_ROW_WIDTH, ((bool)false) },
365  { SDL_DSS_ECC_AGG_DSS_HWA_PARAM_RAM_ECC_RAM_ID, 0x06060000u,
366  SDL_DSS_ECC_AGG_DSS_HWA_PARAM_RAM_ECC_RAM_SIZE, 8u,
367  SDL_DSS_ECC_AGG_DSS_HWA_PARAM_RAM_ECC_ROW_WIDTH, ((bool)true) },
368 };
369 
374 const SDL_MemConfig_t SDL_MSS_MCANA_ECC_MemEntries[SDL_MSS_MCANA_ECC_RAM_IDS_TOTAL_ENTRIES] =
375 {
376  { SDL_MSS_MCANA_ECC_MSS_MCANA_ECC_RAM_ID, 0u,
377  SDL_MSS_MCANA_ECC_MSS_MCANA_ECC_RAM_SIZE, 4u,
378  SDL_MSS_MCANA_ECC_MSS_MCANA_ECC_ROW_WIDTH, ((bool)false) },
379 };
380 
385 const SDL_MemConfig_t SDL_MSS_MCANB_ECC_MemEntries[SDL_MSS_MCANB_ECC_RAM_IDS_TOTAL_ENTRIES] =
386 {
387  { SDL_MSS_MCANB_ECC_MSS_MCANB_ECC_RAM_ID, 0u,
388  SDL_MSS_MCANB_ECC_MSS_MCANB_ECC_RAM_SIZE, 4u,
389  SDL_MSS_MCANB_ECC_MSS_MCANB_ECC_ROW_WIDTH, ((bool)false) },
390 };
391 
396 static const SDL_MemConfig_t SDL_CPSW3GCSS_ECC_AGGR_MemEntries[SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
397 {
398  { SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_RAM_ID, 0x0703E000u,
399  SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_RAM_SIZE, 71u,
400  SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_ROW_WIDTH, ((bool)true) },
401  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_RAM_ID, 0u,
402  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_RAM_SIZE, 32u,
403  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_ROW_WIDTH, ((bool)false) },
404  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_RAM_ID, 0u,
405  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_RAM_SIZE, 32u,
406  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_ROW_WIDTH, ((bool)false) },
407  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_RAM_ID, 0u,
408  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_RAM_SIZE, 32u,
409  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_ROW_WIDTH, ((bool)false) },
410  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_RAM_ID, 0u,
411  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_RAM_SIZE, 32u,
412  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_ROW_WIDTH, ((bool)false) },
413  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_RAM_ID, 0u,
414  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_RAM_SIZE, 32u,
415  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_ROW_WIDTH, ((bool)false) },
416  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_RAM_ID, 0u,
417  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_RAM_SIZE, 32u,
418  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_ROW_WIDTH, ((bool)false) },
419  { SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_EST_RAM_ECC_RAM_ID, 0x07032000u,
420  SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_EST_RAM_ECC_RAM_SIZE, 4u,
421  SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
422 };
423 
428 static const SDL_RAMIdEntry_t SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE0_ECC_AGGR_NUM_RAMS] =
429 {
430  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID,
431  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_INJECT_TYPE,
432  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_ECC_TYPE,
433  0u,
434  NULL },
435  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID,
436  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_INJECT_TYPE,
437  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_ECC_TYPE,
438  0u,
439  NULL },
440  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID,
441  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_INJECT_TYPE,
442  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_ECC_TYPE,
443  0u,
444  NULL },
445  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID,
446  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_INJECT_TYPE,
447  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_ECC_TYPE,
448  0u,
449  NULL },
450  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID,
451  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_INJECT_TYPE,
452  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_ECC_TYPE,
453  0u,
454  NULL },
455  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID,
456  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_INJECT_TYPE,
457  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_ECC_TYPE,
458  0u,
459  NULL },
460  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID,
461  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_INJECT_TYPE,
462  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_ECC_TYPE,
463  0u,
464  NULL },
465  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID,
466  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_INJECT_TYPE,
467  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_ECC_TYPE,
468  0u,
469  NULL },
470  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID,
471  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_INJECT_TYPE,
472  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_ECC_TYPE,
473  0u,
474  NULL },
475  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID,
476  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_INJECT_TYPE,
477  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_ECC_TYPE,
478  0u,
479  NULL },
480  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID,
481  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_INJECT_TYPE,
482  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_ECC_TYPE,
483  0u,
484  NULL },
485  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID,
486  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_INJECT_TYPE,
487  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_ECC_TYPE,
488  0u,
489  NULL },
490  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID,
491  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_INJECT_TYPE,
492  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_ECC_TYPE,
493  0u,
494  NULL },
495  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID,
496  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_INJECT_TYPE,
497  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_ECC_TYPE,
498  0u,
499  NULL },
500  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID,
501  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_INJECT_TYPE,
502  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_ECC_TYPE,
503  0u,
504  NULL },
505  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID,
506  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_INJECT_TYPE,
507  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_ECC_TYPE,
508  0u,
509  NULL },
510  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID,
511  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_INJECT_TYPE,
512  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_ECC_TYPE,
513  0u,
514  NULL },
515  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID,
516  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_INJECT_TYPE,
517  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_ECC_TYPE,
518  0u,
519  NULL },
520  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID,
521  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_INJECT_TYPE,
522  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_ECC_TYPE,
523  0u,
524  NULL },
525  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID,
526  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_INJECT_TYPE,
527  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_ECC_TYPE,
528  0u,
529  NULL },
530  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID,
531  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_INJECT_TYPE,
532  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_ECC_TYPE,
533  0u,
534  NULL },
535  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID,
536  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_INJECT_TYPE,
537  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ECC_TYPE,
538  0u,
539  NULL },
540  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID,
541  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_INJECT_TYPE,
542  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ECC_TYPE,
543  0u,
544  NULL },
545  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID,
546  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_INJECT_TYPE,
547  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ECC_TYPE,
548  0u,
549  NULL },
550  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID,
551  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_INJECT_TYPE,
552  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ECC_TYPE,
553  0u,
554  NULL },
555  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID,
556  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_INJECT_TYPE,
557  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ECC_TYPE,
558  0u,
559  NULL },
560  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID,
561  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_INJECT_TYPE,
562  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ECC_TYPE,
563  0u,
564  NULL },
565  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID,
566  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_INJECT_TYPE,
567  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ECC_TYPE,
568  0u,
569  NULL },
570 };
571 
576 static const SDL_RAMIdEntry_t SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE1_ECC_AGGR_NUM_RAMS] =
577 {
578  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_ID,
579  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_INJECT_TYPE,
580  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_ECC_TYPE,
581  0u,
582  NULL },
583  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_ID,
584  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_INJECT_TYPE,
585  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_ECC_TYPE,
586  0u,
587  NULL },
588  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_ID,
589  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_INJECT_TYPE,
590  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_ECC_TYPE,
591  0u,
592  NULL },
593  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_ID,
594  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_INJECT_TYPE,
595  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_ECC_TYPE,
596  0u,
597  NULL },
598  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_ID,
599  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_INJECT_TYPE,
600  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_ECC_TYPE,
601  0u,
602  NULL },
603  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_ID,
604  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_INJECT_TYPE,
605  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_ECC_TYPE,
606  0u,
607  NULL },
608  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_ID,
609  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_INJECT_TYPE,
610  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_ECC_TYPE,
611  0u,
612  NULL },
613  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_ID,
614  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_INJECT_TYPE,
615  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_ECC_TYPE,
616  0u,
617  NULL },
618  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_ID,
619  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_INJECT_TYPE,
620  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_ECC_TYPE,
621  0u,
622  NULL },
623  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_ID,
624  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_INJECT_TYPE,
625  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_ECC_TYPE,
626  0u,
627  NULL },
628  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_ID,
629  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_INJECT_TYPE,
630  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_ECC_TYPE,
631  0u,
632  NULL },
633  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_ID,
634  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_INJECT_TYPE,
635  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_ECC_TYPE,
636  0u,
637  NULL },
638  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_ID,
639  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_INJECT_TYPE,
640  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_ECC_TYPE,
641  0u,
642  NULL },
643  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_ID,
644  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_INJECT_TYPE,
645  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_ECC_TYPE,
646  0u,
647  NULL },
648  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_ID,
649  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_INJECT_TYPE,
650  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_ECC_TYPE,
651  0u,
652  NULL },
653  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_ID,
654  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_INJECT_TYPE,
655  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_ECC_TYPE,
656  0u,
657  NULL },
658  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_ID,
659  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_INJECT_TYPE,
660  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_ECC_TYPE,
661  0u,
662  NULL },
663  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_ID,
664  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_INJECT_TYPE,
665  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_ECC_TYPE,
666  0u,
667  NULL },
668  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_ID,
669  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_INJECT_TYPE,
670  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_ECC_TYPE,
671  0u,
672  NULL },
673  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_ID,
674  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_INJECT_TYPE,
675  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_ECC_TYPE,
676  0u,
677  NULL },
678  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_ID,
679  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_INJECT_TYPE,
680  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_ECC_TYPE,
681  0u,
682  NULL },
683  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_ID,
684  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_INJECT_TYPE,
685  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_ECC_TYPE,
686  0u,
687  NULL },
688  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_ID,
689  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_INJECT_TYPE,
690  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_ECC_TYPE,
691  0u,
692  NULL },
693  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_ID,
694  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_INJECT_TYPE,
695  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_ECC_TYPE,
696  0u,
697  NULL },
698  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_ID,
699  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_INJECT_TYPE,
700  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_ECC_TYPE,
701  0u,
702  NULL },
703  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_ID,
704  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_INJECT_TYPE,
705  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_ECC_TYPE,
706  0u,
707  NULL },
708  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_ID,
709  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_INJECT_TYPE,
710  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_ECC_TYPE,
711  0u,
712  NULL },
713  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_ID,
714  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_INJECT_TYPE,
715  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_ECC_TYPE,
716  0u,
717  NULL },
718 };
719 
724 const SDL_RAMIdEntry_t SDL_MSS_ECC_AGG_MSS_RamIdTable[SDL_MSS_ECC_AGG_MSS_NUM_RAMS] =
725 {
726  { SDL_MSS_ECC_AGG_MSS_MSS_L2RAMA_ECC_RAM_ID,
727  SDL_MSS_ECC_AGG_MSS_MSS_L2RAMA_ECC_INJECT_TYPE,
728  SDL_MSS_ECC_AGG_MSS_MSS_L2RAMA_ECC_ECC_TYPE,
729  0u,
730  NULL },
731  { SDL_MSS_ECC_AGG_MSS_MSS_L2RAMB_ECC_RAM_ID,
732  SDL_MSS_ECC_AGG_MSS_MSS_L2RAMB_ECC_INJECT_TYPE,
733  SDL_MSS_ECC_AGG_MSS_MSS_L2RAMB_ECC_ECC_TYPE,
734  0u,
735  NULL },
736  { SDL_MSS_ECC_AGG_MSS_MSS_MBOX_ECC_RAM_ID,
737  SDL_MSS_ECC_AGG_MSS_MSS_MBOX_ECC_INJECT_TYPE,
738  SDL_MSS_ECC_AGG_MSS_MSS_MBOX_ECC_ECC_TYPE,
739  0u,
740  NULL },
741  { SDL_MSS_ECC_AGG_MSS_MSS_RETRAM_ECC_RAM_ID,
742  SDL_MSS_ECC_AGG_MSS_MSS_RETRAM_ECC_INJECT_TYPE,
743  SDL_MSS_ECC_AGG_MSS_MSS_RETRAM_ECC_ECC_TYPE,
744  0u,
745  NULL },
746  { SDL_MSS_ECC_AGG_MSS_MSS_GPADC_DATA_RAM_ECC_RAM_ID,
747  SDL_MSS_ECC_AGG_MSS_MSS_GPADC_DATA_RAM_ECC_INJECT_TYPE,
748  SDL_MSS_ECC_AGG_MSS_MSS_GPADC_DATA_RAM_ECC_ECC_TYPE,
749  0u,
750  NULL },
751  { SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A0_ECC_RAM_ID,
752  SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A0_ECC_INJECT_TYPE,
753  SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A0_ECC_ECC_TYPE,
754  0u,
755  NULL },
756  { SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A1_ECC_RAM_ID,
757  SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A1_ECC_INJECT_TYPE,
758  SDL_MSS_ECC_AGG_MSS_MSS_TPTC_A1_ECC_ECC_TYPE,
759  0u,
760  NULL },
761  { SDL_MSS_ECC_AGG_MSS_MSS_TPTC_B0_ECC_RAM_ID,
762  SDL_MSS_ECC_AGG_MSS_MSS_TPTC_B0_ECC_INJECT_TYPE,
763  SDL_MSS_ECC_AGG_MSS_MSS_TPTC_B0_ECC_ECC_TYPE,
764  0u,
765  NULL },
766 };
767 
772 const SDL_RAMIdEntry_t SDL_DSS_ECC_AGG_RamIdTable[SDL_DSS_ECC_AGG_NUM_RAMS] =
773 {
774  { SDL_DSS_ECC_AGG_DSS_L3RAMA_ECC_RAM_ID,
775  SDL_DSS_ECC_AGG_DSS_L3RAMA_ECC_INJECT_TYPE,
776  SDL_DSS_ECC_AGG_DSS_L3RAMA_ECC_ECC_TYPE,
777  0u,
778  NULL },
779  { SDL_DSS_ECC_AGG_DSS_L3RAMB_ECC_RAM_ID,
780  SDL_DSS_ECC_AGG_DSS_L3RAMB_ECC_INJECT_TYPE,
781  SDL_DSS_ECC_AGG_DSS_L3RAMB_ECC_ECC_TYPE,
782  0u,
783  NULL },
784  { SDL_DSS_ECC_AGG_DSS_L3RAMC_ECC_RAM_ID,
785  SDL_DSS_ECC_AGG_DSS_L3RAMC_ECC_INJECT_TYPE,
786  SDL_DSS_ECC_AGG_DSS_L3RAMC_ECC_ECC_TYPE,
787  0u,
788  NULL },
789  { SDL_DSS_ECC_AGG_DSS_L3RAMD_ECC_RAM_ID,
790  SDL_DSS_ECC_AGG_DSS_L3RAMD_ECC_INJECT_TYPE,
791  SDL_DSS_ECC_AGG_DSS_L3RAMD_ECC_ECC_TYPE,
792  0u,
793  NULL },
794  { SDL_DSS_ECC_AGG_DSS_MAILBOX_ECC_RAM_ID,
795  SDL_DSS_ECC_AGG_DSS_MAILBOX_ECC_INJECT_TYPE,
796  SDL_DSS_ECC_AGG_DSS_MAILBOX_ECC_ECC_TYPE,
797  0u,
798  NULL },
799  { SDL_DSS_ECC_AGG_DSS_CM4_RAM_B0_ECC_RAM_ID,
800  SDL_DSS_ECC_AGG_DSS_CM4_RAM_B0_ECC_INJECT_TYPE,
801  SDL_DSS_ECC_AGG_DSS_CM4_RAM_B0_ECC_ECC_TYPE,
802  0u,
803  NULL },
804  { SDL_DSS_ECC_AGG_DSS_CM4_RAM_B1_ECC_RAM_ID,
805  SDL_DSS_ECC_AGG_DSS_CM4_RAM_B1_ECC_INJECT_TYPE,
806  SDL_DSS_ECC_AGG_DSS_CM4_RAM_B1_ECC_ECC_TYPE,
807  0u,
808  NULL },
809  { SDL_DSS_ECC_AGG_DSS_CM4_RAM_B2_ECC_RAM_ID,
810  SDL_DSS_ECC_AGG_DSS_CM4_RAM_B2_ECC_INJECT_TYPE,
811  SDL_DSS_ECC_AGG_DSS_CM4_RAM_B2_ECC_ECC_TYPE,
812  0u,
813  NULL },
814  { SDL_DSS_ECC_AGG_DSS_CM4_MAILBOX_ECC_RAM_ID,
815  SDL_DSS_ECC_AGG_DSS_CM4_MAILBOX_ECC_INJECT_TYPE,
816  SDL_DSS_ECC_AGG_DSS_CM4_MAILBOX_ECC_ECC_TYPE,
817  0u,
818  NULL },
819  { SDL_DSS_ECC_AGG_DSS_TPTC_A0_FIFO_ECC_RAM_ID,
820  SDL_DSS_ECC_AGG_DSS_TPTC_A0_FIFO_ECC_INJECT_TYPE,
821  SDL_DSS_ECC_AGG_DSS_TPTC_A0_FIFO_ECC_ECC_TYPE,
822  0u,
823  NULL },
824  { SDL_DSS_ECC_AGG_DSS_TPTC_A1_FIFO_ECC_RAM_ID,
825  SDL_DSS_ECC_AGG_DSS_TPTC_A1_FIFO_ECC_INJECT_TYPE,
826  SDL_DSS_ECC_AGG_DSS_TPTC_A1_FIFO_ECC_ECC_TYPE,
827  0u,
828  NULL },
829  { SDL_DSS_ECC_AGG_DSS_TPTC_B0_FIFO_ECC_RAM_ID,
830  SDL_DSS_ECC_AGG_DSS_TPTC_B0_FIFO_ECC_INJECT_TYPE,
831  SDL_DSS_ECC_AGG_DSS_TPTC_B0_FIFO_ECC_ECC_TYPE,
832  0u,
833  NULL },
834  { SDL_DSS_ECC_AGG_DSS_TPTC_B1_FIFO_ECC_RAM_ID,
835  SDL_DSS_ECC_AGG_DSS_TPTC_B1_FIFO_ECC_INJECT_TYPE,
836  SDL_DSS_ECC_AGG_DSS_TPTC_B1_FIFO_ECC_ECC_TYPE,
837  0u,
838  NULL },
839  { SDL_DSS_ECC_AGG_DSS_TPTC_C0_FIFO_ECC_RAM_ID,
840  SDL_DSS_ECC_AGG_DSS_TPTC_C0_FIFO_ECC_INJECT_TYPE,
841  SDL_DSS_ECC_AGG_DSS_TPTC_C0_FIFO_ECC_ECC_TYPE,
842  0u,
843  NULL },
844  { SDL_DSS_ECC_AGG_DSS_TPTC_C1_FIFO_ECC_RAM_ID,
845  SDL_DSS_ECC_AGG_DSS_TPTC_C1_FIFO_ECC_INJECT_TYPE,
846  SDL_DSS_ECC_AGG_DSS_TPTC_C1_FIFO_ECC_ECC_TYPE,
847  0u,
848  NULL },
849  { SDL_DSS_ECC_AGG_DSS_TPTC_C2_FIFO_ECC_RAM_ID,
850  SDL_DSS_ECC_AGG_DSS_TPTC_C2_FIFO_ECC_INJECT_TYPE,
851  SDL_DSS_ECC_AGG_DSS_TPTC_C2_FIFO_ECC_ECC_TYPE,
852  0u,
853  NULL },
854  { SDL_DSS_ECC_AGG_DSS_TPTC_C3_FIFO_ECC_RAM_ID,
855  SDL_DSS_ECC_AGG_DSS_TPTC_C3_FIFO_ECC_INJECT_TYPE,
856  SDL_DSS_ECC_AGG_DSS_TPTC_C3_FIFO_ECC_ECC_TYPE,
857  0u,
858  NULL },
859  { SDL_DSS_ECC_AGG_DSS_TPTC_C4_FIFO_ECC_RAM_ID,
860  SDL_DSS_ECC_AGG_DSS_TPTC_C4_FIFO_ECC_INJECT_TYPE,
861  SDL_DSS_ECC_AGG_DSS_TPTC_C4_FIFO_ECC_ECC_TYPE,
862  0u,
863  NULL },
864  { SDL_DSS_ECC_AGG_DSS_TPTC_C5_FIFO_ECC_RAM_ID,
865  SDL_DSS_ECC_AGG_DSS_TPTC_C5_FIFO_ECC_INJECT_TYPE,
866  SDL_DSS_ECC_AGG_DSS_TPTC_C5_FIFO_ECC_ECC_TYPE,
867  0u,
868  NULL },
869  { SDL_DSS_ECC_AGG_RSS_TPTC_A0_FIFO_ECC_RAM_ID,
870  SDL_DSS_ECC_AGG_RSS_TPTC_A0_FIFO_ECC_INJECT_TYPE,
871  SDL_DSS_ECC_AGG_RSS_TPTC_A0_FIFO_ECC_ECC_TYPE,
872  0u,
873  NULL },
874  { SDL_DSS_ECC_AGG_RSS_TPTC_A1_FIFO_ECC_RAM_ID,
875  SDL_DSS_ECC_AGG_RSS_TPTC_A1_FIFO_ECC_INJECT_TYPE,
876  SDL_DSS_ECC_AGG_RSS_TPTC_A1_FIFO_ECC_ECC_TYPE,
877  0u,
878  NULL },
879  { SDL_DSS_ECC_AGG_DSS_HWA_PARAM_RAM_ECC_RAM_ID,
880  SDL_DSS_ECC_AGG_DSS_HWA_PARAM_RAM_ECC_INJECT_TYPE,
881  SDL_DSS_ECC_AGG_DSS_HWA_PARAM_RAM_ECC_ECC_TYPE,
882  0u,
883  NULL },
884 };
885 
890 const SDL_RAMIdEntry_t SDL_MSS_MCANA_ECC_RamIdTable[SDL_MSS_MCANA_ECC_NUM_RAMS] =
891 {
892  { SDL_MSS_MCANA_ECC_MSS_MCANA_ECC_RAM_ID,
893  SDL_MSS_MCANA_ECC_MSS_MCANA_ECC_INJECT_TYPE,
894  SDL_MSS_MCANA_ECC_MSS_MCANA_ECC_ECC_TYPE,
895  0u,
896  NULL },
897 };
898 
903 const SDL_RAMIdEntry_t SDL_MSS_MCANB_ECC_RamIdTable[SDL_MSS_MCANB_ECC_NUM_RAMS] =
904 {
905  { SDL_MSS_MCANB_ECC_MSS_MCANB_ECC_RAM_ID,
906  SDL_MSS_MCANB_ECC_MSS_MCANB_ECC_INJECT_TYPE,
907  SDL_MSS_MCANB_ECC_MSS_MCANB_ECC_ECC_TYPE,
908  0u,
909  NULL },
910 };
911 
916 static const SDL_RAMIdEntry_t SDL_CPSW3GCSS_ECC_AGGR_RamIdTable[SDL_CPSW3GCSS_ECC_AGGR_NUM_RAMS] =
917 {
918  { SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_RAM_ID,
919  SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_INJECT_TYPE,
920  SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_ECC_TYPE,
921  0u,
922  NULL },
923  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_RAM_ID,
924  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_INJECT_TYPE,
925  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_ECC_TYPE,
926  0u,
927  NULL },
928  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_RAM_ID,
929  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_INJECT_TYPE,
930  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_ECC_TYPE,
931  0u,
932  NULL },
933  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_RAM_ID,
934  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_INJECT_TYPE,
935  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_ECC_TYPE,
936  0u,
937  NULL },
938  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_RAM_ID,
939  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_INJECT_TYPE,
940  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_ECC_TYPE,
941  0u,
942  NULL },
943  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_RAM_ID,
944  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_INJECT_TYPE,
945  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_ECC_TYPE,
946  0u,
947  NULL },
948  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_RAM_ID,
949  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_INJECT_TYPE,
950  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_ECC_TYPE,
951  0u,
952  NULL },
953  { SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_EST_RAM_ECC_RAM_ID,
954  SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_EST_RAM_ECC_INJECT_TYPE,
955  SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_EST_RAM_ECC_ECC_TYPE,
956  0u,
957  NULL },
958 };
959 
960 static SDL_ecc_aggrRegs * const SDL_ECC_aggrBaseAddressTable[SDL_ECC_Base_Address_TOTAL_ENTRIES] =
961 {
962  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MSS_ECC_AGG_R5A_U_BASE)),
963  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MSS_ECC_AGG_R5B_U_BASE)),
964  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MSS_ECC_AGG_MSS_U_BASE)),
965  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_DSS_ECC_AGG_U_BASE)),
966  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MSS_MCANA_ECC_U_BASE )),
967  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MSS_MCANB_ECC_U_BASE)),
968  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MSS_CPSW0_ECC_U_BASE)),
969 };
970 
971 SDL_ecc_aggrRegs * SDL_ECC_aggrTransBaseAddressTable[SDL_ECC_MEMTYPE_MAX];
974 static const SDL_EccAggrEntry_t SDL_ECC_aggrTable[SDL_ECC_MEMTYPE_MAX] =
975 {
976 
977  /* Index: SDL_MSS_ECC_AGG_R5A (0) */
978  {
979  SDL_R5FSS0_CORE0_ECC_AGGR_NUM_RAMS,
980  SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable,
981  SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
982  SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries,
983  SDL_ESM_INST_MSS_ESM,
984  SDL_ESMG1_ECCAGGA_SERR,
985  SDL_ESMG1_ECCAGGA_UERR
986  },
987  /* Index: SDL_MSS_ECC_AGG_R5B (1) */
988  {
989  SDL_R5FSS0_CORE1_ECC_AGGR_NUM_RAMS,
990  SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable,
991  SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
992  SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries,
993  SDL_ESM_INST_MSS_ESM,
994  SDL_ESMG1_ECCAGGB_SERR,
995  SDL_ESMG1_ECCAGGB_UERR
996  },
997  /* Index: SDL_MSS_ECC_AGG_MSS (2) */
998  {
999  SDL_MSS_ECC_AGG_MSS_NUM_RAMS,
1000  SDL_MSS_ECC_AGG_MSS_RamIdTable,
1001  SDL_MSS_ECC_AGG_MSS_RAM_IDS_TOTAL_ENTRIES,
1002  SDL_MSS_ECC_AGG_MSS_MemEntries,
1003  SDL_ESM_INST_MSS_ESM,
1004  SDL_ESMG1_ECCAGGMSS_SERR,
1005  SDL_ESMG1_ECCAGGMSS_UERR
1006  },
1007  /* Index: SDL_DSS_ECC_AGG (3) */
1008  {
1009  SDL_DSS_ECC_AGG_NUM_RAMS,
1010  SDL_DSS_ECC_AGG_RamIdTable,
1011  SDL_DSS_ECC_AGG_RAM_IDS_TOTAL_ENTRIES,
1012  SDL_DSS_ECC_AGG_MemEntries,
1013  SDL_ESM_INST_DSS_ESM,
1014  SDL_DSS_ESMG1_DSS_ECC_AGG_SERR,
1015  SDL_DSS_ESMG1_DSS_ECC_AGG_UERR
1016  },
1017  /* Index: SDL_MSS_MCANA_ECC (4) */
1018  {
1019  SDL_MSS_MCANA_ECC_NUM_RAMS,
1020  SDL_MSS_MCANA_ECC_RamIdTable,
1021  SDL_MSS_MCANA_ECC_RAM_IDS_TOTAL_ENTRIES,
1022  SDL_MSS_MCANA_ECC_MemEntries,
1023  SDL_ESM_INST_MSS_ESM,
1024  SDL_ESMG1_MCANA_SERR,
1025  SDL_ESMG1_MCANA_UERR
1026  },
1027  /* Index: SDL_MSS_MCANB_ECC (5) */
1028  {
1029  SDL_MSS_MCANB_ECC_NUM_RAMS,
1030  SDL_MSS_MCANB_ECC_RamIdTable,
1031  SDL_MSS_MCANB_ECC_RAM_IDS_TOTAL_ENTRIES,
1032  SDL_MSS_MCANB_ECC_MemEntries,
1033  SDL_ESM_INST_MSS_ESM,
1034  SDL_ESMG1_MCANB_SERR,
1035  SDL_ESMG1_MCANB_UERR
1036  },
1037  /* Index: SDL_CPSW3GCSS_ECC_AGGR (6) */
1038  {
1039  SDL_CPSW3GCSS_ECC_AGGR_NUM_RAMS,
1040  SDL_CPSW3GCSS_ECC_AGGR_RamIdTable,
1041  SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1042  SDL_CPSW3GCSS_ECC_AGGR_MemEntries,
1043  SDL_ESM_INST_MSS_ESM,
1044  SDL_ESMG1_CPSW_SERR,
1045  SDL_ESMG1_CPSW_UERR,
1046  }
1047 
1048  };
1049  #endif /* INCLUDE_SDL_ECC_SOC_H_ */
SDL_MSS_ECC_AGG_MSS_MemEntries
const SDL_MemConfig_t SDL_MSS_ECC_AGG_MSS_MemEntries[SDL_MSS_ECC_AGG_MSS_RAM_IDS_TOTAL_ENTRIES]
Definition: am273x/sdl_ecc_soc.h:268
SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE0_ECC_AGGR_NUM_RAMS]
Definition: am273x/sdl_ecc_soc.h:428
SDL_ECC_WIDTH_UNDEFINED
#define SDL_ECC_WIDTH_UNDEFINED
Definition: am273x/sdl_ecc_soc.h:54
SDL_ecc_aggrRegs
Definition: V1/sdlr_ecc.h:53
SDL_MSS_MCANA_ECC_MemEntries
const SDL_MemConfig_t SDL_MSS_MCANA_ECC_MemEntries[SDL_MSS_MCANA_ECC_RAM_IDS_TOTAL_ENTRIES]
Definition: am273x/sdl_ecc_soc.h:374
SDL_DSS_ECC_AGG_RAM_IDS_TOTAL_ENTRIES
#define SDL_DSS_ECC_AGG_RAM_IDS_TOTAL_ENTRIES
Definition: am273x/sdl_ecc_soc.h:60
SDL_DSS_ECC_AGG_RamIdTable
const SDL_RAMIdEntry_t SDL_DSS_ECC_AGG_RamIdTable[SDL_DSS_ECC_AGG_NUM_RAMS]
Definition: am273x/sdl_ecc_soc.h:772
SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: am273x/sdl_ecc_soc.h:84
SDL_CPSW3GCSS_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_CPSW3GCSS_ECC_AGGR_MemEntries[SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: am273x/sdl_ecc_soc.h:396
SDL_DSS_ECC_AGG_MemEntries
const SDL_MemConfig_t SDL_DSS_ECC_AGG_MemEntries[SDL_DSS_ECC_AGG_RAM_IDS_TOTAL_ENTRIES]
Definition: am273x/sdl_ecc_soc.h:300
SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: am273x/sdl_ecc_soc.h:57
SDL_CPSW3GCSS_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_CPSW3GCSS_ECC_AGGR_RamIdTable[SDL_CPSW3GCSS_ECC_AGGR_NUM_RAMS]
Definition: am273x/sdl_ecc_soc.h:916
SDL_MSS_MCANB_ECC_RamIdTable
const SDL_RAMIdEntry_t SDL_MSS_MCANB_ECC_RamIdTable[SDL_MSS_MCANB_ECC_NUM_RAMS]
Definition: am273x/sdl_ecc_soc.h:903
SDL_MSS_CPSW0_ECC_U_BASE
#define SDL_MSS_CPSW0_ECC_U_BASE
Definition: am273x/sdl_ecc_soc.h:66
sdl_ip_ecc.h
SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: am273x/sdl_ecc_soc.h:58
SDL_MSS_MCANA_ECC_RamIdTable
const SDL_RAMIdEntry_t SDL_MSS_MCANA_ECC_RamIdTable[SDL_MSS_MCANA_ECC_NUM_RAMS]
Definition: am273x/sdl_ecc_soc.h:890
SDL_ECC_Base_Address_TOTAL_ENTRIES
#define SDL_ECC_Base_Address_TOTAL_ENTRIES
Definition: am273x/sdl_ecc_soc.h:64
SDL_MemConfig_t
Definition: sdl_ecc_priv.h:88
sdl_ecc.h
Header file contains enumerations, structure definitions and function.
SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: am273x/sdl_ecc_soc.h:63
SDL_ECC_aggrBaseAddressTable
static SDL_ecc_aggrRegs *const SDL_ECC_aggrBaseAddressTable[SDL_ECC_Base_Address_TOTAL_ENTRIES]
Definition: am273x/sdl_ecc_soc.h:960
SDL_ECC_aggrTransBaseAddressTable
SDL_ecc_aggrRegs * SDL_ECC_aggrTransBaseAddressTable[SDL_ECC_MEMTYPE_MAX]
Definition: am273x/sdl_ecc_soc.h:971
SDL_MSS_ECC_AGG_MSS_RamIdTable
const SDL_RAMIdEntry_t SDL_MSS_ECC_AGG_MSS_RamIdTable[SDL_MSS_ECC_AGG_MSS_NUM_RAMS]
Definition: am273x/sdl_ecc_soc.h:724
SDL_RAMIdEntry_t
Definition: sdl_ecc_priv.h:63
SDL_ECC_aggrTable
static const SDL_EccAggrEntry_t SDL_ECC_aggrTable[SDL_ECC_MEMTYPE_MAX]
Definition: am273x/sdl_ecc_soc.h:974
SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE1_ECC_AGGR_NUM_RAMS]
Definition: am273x/sdl_ecc_soc.h:576
SDL_MSS_MCANB_ECC_MemEntries
const SDL_MemConfig_t SDL_MSS_MCANB_ECC_MemEntries[SDL_MSS_MCANB_ECC_RAM_IDS_TOTAL_ENTRIES]
Definition: am273x/sdl_ecc_soc.h:385
SDL_EccAggrEntry_t
Definition: sdl_ecc_priv.h:104
SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: am273x/sdl_ecc_soc.h:176
SDL_MSS_MCANA_ECC_RAM_IDS_TOTAL_ENTRIES
#define SDL_MSS_MCANA_ECC_RAM_IDS_TOTAL_ENTRIES
Definition: am273x/sdl_ecc_soc.h:61
SDL_MSS_MCANB_ECC_RAM_IDS_TOTAL_ENTRIES
#define SDL_MSS_MCANB_ECC_RAM_IDS_TOTAL_ENTRIES
Definition: am273x/sdl_ecc_soc.h:62
SDL_MSS_ECC_AGG_MSS_RAM_IDS_TOTAL_ENTRIES
#define SDL_MSS_ECC_AGG_MSS_RAM_IDS_TOTAL_ENTRIES
Definition: am273x/sdl_ecc_soc.h:59
sdl_ecc_priv.h