Detailed Description

RCM Analog register TW Control Registers.

Data Fields
uint32_t	b1_AdcEn: 1

uint32_t	b1_AdcStartConv: 1

uint32_t	b1_AdcReset: 1

uint32_t	b1_AdcInpBufEn: 1

uint32_t	b1_AdcRefBufEn: 1

uint32_t	b3_AdcRefSel_2_0: 3

uint32_t	b1_TsDiffInpBufEn: 1

uint32_t	b1_TsSeInpBufEn: 1

uint32_t	b1_IforceExtCtrl: 1

uint32_t	b1_VrefExtCtrl: 1

uint32_t	b1_VinExtCtrl: 1

uint32_t	b1_AnaTmuxBufBypass: 1

uint32_t	b1_AnaTmuxBufEn: 1

uint32_t	b5_RtrimTw_4_0: 5

uint32_t	b12_Reserved1: 12

Field Documentation

◆ b1_AdcEn

uint32_t U_MSS_TOPRCM_ANA_REG_TW_CTRL_REG_LOWV_REG::b1_AdcEn

bits 0: 0

◆ b1_AdcStartConv

uint32_t U_MSS_TOPRCM_ANA_REG_TW_CTRL_REG_LOWV_REG::b1_AdcStartConv

bits 1: 1

◆ b1_AdcReset

uint32_t U_MSS_TOPRCM_ANA_REG_TW_CTRL_REG_LOWV_REG::b1_AdcReset

bits 2: 2

◆ b1_AdcInpBufEn

uint32_t U_MSS_TOPRCM_ANA_REG_TW_CTRL_REG_LOWV_REG::b1_AdcInpBufEn

bits 3: 3

◆ b1_AdcRefBufEn

uint32_t U_MSS_TOPRCM_ANA_REG_TW_CTRL_REG_LOWV_REG::b1_AdcRefBufEn

bits 4: 4

◆ b3_AdcRefSel_2_0

uint32_t U_MSS_TOPRCM_ANA_REG_TW_CTRL_REG_LOWV_REG::b3_AdcRefSel_2_0

bits 7: 5

◆ b1_TsDiffInpBufEn

uint32_t U_MSS_TOPRCM_ANA_REG_TW_CTRL_REG_LOWV_REG::b1_TsDiffInpBufEn

bits 8: 8

◆ b1_TsSeInpBufEn

uint32_t U_MSS_TOPRCM_ANA_REG_TW_CTRL_REG_LOWV_REG::b1_TsSeInpBufEn

bits 9: 9

◆ b1_IforceExtCtrl

uint32_t U_MSS_TOPRCM_ANA_REG_TW_CTRL_REG_LOWV_REG::b1_IforceExtCtrl

bits 10: 10

◆ b1_VrefExtCtrl

uint32_t U_MSS_TOPRCM_ANA_REG_TW_CTRL_REG_LOWV_REG::b1_VrefExtCtrl

bits 11: 11

◆ b1_VinExtCtrl

uint32_t U_MSS_TOPRCM_ANA_REG_TW_CTRL_REG_LOWV_REG::b1_VinExtCtrl

bits 12: 12

◆ b1_AnaTmuxBufBypass

uint32_t U_MSS_TOPRCM_ANA_REG_TW_CTRL_REG_LOWV_REG::b1_AnaTmuxBufBypass

bits 13: 13

◆ b1_AnaTmuxBufEn

uint32_t U_MSS_TOPRCM_ANA_REG_TW_CTRL_REG_LOWV_REG::b1_AnaTmuxBufEn

bits 14: 14

◆ b5_RtrimTw_4_0

uint32_t U_MSS_TOPRCM_ANA_REG_TW_CTRL_REG_LOWV_REG::b5_RtrimTw_4_0

bits 19: 15

◆ b12_Reserved1

uint32_t U_MSS_TOPRCM_ANA_REG_TW_CTRL_REG_LOWV_REG::b12_Reserved1

bits 31: 20