am263x/sdl_ecc_soc.h File Reference

Go to the source code of this file.

Macros
#define	SDL_ECC_WIDTH_UNDEFINED   0x1
#define	SDL_SOC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (7U)
#define	SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (28U)
#define	SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (28U)
#define	SDL_R5FSS1_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (28U)
#define	SDL_R5FSS1_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (28U)
#define	SDL_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (10U)
#define	SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (5U)
#define	SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (8U)
#define	SDL_ECC_Base_Address_TOTAL_ENTRIES   (11U)

Variables
static const SDL_MemConfig_t	SDL_SOC_ECC_AGGR_MemEntries [SDL_SOC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries [SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries [SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_R5FSS1_CORE0_ECC_AGGR_MemEntries [SDL_R5FSS1_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_R5FSS1_CORE1_ECC_AGGR_MemEntries [SDL_R5FSS1_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_HSM_ECC_AGGR_MemEntries [SDL_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries [SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries [SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries [SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries [SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries [SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_CPSW3GCSS_ECC_AGGR_MemEntries [SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_RAMIdEntry_t	SDL_SOC_ECC_AGGR_RamIdTable [SDL_SOC_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable [SDL_R5FSS0_CORE0_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable [SDL_R5FSS0_CORE1_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_R5FSS1_CORE0_ECC_AGGR_RamIdTable [SDL_R5FSS1_CORE0_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_R5FSS1_CORE1_ECC_AGGR_RamIdTable [SDL_R5FSS1_CORE1_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_HSM_ECC_AGGR_RamIdTable [SDL_HSM_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable [SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable [SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable [SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable [SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable [SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_CPSW3GCSS_ECC_AGGR_RamIdTable [SDL_CPSW3GCSS_ECC_AGGR_NUM_RAMS]
static SDL_ecc_aggrRegs *const	SDL_ECC_aggrBaseAddressTable [SDL_ECC_Base_Address_TOTAL_ENTRIES]
SDL_ecc_aggrRegs *	SDL_ECC_aggrTransBaseAddressTable [SDL_ECC_MEMTYPE_MAX]
static const SDL_EccAggrEntry_t	SDL_ECC_aggrTable [SDL_ECC_MEMTYPE_MAX]

Macro Definition Documentation

SDL_ECC_WIDTH_UNDEFINED

#define SDL_ECC_WIDTH_UNDEFINED   0x1

SDL_SOC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_SOC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (7U)

SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (28U)

SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (28U)

SDL_R5FSS1_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_R5FSS1_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (28U)

SDL_R5FSS1_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_R5FSS1_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (28U)

SDL_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (10U)

SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (5U)

SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (8U)

SDL_ECC_Base_Address_TOTAL_ENTRIES

#define SDL_ECC_Base_Address_TOTAL_ENTRIES   (11U)

Variable Documentation

SDL_SOC_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_SOC_ECC_AGGR_MemEntries[SDL_SOC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_SOC_ECC_AGGR_MSS_L2_SLV0_ECC_RAM_ID, 0x70000000u,
      SDL_SOC_ECC_AGGR_MSS_L2_SLV0_ECC_RAM_SIZE, 4u,
      SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
    { SDL_SOC_ECC_AGGR_MSS_L2_SLV1_ECC_RAM_ID, 0x70080000u,
      SDL_SOC_ECC_AGGR_MSS_L2_SLV1_ECC_RAM_SIZE, 4u,
      SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
    { SDL_SOC_ECC_AGGR_MSS_L2_SLV2_ECC_RAM_ID, 0x70100000u,
      SDL_SOC_ECC_AGGR_MSS_L2_SLV2_ECC_RAM_SIZE, 4u,
      SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
    { SDL_SOC_ECC_AGGR_MSS_L2_SLV3_ECC_RAM_ID, 0x70180000u,
      SDL_SOC_ECC_AGGR_MSS_L2_SLV3_ECC_RAM_SIZE, 4u,
      SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
    { SDL_SOC_ECC_AGGR_MAILBOX_ECC_RAM_ID, 0x72000000u,
      SDL_SOC_ECC_AGGR_MAILBOX_ECC_RAM_SIZE, 4u,
      SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
    { SDL_SOC_ECC_AGGR_TPTC_A0_ECC_RAM_ID, 0x52A40000u,
      SDL_SOC_ECC_AGGR_TPTC_A0_ECC_RAM_SIZE, 4u,
      SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
    { SDL_SOC_ECC_AGGR_TPTC_A1_ECC_RAM_ID, 0x52A60000u,
      SDL_SOC_ECC_AGGR_TPTC_A1_ECC_RAM_SIZE, 4u,
      SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_SOC_ECC_AGGR

SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_R5FSS0_CORE0_ECC_AGGR

SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_R5FSS0_CORE1_ECC_AGGR

SDL_R5FSS1_CORE0_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_R5FSS1_CORE0_ECC_AGGR_MemEntries[SDL_R5FSS1_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_R5FSS1_CORE0_ECC_AGGR

SDL_R5FSS1_CORE1_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_R5FSS1_CORE1_ECC_AGGR_MemEntries[SDL_R5FSS1_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_R5FSS1_CORE1_ECC_AGGR

SDL_HSM_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_HSM_ECC_AGGR_MemEntries[SDL_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_HSM_ECC_AGGR

SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries[SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_ID, 0x48100000u,
      SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_ID, 0x48100004u,
      SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_ID, 0x48100008u,
      SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_ID, 0x4810000cu,
      SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_ID, 0x48100010u,
      SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR

SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x52600000u,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x52610000u,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x52620000u,
      SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x52630000u,
      SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_CPSW3GCSS_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_CPSW3GCSS_ECC_AGGR_MemEntries[SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_RAM_ID, 0u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_RAM_SIZE, 4u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_RAM_ID, 0u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_RAM_SIZE, 4u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_RAM_ID, 0u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_RAM_SIZE, 4u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_RAM_ID, 0u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_RAM_SIZE, 4u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_RAM_ID, 0u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_RAM_SIZE, 4u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_RAM_ID, 0u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_RAM_SIZE, 4u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_RAM_ID, 0u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_RAM_SIZE, 4u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_EST_RAM_ECC_RAM_ID, 0u,
      SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_EST_RAM_ECC_RAM_SIZE, 4u,
      SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_CPSW3GCSS_ECC_AGGR

SDL_SOC_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_SOC_ECC_AGGR_RamIdTable[SDL_SOC_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_SOC_ECC_AGGR

SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE0_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_R5FSS0_CORE0_ECC_AGGR

SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE1_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_R5FSS0_CORE1_ECC_AGGR

SDL_R5FSS1_CORE0_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_R5FSS1_CORE0_ECC_AGGR_RamIdTable[SDL_R5FSS1_CORE0_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_R5FSS1_CORE0_ECC_AGGR

SDL_R5FSS1_CORE1_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_R5FSS1_CORE1_ECC_AGGR_RamIdTable[SDL_R5FSS1_CORE1_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_R5FSS1_CORE1_ECC_AGGR

SDL_HSM_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_HSM_ECC_AGGR_RamIdTable[SDL_HSM_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_HSM_ECC_AGGR

SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable[SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_ID,
      SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_INJECT_TYPE,
      SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_ID,
      SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_INJECT_TYPE,
      SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_ID,
      SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_INJECT_TYPE,
      SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_ID,
      SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_INJECT_TYPE,
      SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_ID,
      SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_INJECT_TYPE,
      SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR

SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL }
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL }
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL }
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL }
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_CPSW3GCSS_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_CPSW3GCSS_ECC_AGGR_RamIdTable[SDL_CPSW3GCSS_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_CPSW3GCSS_ECC_AGGR

SDL_ECC_aggrBaseAddressTable

SDL_ecc_aggrRegs* const SDL_ECC_aggrBaseAddressTable[SDL_ECC_Base_Address_TOTAL_ENTRIES]

static

Initial value:

=
{
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ECC_AGG_TOP_U_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ECC_AGG_R5SS0_CORE0_U_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ECC_AGG_R5SS1_CORE0_U_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ECC_AGG_R5SS0_CORE1_U_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ECC_AGG_R5SS1_CORE1_U_BASE )),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_HSM_ECC_AGGR_U_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ICSSM0_ECC_U_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN0_ECC_U_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN1_ECC_U_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN2_ECC_U_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN3_ECC_U_BASE)),
 
}

SDL_ECC_aggrTransBaseAddressTable

SDL_ecc_aggrRegs* SDL_ECC_aggrTransBaseAddressTable[SDL_ECC_MEMTYPE_MAX]

SDL_ECC_aggrTable

const SDL_EccAggrEntry_t SDL_ECC_aggrTable[SDL_ECC_MEMTYPE_MAX]

static