AM273x MCU+ SDK  08.05.00
am263x/sdl_ecc_soc.h
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1 /*
2  * SDL ECC
3  *
4  * Software Diagnostics Library module for ECC
5  *
6  * Copyright (c) Texas Instruments Incorporated 2022
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  *
12  * Redistributions of source code must retain the above copyright
13  * notice, this list of conditions and the following disclaimer.
14  *
15  * Redistributions in binary form must reproduce the above copyright
16  * notice, this list of conditions and the following disclaimer in the
17  * documentation and/or other materials provided with the
18  * distribution.
19  *
20  * Neither the name of Texas Instruments Incorporated nor the names of
21  * its contributors may be used to endorse or promote products derived
22  * from this software without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35  *
36  */
37 
38  #ifndef INCLUDE_SDL_ECC_SOC_H_
39  #define INCLUDE_SDL_ECC_SOC_H_
40 
41  #include <stdint.h>
42  #include <sdl/sdl_ecc.h>
43  #include <sdl/ecc/sdl_ip_ecc.h>
44  #include <sdl/include/sdl_types.h>
45  #include <sdl/esm/soc/am263x/sdl_esm_core.h>
46  #include <sdl/ecc/sdl_ecc_priv.h>
47  #include <sdl/include/am263x/sdlr_soc_ecc_aggr.h>
48  #include <sdl/include/am263x/soc_config.h>
49  #include <sdl/include/am263x/sdlr_intr_esm0.h>
50  #include <sdl/include/am263x/sdlr_soc_baseaddress.h>
51  #include <sdl/include/am263x/sdlr_intr_r5fss0_core0.h>
52  #include <sdl/include/am263x/sdlr_intr_r5fss0_core1.h>
53  #include <sdl/include/am263x/sdlr_intr_r5fss1_core0.h>
54  #include <sdl/include/am263x/sdlr_intr_r5fss1_core1.h>
55 
56 #define SDL_ECC_WIDTH_UNDEFINED 0x1
57 
58 /* define Max memEntries for each aggregator (i.e. the number of RAM ID's with * Wrapper type) */
59 #define SDL_SOC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (7U)
60 #define SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (28U)
61 #define SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (28U)
62 #define SDL_R5FSS1_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (28U)
63 #define SDL_R5FSS1_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (28U)
64 #define SDL_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (10U)
65 #define SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (5U)
66 #define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
67 #define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
68 #define SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
69 #define SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
70 #define SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (8U)
71 #define SDL_ECC_Base_Address_TOTAL_ENTRIES (11U)
72 
77 static const SDL_MemConfig_t SDL_SOC_ECC_AGGR_MemEntries[SDL_SOC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
78 {
79  { SDL_SOC_ECC_AGGR_MSS_L2_SLV0_ECC_RAM_ID, 0x70000000u,
80  SDL_SOC_ECC_AGGR_MSS_L2_SLV0_ECC_RAM_SIZE, 4u,
81  SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
82  { SDL_SOC_ECC_AGGR_MSS_L2_SLV1_ECC_RAM_ID, 0x70080000u,
83  SDL_SOC_ECC_AGGR_MSS_L2_SLV1_ECC_RAM_SIZE, 4u,
84  SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
85  { SDL_SOC_ECC_AGGR_MSS_L2_SLV2_ECC_RAM_ID, 0x70100000u,
86  SDL_SOC_ECC_AGGR_MSS_L2_SLV2_ECC_RAM_SIZE, 4u,
87  SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
88  { SDL_SOC_ECC_AGGR_MSS_L2_SLV3_ECC_RAM_ID, 0x70180000u,
89  SDL_SOC_ECC_AGGR_MSS_L2_SLV3_ECC_RAM_SIZE, 4u,
90  SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
91  { SDL_SOC_ECC_AGGR_MAILBOX_ECC_RAM_ID, 0x72000000u,
92  SDL_SOC_ECC_AGGR_MAILBOX_ECC_RAM_SIZE, 4u,
93  SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
94  { SDL_SOC_ECC_AGGR_TPTC_A0_ECC_RAM_ID, 0x52A40000u,
95  SDL_SOC_ECC_AGGR_TPTC_A0_ECC_RAM_SIZE, 4u,
96  SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
97  { SDL_SOC_ECC_AGGR_TPTC_A1_ECC_RAM_ID, 0x52A60000u,
98  SDL_SOC_ECC_AGGR_TPTC_A1_ECC_RAM_SIZE, 4u,
99  SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
100 };
101 
106 static const SDL_MemConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
107 {
108  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID, 0u,
109  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_SIZE, 4u,
110  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
111  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID, 0u,
112  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_SIZE, 4u,
113  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
114  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID, 0u,
115  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_SIZE, 4u,
116  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
117  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID, 0u,
118  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_SIZE, 4u,
119  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
120  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID, 0u,
121  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_SIZE, 4u,
122  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_ROW_WIDTH, ((bool)false) },
123  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID, 0u,
124  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_SIZE, 4u,
125  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_ROW_WIDTH, ((bool)false) },
126  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID, 0u,
127  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_SIZE, 4u,
128  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_ROW_WIDTH, ((bool)false) },
129  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID, 0u,
130  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_SIZE, 4u,
131  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_ROW_WIDTH, ((bool)false) },
132  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID, 0u,
133  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_SIZE, 4u,
134  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
135  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID, 0u,
136  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_SIZE, 4u,
137  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
138  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID, 0u,
139  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_SIZE, 4u,
140  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
141  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID, 0u,
142  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_SIZE, 4u,
143  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
144  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID, 0u,
145  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_SIZE, 4u,
146  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
147  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID, 0u,
148  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_SIZE, 4u,
149  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_ROW_WIDTH, ((bool)false) },
150  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID, 0u,
151  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_SIZE, 4u,
152  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_ROW_WIDTH, ((bool)false) },
153  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID, 0u,
154  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_SIZE, 4u,
155  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_ROW_WIDTH, ((bool)false) },
156  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID, 0u,
157  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_SIZE, 4u,
158  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_ROW_WIDTH, ((bool)false) },
159  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID, 0u,
160  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_SIZE, 4u,
161  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_ROW_WIDTH, ((bool)false) },
162  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID, 0u,
163  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_SIZE, 4u,
164  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_ROW_WIDTH, ((bool)false) },
165  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID, 0u,
166  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_SIZE, 4u,
167  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_ROW_WIDTH, ((bool)false) },
168  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID, 0u,
169  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_SIZE, 4u,
170  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_ROW_WIDTH, ((bool)false) },
171  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID, 0x0u,
172  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_SIZE, 4u,
173  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ROW_WIDTH, ((bool)true) },
174  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID, 0x00004000u,
175  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_SIZE, 4u,
176  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ROW_WIDTH, ((bool)true) },
177  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID, 0x00080000u,
178  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_SIZE, 4u,
179  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ROW_WIDTH, ((bool)true) },
180  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID, 0x00082000u,
181  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_SIZE, 4u,
182  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ROW_WIDTH, ((bool)true) },
183  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID, 0x00084000u,
184  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_SIZE, 4u,
185  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ROW_WIDTH, ((bool)true) },
186  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID, 0x00086000u,
187  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_SIZE, 4u,
188  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ROW_WIDTH, ((bool)true) },
189  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID, 0x5300006Cu,
190  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_SIZE, 4u,
191  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ROW_WIDTH, ((bool)true) },
192 };
193 
198 static const SDL_MemConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
199 {
200  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_ID, 0u,
201  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_SIZE, 4u,
202  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
203  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_ID, 0u,
204  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_SIZE, 4u,
205  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
206  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_ID, 0u,
207  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_SIZE, 4u,
208  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
209  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_ID, 0u,
210  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_SIZE, 4u,
211  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
212  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_ID, 0u,
213  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_SIZE, 4u,
214  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_ROW_WIDTH, ((bool)false) },
215  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_ID, 0u,
216  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_SIZE, 4u,
217  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_ROW_WIDTH, ((bool)false) },
218  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_ID, 0u,
219  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_SIZE, 4u,
220  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_ROW_WIDTH, ((bool)false) },
221  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_ID, 0u,
222  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_SIZE, 4u,
223  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_ROW_WIDTH, ((bool)false) },
224  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_ID, 0u,
225  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_SIZE, 4u,
226  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
227  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_ID, 0u,
228  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_SIZE, 4u,
229  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
230  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_ID, 0u,
231  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_SIZE, 4u,
232  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
233  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_ID, 0u,
234  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_SIZE, 4u,
235  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
236  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_ID, 0u,
237  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_SIZE, 4u,
238  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
239  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_ID, 0u,
240  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_SIZE, 4u,
241  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_ROW_WIDTH, ((bool)false) },
242  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_ID, 0u,
243  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_SIZE, 4u,
244  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_ROW_WIDTH, ((bool)false) },
245  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_ID, 0u,
246  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_SIZE, 4u,
247  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_ROW_WIDTH, ((bool)false) },
248  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_ID, 0u,
249  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_SIZE, 4u,
250  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_ROW_WIDTH, ((bool)false) },
251  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_ID, 0u,
252  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_SIZE, 4u,
253  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_ROW_WIDTH, ((bool)false) },
254  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_ID, 0u,
255  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_SIZE, 4u,
256  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_ROW_WIDTH, ((bool)false) },
257  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_ID, 0u,
258  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_SIZE, 4u,
259  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_ROW_WIDTH, ((bool)false) },
260  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_ID, 0u,
261  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_SIZE, 4u,
262  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_ROW_WIDTH, ((bool)false) },
263  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_ID, 0x53003054u,
264  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_SIZE, 8u,
265  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_ROW_WIDTH, ((bool)true) },
266  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_ID, 0x53003058u,
267  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_SIZE, 4u,
268  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_ROW_WIDTH, ((bool)true) },
269  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_ID, 0x5300305Cu,
270  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_SIZE, 4u,
271  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_ROW_WIDTH, ((bool)true) },
272  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_ID, 0x53003060u,
273  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_SIZE, 4u,
274  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_ROW_WIDTH, ((bool)true) },
275  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_ID, 0x53003064u,
276  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_SIZE, 4u,
277  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_ROW_WIDTH, ((bool)true) },
278  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_ID, 0x53003068u,
279  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_SIZE, 4u,
280  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_ROW_WIDTH, ((bool)true) },
281  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_ID, 0x5300306cu,
282  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_SIZE, 4u,
283  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_ROW_WIDTH, ((bool)true) },
284 };
285 
290 static const SDL_MemConfig_t SDL_R5FSS1_CORE0_ECC_AGGR_MemEntries[SDL_R5FSS1_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
291 {
292  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID, 0u,
293  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_SIZE, 4u,
294  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
295  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID, 0u,
296  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_SIZE, 4u,
297  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
298  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID, 0u,
299  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_SIZE, 4u,
300  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
301  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID, 0u,
302  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_SIZE, 4u,
303  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
304  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID, 0u,
305  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_SIZE, 4u,
306  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_ROW_WIDTH, ((bool)false) },
307  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID, 0u,
308  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_SIZE, 4u,
309  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_ROW_WIDTH, ((bool)false) },
310  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID, 0u,
311  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_SIZE, 4u,
312  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_ROW_WIDTH, ((bool)false) },
313  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID, 0u,
314  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_SIZE, 4u,
315  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_ROW_WIDTH, ((bool)false) },
316  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID, 0u,
317  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_SIZE, 4u,
318  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
319  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID, 0u,
320  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_SIZE, 4u,
321  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
322  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID, 0u,
323  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_SIZE, 4u,
324  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
325  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID, 0u,
326  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_SIZE, 4u,
327  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
328  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID, 0u,
329  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_SIZE, 4u,
330  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
331  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID, 0u,
332  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_SIZE, 4u,
333  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_ROW_WIDTH, ((bool)false) },
334  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID, 0u,
335  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_SIZE, 4u,
336  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_ROW_WIDTH, ((bool)false) },
337  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID, 0u,
338  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_SIZE, 4u,
339  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_ROW_WIDTH, ((bool)false) },
340  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID, 0u,
341  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_SIZE, 4u,
342  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_ROW_WIDTH, ((bool)false) },
343  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID, 0u,
344  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_SIZE, 4u,
345  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_ROW_WIDTH, ((bool)false) },
346  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID, 0u,
347  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_SIZE, 4u,
348  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_ROW_WIDTH, ((bool)false) },
349  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID, 0u,
350  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_SIZE, 4u,
351  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_ROW_WIDTH, ((bool)false) },
352  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID, 0u,
353  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_SIZE, 4u,
354  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_ROW_WIDTH, ((bool)false) },
355  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID, 0x53004054u,
356  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_SIZE, 4u,
357  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ROW_WIDTH, ((bool)true) },
358  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID, 0x53004058u,
359  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_SIZE, 4u,
360  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ROW_WIDTH, ((bool)true) },
361  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID, 0x5300405cu,
362  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_SIZE, 4u,
363  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ROW_WIDTH, ((bool)true) },
364  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID, 0x53004060u,
365  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_SIZE, 4u,
366  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ROW_WIDTH, ((bool)true) },
367  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID, 0x53004064u,
368  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_SIZE, 4u,
369  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ROW_WIDTH, ((bool)true) },
370  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID, 0x53004068u,
371  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_SIZE, 4u,
372  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ROW_WIDTH, ((bool)true) },
373  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID, 0x5300406cu,
374  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_SIZE, 4u,
375  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ROW_WIDTH, ((bool)true) },
376 };
377 
382 static const SDL_MemConfig_t SDL_R5FSS1_CORE1_ECC_AGGR_MemEntries[SDL_R5FSS1_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
383 {
384  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_ID, 0u,
385  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_SIZE, 4u,
386  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
387  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_ID, 0u,
388  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_SIZE, 4u,
389  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
390  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_ID, 0u,
391  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_SIZE, 4u,
392  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
393  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_ID, 0u,
394  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_SIZE, 4u,
395  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
396  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_ID, 0u,
397  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_SIZE, 4u,
398  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_ROW_WIDTH, ((bool)false) },
399  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_ID, 0u,
400  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_SIZE, 4u,
401  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_ROW_WIDTH, ((bool)false) },
402  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_ID, 0u,
403  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_SIZE, 4u,
404  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_ROW_WIDTH, ((bool)false) },
405  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_ID, 0u,
406  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_SIZE, 4u,
407  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_ROW_WIDTH, ((bool)false) },
408  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_ID, 0u,
409  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_SIZE, 4u,
410  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
411  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_ID, 0u,
412  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_SIZE, 4u,
413  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
414  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_ID, 0u,
415  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_SIZE, 4u,
416  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
417  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_ID, 0u,
418  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_SIZE, 4u,
419  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
420  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_ID, 0u,
421  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_SIZE, 4u,
422  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
423  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_ID, 0u,
424  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_SIZE, 4u,
425  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_ROW_WIDTH, ((bool)false) },
426  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_ID, 0u,
427  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_SIZE, 4u,
428  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_ROW_WIDTH, ((bool)false) },
429  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_ID, 0u,
430  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_SIZE, 4u,
431  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_ROW_WIDTH, ((bool)false) },
432  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_ID, 0u,
433  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_SIZE, 4u,
434  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_ROW_WIDTH, ((bool)false) },
435  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_ID, 0u,
436  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_SIZE, 4u,
437  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_ROW_WIDTH, ((bool)false) },
438  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_ID, 0u,
439  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_SIZE, 4u,
440  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_ROW_WIDTH, ((bool)false) },
441  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_ID, 0u,
442  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_SIZE, 4u,
443  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_ROW_WIDTH, ((bool)false) },
444  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_ID, 0u,
445  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_SIZE, 4u,
446  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_ROW_WIDTH, ((bool)false) },
447  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_ID, 0x53007054u,
448  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_SIZE, 4u,
449  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_ROW_WIDTH, ((bool)true) },
450  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_ID, 0x53007058u,
451  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_SIZE, 4u,
452  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_ROW_WIDTH, ((bool)true) },
453  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_ID, 0x5300705cu,
454  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_SIZE, 4u,
455  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_ROW_WIDTH, ((bool)true) },
456  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_ID, 0x53007060u,
457  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_SIZE, 4u,
458  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_ROW_WIDTH, ((bool)true) },
459  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_ID, 0x53007064u,
460  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_SIZE, 4u,
461  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_ROW_WIDTH, ((bool)true) },
462  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_ID, 0x53007068u,
463  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_SIZE, 4u,
464  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_ROW_WIDTH, ((bool)true) },
465  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_ID, 0x5300706cu,
466  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_SIZE, 4u,
467  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_ROW_WIDTH, ((bool)true) },
468 };
469 
474 static const SDL_MemConfig_t SDL_HSM_ECC_AGGR_MemEntries[SDL_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
475 {
476  { SDL_HSM_ECC_AGGR_RAMB0_RAM_ID, 0u,
477  SDL_HSM_ECC_AGGR_RAMB0_RAM_SIZE, 4u,
478  SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
479  { SDL_HSM_ECC_AGGR_RAMB1_RAM_ID, 0u,
480  SDL_HSM_ECC_AGGR_RAMB1_RAM_SIZE, 4u,
481  SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
482  { SDL_HSM_ECC_AGGR_RAMB2_RAM_ID, 0u,
483  SDL_HSM_ECC_AGGR_RAMB2_RAM_SIZE, 4u,
484  SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
485  { SDL_HSM_ECC_AGGR_RAMB3_RAM_ID, 0u,
486  SDL_HSM_ECC_AGGR_RAMB3_RAM_SIZE, 4u,
487  SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
488  { SDL_HSM_ECC_AGGR_SECUREB4_RAM_ID, 0u,
489  SDL_HSM_ECC_AGGR_SECUREB4_RAM_SIZE, 4u,
490  SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
491  { SDL_HSM_ECC_AGGR_MBOX_RAM_ID, 0u,
492  SDL_HSM_ECC_AGGR_MBOX_RAM_SIZE, 4u,
493  SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
494  { SDL_HSM_ECC_AGGR_SECURE_RAM_ID, 0u,
495  SDL_HSM_ECC_AGGR_SECURE_RAM_SIZE, 4u,
496  SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
497  { SDL_HSM_ECC_AGGR_ROM_RAM_ID, 0u,
498  SDL_HSM_ECC_AGGR_ROM_RAM_SIZE, 4u,
499  SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
500  { SDL_HSM_ECC_AGGR_TPTC_A0_RAM_ID, 0u,
501  SDL_HSM_ECC_AGGR_TPTC_A0_RAM_SIZE, 4u,
502  SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
503  { SDL_HSM_ECC_AGGR_TPTC_A1_RAM_ID, 0u,
504  SDL_HSM_ECC_AGGR_TPTC_A1_RAM_SIZE, 4u,
505  SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
506 };
507 
512 static const SDL_MemConfig_t SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries[SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
513 {
514  { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_ID, 0x48100000u,
515  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_SIZE, 4u,
516  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_ROW_WIDTH, ((bool)true) },
517  { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_ID, 0x48100004u,
518  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_SIZE, 4u,
519  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_ROW_WIDTH, ((bool)true) },
520  { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_ID, 0x48100008u,
521  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_SIZE, 4u,
522  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_ROW_WIDTH, ((bool)true) },
523  { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_ID, 0x4810000cu,
524  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_SIZE, 4u,
525  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_ROW_WIDTH, ((bool)true) },
526  { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_ID, 0x48100010u,
527  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_SIZE, 4u,
528  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_ROW_WIDTH, ((bool)true) },
529 };
530 
535 static const SDL_MemConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
536 {
537  { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x52600000u,
538  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
539  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
540 };
541 
546 static const SDL_MemConfig_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
547 {
548  { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x52610000u,
549  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
550  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
551 };
552 
557 static const SDL_MemConfig_t SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
558 {
559  { SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x52620000u,
560  SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
561  SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
562 };
563 
568 static const SDL_MemConfig_t SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
569 {
570  { SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x52630000u,
571  SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
572  SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
573 };
574 
579 static const SDL_MemConfig_t SDL_CPSW3GCSS_ECC_AGGR_MemEntries[SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
580 {
581  { SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_RAM_ID, 0u,
582  SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_RAM_SIZE, 4u,
583  SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_ROW_WIDTH, ((bool)true) },
584  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_RAM_ID, 0u,
585  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_RAM_SIZE, 4u,
586  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_ROW_WIDTH, ((bool)false) },
587  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_RAM_ID, 0u,
588  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_RAM_SIZE, 4u,
589  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_ROW_WIDTH, ((bool)false) },
590  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_RAM_ID, 0u,
591  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_RAM_SIZE, 4u,
592  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_ROW_WIDTH, ((bool)false) },
593  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_RAM_ID, 0u,
594  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_RAM_SIZE, 4u,
595  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_ROW_WIDTH, ((bool)false) },
596  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_RAM_ID, 0u,
597  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_RAM_SIZE, 4u,
598  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_ROW_WIDTH, ((bool)false) },
599  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_RAM_ID, 0u,
600  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_RAM_SIZE, 4u,
601  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_ROW_WIDTH, ((bool)false) },
602  { SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_EST_RAM_ECC_RAM_ID, 0u,
603  SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_EST_RAM_ECC_RAM_SIZE, 4u,
604  SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
605 };
610 static const SDL_RAMIdEntry_t SDL_SOC_ECC_AGGR_RamIdTable[SDL_SOC_ECC_AGGR_NUM_RAMS] =
611 {
612  { SDL_SOC_ECC_AGGR_MSS_L2_SLV0_ECC_RAM_ID,
613  SDL_SOC_ECC_AGGR_MSS_L2_SLV0_ECC_INJECT_TYPE,
614  SDL_SOC_ECC_AGGR_MSS_L2_SLV0_ECC_ECC_TYPE,
615  0u,
616  NULL },
617  { SDL_SOC_ECC_AGGR_MSS_L2_SLV1_ECC_RAM_ID,
618  SDL_SOC_ECC_AGGR_MSS_L2_SLV1_ECC_INJECT_TYPE,
619  SDL_SOC_ECC_AGGR_MSS_L2_SLV1_ECC_ECC_TYPE,
620  0u,
621  NULL },
622  { SDL_SOC_ECC_AGGR_MSS_L2_SLV2_ECC_RAM_ID,
623  SDL_SOC_ECC_AGGR_MSS_L2_SLV2_ECC_INJECT_TYPE,
624  SDL_SOC_ECC_AGGR_MSS_L2_SLV2_ECC_ECC_TYPE,
625  0u,
626  NULL },
627  { SDL_SOC_ECC_AGGR_MSS_L2_SLV3_ECC_RAM_ID,
628  SDL_SOC_ECC_AGGR_MSS_L2_SLV3_ECC_INJECT_TYPE,
629  SDL_SOC_ECC_AGGR_MSS_L2_SLV3_ECC_ECC_TYPE,
630  0u,
631  NULL },
632  { SDL_SOC_ECC_AGGR_MAILBOX_ECC_RAM_ID,
633  SDL_SOC_ECC_AGGR_MAILBOX_ECC_INJECT_TYPE,
634  SDL_SOC_ECC_AGGR_MAILBOX_ECC_ECC_TYPE,
635  0u,
636  NULL },
637  { SDL_SOC_ECC_AGGR_TPTC_A0_ECC_RAM_ID,
638  SDL_SOC_ECC_AGGR_TPTC_A0_ECC_INJECT_TYPE,
639  SDL_SOC_ECC_AGGR_TPTC_A0_ECC_ECC_TYPE,
640  0u,
641  NULL },
642  { SDL_SOC_ECC_AGGR_TPTC_A1_ECC_RAM_ID,
643  SDL_SOC_ECC_AGGR_TPTC_A1_ECC_INJECT_TYPE,
644  SDL_SOC_ECC_AGGR_TPTC_A1_ECC_ECC_TYPE,
645  0u,
646  NULL },
647 };
648 
653 static const SDL_RAMIdEntry_t SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE0_ECC_AGGR_NUM_RAMS] =
654 {
655  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID,
656  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_INJECT_TYPE,
657  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_ECC_TYPE,
658  0u,
659  NULL },
660  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID,
661  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_INJECT_TYPE,
662  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_ECC_TYPE,
663  0u,
664  NULL },
665  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID,
666  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_INJECT_TYPE,
667  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_ECC_TYPE,
668  0u,
669  NULL },
670  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID,
671  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_INJECT_TYPE,
672  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_ECC_TYPE,
673  0u,
674  NULL },
675  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID,
676  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_INJECT_TYPE,
677  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_ECC_TYPE,
678  0u,
679  NULL },
680  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID,
681  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_INJECT_TYPE,
682  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_ECC_TYPE,
683  0u,
684  NULL },
685  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID,
686  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_INJECT_TYPE,
687  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_ECC_TYPE,
688  0u,
689  NULL },
690  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID,
691  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_INJECT_TYPE,
692  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_ECC_TYPE,
693  0u,
694  NULL },
695  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID,
696  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_INJECT_TYPE,
697  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_ECC_TYPE,
698  0u,
699  NULL },
700  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID,
701  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_INJECT_TYPE,
702  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_ECC_TYPE,
703  0u,
704  NULL },
705  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID,
706  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_INJECT_TYPE,
707  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_ECC_TYPE,
708  0u,
709  NULL },
710  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID,
711  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_INJECT_TYPE,
712  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_ECC_TYPE,
713  0u,
714  NULL },
715  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID,
716  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_INJECT_TYPE,
717  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_ECC_TYPE,
718  0u,
719  NULL },
720  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID,
721  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_INJECT_TYPE,
722  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_ECC_TYPE,
723  0u,
724  NULL },
725  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID,
726  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_INJECT_TYPE,
727  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_ECC_TYPE,
728  0u,
729  NULL },
730  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID,
731  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_INJECT_TYPE,
732  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_ECC_TYPE,
733  0u,
734  NULL },
735  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID,
736  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_INJECT_TYPE,
737  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_ECC_TYPE,
738  0u,
739  NULL },
740  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID,
741  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_INJECT_TYPE,
742  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_ECC_TYPE,
743  0u,
744  NULL },
745  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID,
746  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_INJECT_TYPE,
747  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_ECC_TYPE,
748  0u,
749  NULL },
750  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID,
751  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_INJECT_TYPE,
752  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_ECC_TYPE,
753  0u,
754  NULL },
755  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID,
756  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_INJECT_TYPE,
757  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_ECC_TYPE,
758  0u,
759  NULL },
760  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID,
761  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_INJECT_TYPE,
762  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ECC_TYPE,
763  0u,
764  NULL },
765  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID,
766  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_INJECT_TYPE,
767  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ECC_TYPE,
768  0u,
769  NULL },
770  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID,
771  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_INJECT_TYPE,
772  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ECC_TYPE,
773  0u,
774  NULL },
775  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID,
776  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_INJECT_TYPE,
777  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ECC_TYPE,
778  0u,
779  NULL },
780  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID,
781  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_INJECT_TYPE,
782  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ECC_TYPE,
783  0u,
784  NULL },
785  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID,
786  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_INJECT_TYPE,
787  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ECC_TYPE,
788  0u,
789  NULL },
790  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID,
791  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_INJECT_TYPE,
792  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ECC_TYPE,
793  0u,
794  NULL },
795 };
796 
801 static const SDL_RAMIdEntry_t SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE1_ECC_AGGR_NUM_RAMS] =
802 {
803  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_ID,
804  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_INJECT_TYPE,
805  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_ECC_TYPE,
806  0u,
807  NULL },
808  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_ID,
809  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_INJECT_TYPE,
810  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_ECC_TYPE,
811  0u,
812  NULL },
813  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_ID,
814  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_INJECT_TYPE,
815  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_ECC_TYPE,
816  0u,
817  NULL },
818  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_ID,
819  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_INJECT_TYPE,
820  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_ECC_TYPE,
821  0u,
822  NULL },
823  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_ID,
824  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_INJECT_TYPE,
825  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_ECC_TYPE,
826  0u,
827  NULL },
828  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_ID,
829  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_INJECT_TYPE,
830  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_ECC_TYPE,
831  0u,
832  NULL },
833  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_ID,
834  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_INJECT_TYPE,
835  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_ECC_TYPE,
836  0u,
837  NULL },
838  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_ID,
839  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_INJECT_TYPE,
840  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_ECC_TYPE,
841  0u,
842  NULL },
843  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_ID,
844  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_INJECT_TYPE,
845  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_ECC_TYPE,
846  0u,
847  NULL },
848  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_ID,
849  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_INJECT_TYPE,
850  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_ECC_TYPE,
851  0u,
852  NULL },
853  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_ID,
854  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_INJECT_TYPE,
855  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_ECC_TYPE,
856  0u,
857  NULL },
858  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_ID,
859  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_INJECT_TYPE,
860  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_ECC_TYPE,
861  0u,
862  NULL },
863  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_ID,
864  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_INJECT_TYPE,
865  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_ECC_TYPE,
866  0u,
867  NULL },
868  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_ID,
869  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_INJECT_TYPE,
870  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_ECC_TYPE,
871  0u,
872  NULL },
873  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_ID,
874  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_INJECT_TYPE,
875  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_ECC_TYPE,
876  0u,
877  NULL },
878  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_ID,
879  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_INJECT_TYPE,
880  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_ECC_TYPE,
881  0u,
882  NULL },
883  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_ID,
884  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_INJECT_TYPE,
885  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_ECC_TYPE,
886  0u,
887  NULL },
888  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_ID,
889  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_INJECT_TYPE,
890  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_ECC_TYPE,
891  0u,
892  NULL },
893  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_ID,
894  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_INJECT_TYPE,
895  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_ECC_TYPE,
896  0u,
897  NULL },
898  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_ID,
899  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_INJECT_TYPE,
900  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_ECC_TYPE,
901  0u,
902  NULL },
903  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_ID,
904  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_INJECT_TYPE,
905  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_ECC_TYPE,
906  0u,
907  NULL },
908  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_ID,
909  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_INJECT_TYPE,
910  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_ECC_TYPE,
911  0u,
912  NULL },
913  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_ID,
914  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_INJECT_TYPE,
915  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_ECC_TYPE,
916  0u,
917  NULL },
918  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_ID,
919  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_INJECT_TYPE,
920  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_ECC_TYPE,
921  0u,
922  NULL },
923  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_ID,
924  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_INJECT_TYPE,
925  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_ECC_TYPE,
926  0u,
927  NULL },
928  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_ID,
929  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_INJECT_TYPE,
930  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_ECC_TYPE,
931  0u,
932  NULL },
933  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_ID,
934  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_INJECT_TYPE,
935  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_ECC_TYPE,
936  0u,
937  NULL },
938  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_ID,
939  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_INJECT_TYPE,
940  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_ECC_TYPE,
941  0u,
942  NULL },
943 };
948 static const SDL_RAMIdEntry_t SDL_R5FSS1_CORE0_ECC_AGGR_RamIdTable[SDL_R5FSS1_CORE0_ECC_AGGR_NUM_RAMS] =
949 {
950  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID,
951  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_INJECT_TYPE,
952  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_ECC_TYPE,
953  0u,
954  NULL },
955  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID,
956  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_INJECT_TYPE,
957  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_ECC_TYPE,
958  0u,
959  NULL },
960  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID,
961  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_INJECT_TYPE,
962  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_ECC_TYPE,
963  0u,
964  NULL },
965  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID,
966  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_INJECT_TYPE,
967  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_ECC_TYPE,
968  0u,
969  NULL },
970  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID,
971  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_INJECT_TYPE,
972  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_ECC_TYPE,
973  0u,
974  NULL },
975  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID,
976  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_INJECT_TYPE,
977  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_ECC_TYPE,
978  0u,
979  NULL },
980  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID,
981  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_INJECT_TYPE,
982  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_ECC_TYPE,
983  0u,
984  NULL },
985  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID,
986  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_INJECT_TYPE,
987  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_ECC_TYPE,
988  0u,
989  NULL },
990  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID,
991  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_INJECT_TYPE,
992  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_ECC_TYPE,
993  0u,
994  NULL },
995  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID,
996  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_INJECT_TYPE,
997  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_ECC_TYPE,
998  0u,
999  NULL },
1000  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID,
1001  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_INJECT_TYPE,
1002  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_ECC_TYPE,
1003  0u,
1004  NULL },
1005  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID,
1006  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_INJECT_TYPE,
1007  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_ECC_TYPE,
1008  0u,
1009  NULL },
1010  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID,
1011  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_INJECT_TYPE,
1012  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_ECC_TYPE,
1013  0u,
1014  NULL },
1015  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID,
1016  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_INJECT_TYPE,
1017  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_ECC_TYPE,
1018  0u,
1019  NULL },
1020  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID,
1021  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_INJECT_TYPE,
1022  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_ECC_TYPE,
1023  0u,
1024  NULL },
1025  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID,
1026  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_INJECT_TYPE,
1027  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_ECC_TYPE,
1028  0u,
1029  NULL },
1030  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID,
1031  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_INJECT_TYPE,
1032  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_ECC_TYPE,
1033  0u,
1034  NULL },
1035  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID,
1036  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_INJECT_TYPE,
1037  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_ECC_TYPE,
1038  0u,
1039  NULL },
1040  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID,
1041  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_INJECT_TYPE,
1042  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_ECC_TYPE,
1043  0u,
1044  NULL },
1045  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID,
1046  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_INJECT_TYPE,
1047  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_ECC_TYPE,
1048  0u,
1049  NULL },
1050  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID,
1051  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_INJECT_TYPE,
1052  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_ECC_TYPE,
1053  0u,
1054  NULL },
1055  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID,
1056  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_INJECT_TYPE,
1057  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ECC_TYPE,
1058  0u,
1059  NULL },
1060  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID,
1061  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_INJECT_TYPE,
1062  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ECC_TYPE,
1063  0u,
1064  NULL },
1065  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID,
1066  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_INJECT_TYPE,
1067  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ECC_TYPE,
1068  0u,
1069  NULL },
1070  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID,
1071  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_INJECT_TYPE,
1072  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ECC_TYPE,
1073  0u,
1074  NULL },
1075  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID,
1076  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_INJECT_TYPE,
1077  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ECC_TYPE,
1078  0u,
1079  NULL },
1080  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID,
1081  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_INJECT_TYPE,
1082  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ECC_TYPE,
1083  0u,
1084  NULL },
1085  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID,
1086  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_INJECT_TYPE,
1087  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ECC_TYPE,
1088  0u,
1089  NULL },
1090 };
1091 
1096 static const SDL_RAMIdEntry_t SDL_R5FSS1_CORE1_ECC_AGGR_RamIdTable[SDL_R5FSS1_CORE1_ECC_AGGR_NUM_RAMS] =
1097 {
1098  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_ID,
1099  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_INJECT_TYPE,
1100  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_ECC_TYPE,
1101  0u,
1102  NULL },
1103  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_ID,
1104  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_INJECT_TYPE,
1105  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_ECC_TYPE,
1106  0u,
1107  NULL },
1108  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_ID,
1109  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_INJECT_TYPE,
1110  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_ECC_TYPE,
1111  0u,
1112  NULL },
1113  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_ID,
1114  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_INJECT_TYPE,
1115  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_ECC_TYPE,
1116  0u,
1117  NULL },
1118  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_ID,
1119  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_INJECT_TYPE,
1120  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_ECC_TYPE,
1121  0u,
1122  NULL },
1123  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_ID,
1124  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_INJECT_TYPE,
1125  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_ECC_TYPE,
1126  0u,
1127  NULL },
1128  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_ID,
1129  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_INJECT_TYPE,
1130  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_ECC_TYPE,
1131  0u,
1132  NULL },
1133  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_ID,
1134  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_INJECT_TYPE,
1135  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_ECC_TYPE,
1136  0u,
1137  NULL },
1138  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_ID,
1139  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_INJECT_TYPE,
1140  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_ECC_TYPE,
1141  0u,
1142  NULL },
1143  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_ID,
1144  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_INJECT_TYPE,
1145  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_ECC_TYPE,
1146  0u,
1147  NULL },
1148  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_ID,
1149  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_INJECT_TYPE,
1150  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_ECC_TYPE,
1151  0u,
1152  NULL },
1153  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_ID,
1154  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_INJECT_TYPE,
1155  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_ECC_TYPE,
1156  0u,
1157  NULL },
1158  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_ID,
1159  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_INJECT_TYPE,
1160  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_ECC_TYPE,
1161  0u,
1162  NULL },
1163  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_ID,
1164  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_INJECT_TYPE,
1165  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_ECC_TYPE,
1166  0u,
1167  NULL },
1168  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_ID,
1169  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_INJECT_TYPE,
1170  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_ECC_TYPE,
1171  0u,
1172  NULL },
1173  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_ID,
1174  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_INJECT_TYPE,
1175  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_ECC_TYPE,
1176  0u,
1177  NULL },
1178  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_ID,
1179  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_INJECT_TYPE,
1180  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_ECC_TYPE,
1181  0u,
1182  NULL },
1183  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_ID,
1184  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_INJECT_TYPE,
1185  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_ECC_TYPE,
1186  0u,
1187  NULL },
1188  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_ID,
1189  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_INJECT_TYPE,
1190  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_ECC_TYPE,
1191  0u,
1192  NULL },
1193  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_ID,
1194  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_INJECT_TYPE,
1195  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_ECC_TYPE,
1196  0u,
1197  NULL },
1198  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_ID,
1199  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_INJECT_TYPE,
1200  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_ECC_TYPE,
1201  0u,
1202  NULL },
1203  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_ID,
1204  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_INJECT_TYPE,
1205  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_ECC_TYPE,
1206  0u,
1207  NULL },
1208  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_ID,
1209  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_INJECT_TYPE,
1210  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_ECC_TYPE,
1211  0u,
1212  NULL },
1213  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_ID,
1214  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_INJECT_TYPE,
1215  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_ECC_TYPE,
1216  0u,
1217  NULL },
1218  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_ID,
1219  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_INJECT_TYPE,
1220  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_ECC_TYPE,
1221  0u,
1222  NULL },
1223  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_ID,
1224  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_INJECT_TYPE,
1225  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_ECC_TYPE,
1226  0u,
1227  NULL },
1228  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_ID,
1229  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_INJECT_TYPE,
1230  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_ECC_TYPE,
1231  0u,
1232  NULL },
1233  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_ID,
1234  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_INJECT_TYPE,
1235  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_ECC_TYPE,
1236  0u,
1237  NULL },
1238 };
1239 
1244 static const SDL_RAMIdEntry_t SDL_HSM_ECC_AGGR_RamIdTable[SDL_HSM_ECC_AGGR_NUM_RAMS] =
1245 {
1246  { SDL_HSM_ECC_AGGR_RAMB0_RAM_ID,
1247  SDL_HSM_ECC_AGGR_RAMB0_INJECT_TYPE,
1248  SDL_HSM_ECC_AGGR_RAMB0_ECC_TYPE,
1249  0u,
1250  NULL },
1251  { SDL_HSM_ECC_AGGR_RAMB1_RAM_ID,
1252  SDL_HSM_ECC_AGGR_RAMB1_INJECT_TYPE,
1253  SDL_HSM_ECC_AGGR_RAMB1_ECC_TYPE,
1254  0u,
1255  NULL },
1256  { SDL_HSM_ECC_AGGR_RAMB2_RAM_ID,
1257  SDL_HSM_ECC_AGGR_RAMB2_INJECT_TYPE,
1258  SDL_HSM_ECC_AGGR_RAMB2_ECC_TYPE,
1259  0u,
1260  NULL },
1261  { SDL_HSM_ECC_AGGR_RAMB3_RAM_ID,
1262  SDL_HSM_ECC_AGGR_RAMB3_INJECT_TYPE,
1263  SDL_HSM_ECC_AGGR_RAMB3_ECC_TYPE,
1264  0u,
1265  NULL },
1266  { SDL_HSM_ECC_AGGR_SECUREB4_RAM_ID,
1267  SDL_HSM_ECC_AGGR_SECUREB4_INJECT_TYPE,
1268  SDL_HSM_ECC_AGGR_SECUREB4_ECC_TYPE,
1269  0u,
1270  NULL },
1271  { SDL_HSM_ECC_AGGR_MBOX_RAM_ID,
1272  SDL_HSM_ECC_AGGR_MBOX_INJECT_TYPE,
1273  SDL_HSM_ECC_AGGR_MBOX_ECC_TYPE,
1274  0u,
1275  NULL },
1276  { SDL_HSM_ECC_AGGR_SECURE_RAM_ID,
1277  SDL_HSM_ECC_AGGR_SECURE_INJECT_TYPE,
1278  SDL_HSM_ECC_AGGR_SECURE_ECC_TYPE,
1279  0u,
1280  NULL },
1281  { SDL_HSM_ECC_AGGR_ROM_RAM_ID,
1282  SDL_HSM_ECC_AGGR_ROM_INJECT_TYPE,
1283  SDL_HSM_ECC_AGGR_ROM_ECC_TYPE,
1284  0u,
1285  NULL },
1286  { SDL_HSM_ECC_AGGR_TPTC_A0_RAM_ID,
1287  SDL_HSM_ECC_AGGR_TPTC_A0_INJECT_TYPE,
1288  SDL_HSM_ECC_AGGR_TPTC_A0_ECC_TYPE,
1289  0u,
1290  NULL },
1291  { SDL_HSM_ECC_AGGR_TPTC_A1_RAM_ID,
1292  SDL_HSM_ECC_AGGR_TPTC_A1_INJECT_TYPE,
1293  SDL_HSM_ECC_AGGR_TPTC_A1_ECC_TYPE,
1294  0u,
1295  NULL },
1296 };
1297 
1302 static const SDL_RAMIdEntry_t SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable[SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_NUM_RAMS] =
1303 {
1304  { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_ID,
1305  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_INJECT_TYPE,
1306  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_ECC_TYPE,
1307  0u,
1308  NULL },
1309  { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_ID,
1310  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_INJECT_TYPE,
1311  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_ECC_TYPE,
1312  0u,
1313  NULL },
1314  { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_ID,
1315  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_INJECT_TYPE,
1316  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_ECC_TYPE,
1317  0u,
1318  NULL },
1319  { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_ID,
1320  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_INJECT_TYPE,
1321  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_ECC_TYPE,
1322  0u,
1323  NULL },
1324  { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_ID,
1325  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_INJECT_TYPE,
1326  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_ECC_TYPE,
1327  0u,
1328  NULL },
1329 };
1330 
1335 static const SDL_RAMIdEntry_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
1336 {
1337  { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
1338  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
1339  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
1340  0u,
1341  NULL }
1342 };
1343 
1348 static const SDL_RAMIdEntry_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
1349 {
1350  { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
1351  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
1352  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
1353  0u,
1354  NULL }
1355 };
1356 
1361 static const SDL_RAMIdEntry_t SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
1362 {
1363  { SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
1364  SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
1365  SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
1366  0u,
1367  NULL }
1368 };
1369 
1374 static const SDL_RAMIdEntry_t SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
1375 {
1376  { SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
1377  SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
1378  SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
1379  0u,
1380  NULL }
1381 };
1382 
1387 static const SDL_RAMIdEntry_t SDL_CPSW3GCSS_ECC_AGGR_RamIdTable[SDL_CPSW3GCSS_ECC_AGGR_NUM_RAMS] =
1388 {
1389  { SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_RAM_ID,
1390  SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_INJECT_TYPE,
1391  SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_ECC_TYPE,
1392  0u,
1393  NULL },
1394  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_RAM_ID,
1395  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_INJECT_TYPE,
1396  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_ECC_TYPE,
1397  0u,
1398  NULL },
1399  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_RAM_ID,
1400  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_INJECT_TYPE,
1401  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_ECC_TYPE,
1402  0u,
1403  NULL },
1404  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_RAM_ID,
1405  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_INJECT_TYPE,
1406  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_ECC_TYPE,
1407  0u,
1408  NULL },
1409  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_RAM_ID,
1410  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_INJECT_TYPE,
1411  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_ECC_TYPE,
1412  0u,
1413  NULL },
1414  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_RAM_ID,
1415  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_INJECT_TYPE,
1416  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_ECC_TYPE,
1417  0u,
1418  NULL },
1419  { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_RAM_ID,
1420  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_INJECT_TYPE,
1421  SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_ECC_TYPE,
1422  0u,
1423  NULL },
1424  { SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_EST_RAM_ECC_RAM_ID,
1425  SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_EST_RAM_ECC_INJECT_TYPE,
1426  SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_EST_RAM_ECC_ECC_TYPE,
1427  0u,
1428  NULL },
1429 };
1430 
1431 static SDL_ecc_aggrRegs * const SDL_ECC_aggrBaseAddressTable[SDL_ECC_Base_Address_TOTAL_ENTRIES] =
1432 {
1433  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ECC_AGG_TOP_U_BASE)),
1434  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ECC_AGG_R5SS0_CORE0_U_BASE)),
1435  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ECC_AGG_R5SS1_CORE0_U_BASE)),
1436  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ECC_AGG_R5SS0_CORE1_U_BASE)),
1437  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ECC_AGG_R5SS1_CORE1_U_BASE )),
1438  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_HSM_ECC_AGGR_U_BASE)),
1439  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ICSSM0_ECC_U_BASE)),
1440  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN0_ECC_U_BASE)),
1441  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN1_ECC_U_BASE)),
1442  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN2_ECC_U_BASE)),
1443  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN3_ECC_U_BASE)),
1444 
1445 };
1446 
1447 SDL_ecc_aggrRegs * SDL_ECC_aggrTransBaseAddressTable[SDL_ECC_MEMTYPE_MAX];
1450 static const SDL_EccAggrEntry_t SDL_ECC_aggrTable[SDL_ECC_MEMTYPE_MAX] =
1451 {
1452 
1453  /* Index: SDL_SOC_ECC_AGGR (0) */
1454  {
1455  SDL_SOC_ECC_AGGR_NUM_RAMS,
1456  SDL_SOC_ECC_AGGR_RamIdTable,
1457  SDL_SOC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1458  SDL_SOC_ECC_AGGR_MemEntries,
1459  SDL_ESM_INST_MAIN_ESM0,
1460  SDL_ESM0_ECC_AGGREGATOR_SOC_ECCAGG_CORR_LEVEL,
1461  SDL_ESM0_ECC_AGGREGATOR_SOC_ECCAGG_UNCORR_LEVEL
1462  },
1463  /* Index: SDL_R5FSS0_CORE0_ECC_AGGR (1) */
1464  {
1465  SDL_R5FSS0_CORE0_ECC_AGGR_NUM_RAMS,
1466  SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable,
1467  SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1468  SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries,
1469  SDL_ESM_INST_MAIN_ESM0,
1470  SDL_ESM0_R5FSS0_CORE0_R5FSS0_CORE0_ECC_CORRECTED_LEVEL_0,
1471  SDL_ESM0_R5FSS0_CORE0_R5FSS0_CORE0_ECC_UNCORRECTED_LEVEL_0
1472  },
1473  /* Index: SDL_R5FSS0_CORE1_ECC_AGGR (2) */
1474  {
1475  SDL_R5FSS0_CORE1_ECC_AGGR_NUM_RAMS,
1476  SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable,
1477  SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1478  SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries,
1479  SDL_ESM_INST_MAIN_ESM0,
1480  SDL_ESM0_R5FSS0_CORE1_R5FSS0_CORE1_ECC_CORRECTED_LEVEL_0,
1481  SDL_ESM0_R5FSS0_CORE1_R5FSS0_CORE1_ECC_UNCORRECTED_LEVEL_0
1482  },
1483  /* Index: SDL_R5FSS1_CORE0_ECC_AGGR (3) */
1484  {
1485  SDL_R5FSS1_CORE0_ECC_AGGR_NUM_RAMS,
1486  SDL_R5FSS1_CORE0_ECC_AGGR_RamIdTable,
1487  SDL_R5FSS1_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1488  SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries,
1489  SDL_ESM_INST_MAIN_ESM0,
1490  SDL_ESM0_R5FSS1_CORE0_R5FSS1_CORE0_ECC_CORRECTED_LEVEL_0,
1491  SDL_ESM0_R5FSS1_CORE0_R5FSS1_CORE0_ECC_UNCORRECTED_LEVEL_0
1492  },
1493  /* Index: SDL_R5FSS1_CORE1_ECC_AGGR (4) */
1494  {
1495  SDL_R5FSS1_CORE1_ECC_AGGR_NUM_RAMS,
1496  SDL_R5FSS1_CORE1_ECC_AGGR_RamIdTable,
1497  SDL_R5FSS1_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1498  SDL_R5FSS1_CORE1_ECC_AGGR_MemEntries,
1499  SDL_ESM_INST_MAIN_ESM0,
1500  SDL_ESM0_R5FSS1_CORE1_R5FSS1_CORE1_ECC_CORRECTED_LEVEL_0,
1501  SDL_ESM0_R5FSS1_CORE1_R5FSS1_CORE1_ECC_UNCORRECTED_LEVEL_0
1502  },
1503  /* Index: SDL_HSM_ECC_AGGR (5) */
1504  {
1505  SDL_HSM_ECC_AGGR_NUM_RAMS,
1506  SDL_HSM_ECC_AGGR_RamIdTable,
1507  SDL_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1508  SDL_HSM_ECC_AGGR_MemEntries,
1509  SDL_ESM_INST_MAIN_ESM0,
1510  SDL_ESM0_HSM_ESM_HIGH_INTR,
1511  SDL_ESM0_HSM_ESM_LOW_INTR
1512  },
1513  /* Index: SDL_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR (6) */
1514  {
1515  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_NUM_RAMS,
1516  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable,
1517  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1518  SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries,
1519  SDL_ESM_INST_MAIN_ESM0,
1520  SDL_ESM0_PRU_ICSSM0_PR1_ECC_SEC_ERR_REQ,
1521  SDL_ESM0_PRU_ICSSM0_PR1_ECC_DED_ERR_REQ
1522  },
1523  /* Index: SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR (7) */
1524  {
1525  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
1526  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
1527  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1528  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
1529  SDL_ESM_INST_MAIN_ESM0,
1530  SDL_ESM0_MCAN0_MCAN0_ECC_CORR_LVL_INT,
1531  SDL_ESM0_MCAN0_MCAN0_ECC_UNCORR_LVL_INT
1532  },
1533  /* Index: SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR (8) */
1534  {
1535  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
1536  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
1537  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1538  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
1539  SDL_ESM_INST_MAIN_ESM0,
1540  SDL_ESM0_MCAN1_MCAN1_ECC_CORR_LVL_INT,
1541  SDL_ESM0_MCAN1_MCAN1_ECC_UNCORR_LVL_INT
1542  },
1543  /* Index: SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR (9) */
1544  {
1545  SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
1546  SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
1547  SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1548  SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
1549  SDL_ESM_INST_MAIN_ESM0,
1550  SDL_ESM0_MCAN2_MCAN2_ECC_CORR_LVL_INT,
1551  SDL_ESM0_MCAN2_MCAN2_ECC_UNCORR_LVL_INT
1552  },
1553  /* Index: SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR (10) */
1554  {
1555  SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
1556  SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
1557  SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1558  SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
1559  SDL_ESM_INST_MAIN_ESM0,
1560  SDL_ESM0_MCAN3_MCAN3_ECC_CORR_LVL_INT,
1561  SDL_ESM0_MCAN3_MCAN3_ECC_UNCORR_LVL_INT
1562  },
1563  /* Index: SDL_CPSW3GCSS_ECC_AGGR (11) */
1564  {
1565  SDL_CPSW3GCSS_ECC_AGGR_NUM_RAMS,
1566  SDL_CPSW3GCSS_ECC_AGGR_RamIdTable,
1567  SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1568  SDL_CPSW3GCSS_ECC_AGGR_MemEntries,
1569  SDL_ESM_INST_MAIN_ESM0,
1570  SDL_ESM0_CPSW3G_CPSW_ECC_SEC_PEND_INTR,
1571  SDL_ESM0_CPSW3G_CPSW_ECC_DED_PEND_INTR
1572  },
1573 
1574 
1575  };
1576  #endif /* INCLUDE_SDL_ECC_SOC_H_ */
SDL_R5FSS1_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_R5FSS1_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: am263x/sdl_ecc_soc.h:63
SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: am263x/sdl_ecc_soc.h:535
SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: am263x/sdl_ecc_soc.h:68
SDL_HSM_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_HSM_ECC_AGGR_RamIdTable[SDL_HSM_ECC_AGGR_NUM_RAMS]
Definition: am263x/sdl_ecc_soc.h:1244
SDL_CPSW3GCSS_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_CPSW3GCSS_ECC_AGGR_MemEntries[SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: am263x/sdl_ecc_soc.h:579
SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: am263x/sdl_ecc_soc.h:66
SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: am263x/sdl_ecc_soc.h:1335
SDL_ecc_aggrRegs
Definition: V1/sdlr_ecc.h:53
SDL_ECC_Base_Address_TOTAL_ENTRIES
#define SDL_ECC_Base_Address_TOTAL_ENTRIES
Definition: am263x/sdl_ecc_soc.h:71
SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: am263x/sdl_ecc_soc.h:568
SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: am263x/sdl_ecc_soc.h:1348
SDL_R5FSS1_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_R5FSS1_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: am263x/sdl_ecc_soc.h:62
SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: am263x/sdl_ecc_soc.h:557
SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: am263x/sdl_ecc_soc.h:67
SDL_R5FSS1_CORE1_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_R5FSS1_CORE1_ECC_AGGR_RamIdTable[SDL_R5FSS1_CORE1_ECC_AGGR_NUM_RAMS]
Definition: am263x/sdl_ecc_soc.h:1096
SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: am263x/sdl_ecc_soc.h:70
SDL_R5FSS1_CORE0_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_R5FSS1_CORE0_ECC_AGGR_MemEntries[SDL_R5FSS1_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: am263x/sdl_ecc_soc.h:290
sdl_ip_ecc.h
SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: am263x/sdl_ecc_soc.h:106
SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: am263x/sdl_ecc_soc.h:60
SDL_MemConfig_t
Definition: sdl_ecc_priv.h:88
SDL_ECC_aggrTable
static const SDL_EccAggrEntry_t SDL_ECC_aggrTable[SDL_ECC_MEMTYPE_MAX]
Definition: am263x/sdl_ecc_soc.h:1450
SDL_R5FSS1_CORE1_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_R5FSS1_CORE1_ECC_AGGR_MemEntries[SDL_R5FSS1_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: am263x/sdl_ecc_soc.h:382
SDL_CPSW3GCSS_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_CPSW3GCSS_ECC_AGGR_RamIdTable[SDL_CPSW3GCSS_ECC_AGGR_NUM_RAMS]
Definition: am263x/sdl_ecc_soc.h:1387
sdl_ecc.h
Header file contains enumerations, structure definitions and function.
SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE1_ECC_AGGR_NUM_RAMS]
Definition: am263x/sdl_ecc_soc.h:801
SDL_SOC_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_SOC_ECC_AGGR_RamIdTable[SDL_SOC_ECC_AGGR_NUM_RAMS]
Definition: am263x/sdl_ecc_soc.h:610
SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: am263x/sdl_ecc_soc.h:65
SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable[SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_NUM_RAMS]
Definition: am263x/sdl_ecc_soc.h:1302
SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries[SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: am263x/sdl_ecc_soc.h:512
SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: am263x/sdl_ecc_soc.h:198
SDL_HSM_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_HSM_ECC_AGGR_MemEntries[SDL_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: am263x/sdl_ecc_soc.h:474
SDL_SOC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_SOC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: am263x/sdl_ecc_soc.h:59
SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: am263x/sdl_ecc_soc.h:1374
SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: am263x/sdl_ecc_soc.h:61
SDL_RAMIdEntry_t
Definition: sdl_ecc_priv.h:63
SDL_R5FSS1_CORE0_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_R5FSS1_CORE0_ECC_AGGR_RamIdTable[SDL_R5FSS1_CORE0_ECC_AGGR_NUM_RAMS]
Definition: am263x/sdl_ecc_soc.h:948
SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE0_ECC_AGGR_NUM_RAMS]
Definition: am263x/sdl_ecc_soc.h:653
SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: am263x/sdl_ecc_soc.h:69
SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: am263x/sdl_ecc_soc.h:546
SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: am263x/sdl_ecc_soc.h:1361
SDL_EccAggrEntry_t
Definition: sdl_ecc_priv.h:104
SDL_ECC_aggrBaseAddressTable
static SDL_ecc_aggrRegs *const SDL_ECC_aggrBaseAddressTable[SDL_ECC_Base_Address_TOTAL_ENTRIES]
Definition: am263x/sdl_ecc_soc.h:1431
SDL_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: am263x/sdl_ecc_soc.h:64
SDL_ECC_aggrTransBaseAddressTable
SDL_ecc_aggrRegs * SDL_ECC_aggrTransBaseAddressTable[SDL_ECC_MEMTYPE_MAX]
Definition: am263x/sdl_ecc_soc.h:1447
sdl_ecc_priv.h
SDL_ECC_WIDTH_UNDEFINED
#define SDL_ECC_WIDTH_UNDEFINED
Definition: am263x/sdl_ecc_soc.h:56
SDL_SOC_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_SOC_ECC_AGGR_MemEntries[SDL_SOC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: am263x/sdl_ecc_soc.h:77