AM263x MCU+ SDK  10.00.00
GPMC_HwAttrs Struct Reference

Detailed Description

GPMC instance attributes.

Data Fields

uint32_t gpmcBaseAddr
 
uint32_t dataBaseAddr
 
uint32_t elmBaseAddr
 
uint32_t inputClkFreq
 
uint32_t intrNum
 
uint32_t intrPriority
 
uint32_t clkDivider
 
uint32_t addrDataMux
 
uint32_t timeLatency
 
uint32_t chipSelBaseAddr
 
uint32_t chipSelAddrSize
 
uint32_t waitPinNum
 
uint32_t waitPinPol
 
GPMC_timingParams timingParams
 
GPMC_nandEccAlgo eccAlgo
 
uint32_t readType
 
uint32_t writeType
 
uint32_t csExDelay
 
uint32_t accessType
 
uint32_t optimisedAccess
 
uint32_t cycleOptimisation
 
const GPMC_AddrRegiondmaRestrictedRegions
 

Field Documentation

◆ gpmcBaseAddr

uint32_t GPMC_HwAttrs::gpmcBaseAddr

GPMC Peripheral base address.

◆ dataBaseAddr

uint32_t GPMC_HwAttrs::dataBaseAddr

GPMC flash base address.

◆ elmBaseAddr

uint32_t GPMC_HwAttrs::elmBaseAddr

Error Location Module base address for ECC computation.

◆ inputClkFreq

uint32_t GPMC_HwAttrs::inputClkFreq

GPMC module input clock frequency.

◆ intrNum

uint32_t GPMC_HwAttrs::intrNum

GPMC Peripheral interupt number.

◆ intrPriority

uint32_t GPMC_HwAttrs::intrPriority

Interupt priority

◆ clkDivider

uint32_t GPMC_HwAttrs::clkDivider

GPMC FCLK divider

◆ addrDataMux

uint32_t GPMC_HwAttrs::addrDataMux

Address and data multiplexed protocol

◆ timeLatency

uint32_t GPMC_HwAttrs::timeLatency

Current Active chip select in use by the memory controller

◆ chipSelBaseAddr

uint32_t GPMC_HwAttrs::chipSelBaseAddr

Chip select base address (A29 - A24)

◆ chipSelAddrSize

uint32_t GPMC_HwAttrs::chipSelAddrSize

Chip select address mask size

◆ waitPinNum

uint32_t GPMC_HwAttrs::waitPinNum

Wait pin number

◆ waitPinPol

uint32_t GPMC_HwAttrs::waitPinPol

Wait pin polarity

◆ timingParams

GPMC_timingParams GPMC_HwAttrs::timingParams

Structure holding the timing parameters for the GPMC instance.

◆ eccAlgo

GPMC_nandEccAlgo GPMC_HwAttrs::eccAlgo

ECC algorithm supported by the controller.

◆ readType

uint32_t GPMC_HwAttrs::readType

Read operation mode

◆ writeType

uint32_t GPMC_HwAttrs::writeType

Write operation mode

◆ csExDelay

uint32_t GPMC_HwAttrs::csExDelay

Chip Select Extra Delay flag.

◆ accessType

uint32_t GPMC_HwAttrs::accessType

Prefetch/Postwrite engine optimised access.

◆ optimisedAccess

uint32_t GPMC_HwAttrs::optimisedAccess

Cycle optimisation for prefetch/post write engine.

◆ cycleOptimisation

uint32_t GPMC_HwAttrs::cycleOptimisation

Memory access type

◆ dmaRestrictedRegions

const GPMC_AddrRegion* GPMC_HwAttrs::dmaRestrictedRegions

Pointer to array of GPMC_AddrRegion data structures filled by SysConfig. The array should be terminated by a { 0xFFFFFFFFU, 0U } entry. It is used while using DMA copy to check if the destination address is a region not accessible to DMA and switch to CPU copy