Introduction

This file contains the prototypes of the APIs present in the device abstraction layer file of STC. This also contains some related macros.

Go to the source code of this file.

Data Structures
struct	__attribute__
	EDMA Parameter RAM Set in User Configurable format This is a mapping of the EDMA PaRAM set provided to the user for ease of modification of the individual fields. More...

struct	__attribute__
	EDMA Parameter RAM Set in User Configurable format This is a mapping of the EDMA PaRAM set provided to the user for ease of modification of the individual fields. More...

struct	SDL_stcRegs

Macros
#define	STC_MSS_INTERVAL_NUM (uint32_t)(1U)

#define	STC_MSS_LP_SCAN_MODE (uint32_t)(0U)

#define	STC_MSS_CODEC_SPREAD_MODE (uint32_t)(1U)

#define	STC_MSS_CAP_IDLE_CYCLE (uint32_t)(3U)

#define	STC_MSS_SCANEN_HIGH_CAP_IDLE_CYCLE (uint32_t)(3U)

#define	STC_MSS_MAX_RUN_TIME (uint32_t)(0xFFFFFFFFU)

#define	STC_MSS_CLK_DIV (uint32_t)(1U)

#define	STC_ROM_START_ADDRESS (uint32_t)(0U)

#define	STC_pROM_START_ADDRESS (uint32_t)(1U)

#define	STC_DSS_INTERVAL_NUM (uint32_t)(2U)

#define	STC_DSS_LP_SCAN_MODE (uint32_t)(0U)

#define	STC_DSS_CODEC_SPREAD_MODE (uint32_t)(1U)

#define	STC_DSS_CAP_IDLE_CYCLE (uint32_t)(3U)

#define	STC_DSS_SCANEN_HIGH_CAP_IDLE_CYCLE (uint32_t)(3U)

#define	STC_DSS_MAX_RUN_TIME (uint32_t)(0x13332U)

#define	STC_DSS_CLK_DIV (uint32_t)(1U)

#define	STC_ROM_START_ADDRESS (uint32_t)(0U)

#define	STC_pROM_START_ADDRESS (uint32_t)(1U)

#define	SDL_STC_STCGCR0 (0x00000000U)

#define	SDL_STC_STCGCR1 (0x00000004U)

#define	SDL_STC_STCTPR (0x00000008U)

#define	SDL_STC_CADDR (0x0000000CU)

#define	SDL_STC_STCCICR (0x00000010U)

#define	SDL_STC_STCGSTAT (0x00000014U)

#define	SDL_STC_STCFSTAT (0x00000018U)

#define	SDL_STC_STCSCSCR (0x0000001CU)

#define	SDL_STC_CADDR2 (0x00000020U)

#define	SDL_STC_CLKDIV (0x00000024U)

#define	SDL_STC_SEGPLR (0x00000028U)

#define	SDL_STC_SEG0_START_ADDR (0x0000002CU)

#define	SDL_STC_SEG1_START_ADDR (0x00000030U)

#define	SDL_STC_SEG2_START_ADDR (0x00000034U)

#define	SDL_STC_SEG3_START_ADDR (0x00000038U)

#define	SDL_STC_STCGCR0_INTCOUNT_B16_MASK (0xFFFF0000U)

#define	SDL_STC_STCGCR0_INTCOUNT_B16_SHIFT (16U)

#define	SDL_STC_STCGCR0_INTCOUNT_B16_MAX (0xFFFF0000U)

#define	SDL_STC_STCGCR0_CAP_IDLE_CYCLE_MASK (0x00000700U)

#define	SDL_STC_STCGCR0_CAP_IDLE_CYCLE_SHIFT (8U)

#define	SDL_STC_STCGCR0_CAP_IDLE_CYCLE_MAX (0x00000700U)

#define	SDL_STC_STCGCR0_SCANEN_HIGH_CAP_IDLE_CYCLE_MASK (0x000000E0U)

#define	SDL_STC_STCGCR0_SCANEN_HIGH_CAP_IDLE_CYCLE_SHIFT (5U)

#define	SDL_STC_STCGCR0_SCANEN_HIGH_CAP_IDLE_CYCLE_MAX (0x000000E0U)

#define	SDL_STC_STCGCR0_RS_CNT_B1_MASK (0x00000003U)

#define	SDL_STC_STCGCR0_RS_CNT_B1_SHIFT (0U)

#define	SDL_STC_SEG0_CORE_SEL_MASK (0x00000F00U)

#define	SDL_STC_SEG0_CORE_SEL_SHIFT (8U)

#define	SDL_STC_SEG0_CORE_SEL_ENABLE (0x1U)

#define	SDL_STC_CODEC_SPREAD_MODE_MASK (0x00000040U)

#define	SDL_STC_CODEC_SPREAD_MODE_SHIFT (6U)

#define	SDL_STC_CODEC_SPREAD_MODE_ENABLE (0x1U)

#define	SDL_STC_CODEC_SPREAD_MODE_DISABLE (0x0U)

#define	SDL_STC_LP_SCAN_MODE_MASK (0x00000020U)

#define	SDL_STC_LP_SCAN_MODE_SHIFT (5U)

#define	SDL_STC_LP_SCAN_MODE_ENABLE (0x1U)

#define	SDL_STC_LP_SCAN_MODE_DISABLE (0x0U)

#define	SDL_STC_ROM_ACCESS_INV_MASK (0x00000010U)

#define	SDL_STC_ROM_ACCESS_INV_SHIFT (4U)

#define	SDL_STC_ROM_ACCESS_INV_DISABLE (0x0U)

#define	SDL_STC_ST_ENA_B4_MASK (0x0000000FU)

#define	SDL_STC_ST_ENA_B4_SHIFT (0x00000000U)

#define	SDL_STC_ST_ENA_B4_ENABLE (0xAU)

#define	SDL_STC_TO_PRELOAD_MASK (0xFFFFFFFFU)

#define	SDL_STC_TO_PRELOAD_SHIFT (0x00000000U)

#define	SDL_STC_TO_PRELOAD_MAX (0xFFFFFFFFU)

#define	SDL_STC_ADDR1_MASK (0xFFFFFFFFU)

#define	SDL_STC_ADDR1_SHIFT (0x00000000U)

#define	SDL_STC_CORE2_ICOUNT_MASK (0xFFFF0000U)

#define	SDL_STC_CORE2_ICOUNT_SHIFT (16U)

#define	SDL_STC_CORE1_ICOUNT_MASK (0x0000FFFFU)

#define	SDL_STC_CORE1_ICOUNT_SHIFT (0x00000000U)

#define	SDL_STC_ST_ACTIVE_MASK (0x00000F00U)

#define	SDL_STC_ST_ACTIVE_SHIFT (8U)

#define	SDL_STC_ST_ACTIVE_ENABLE (0xAU)

#define	SDL_STC_TEST_FAIL_MASK (0x00000002U)

#define	SDL_STC_TEST_FAIL_SHIFT (1U)

#define	SDL_STC_TEST_FAIL_ENABLE (0x1U)

#define	SDL_STC_TEST_FAIL_DISABLE (0x0U)

#define	SDL_STC_TEST_DONE_MASK (0x00000001U)

#define	SDL_STC_TEST_DONE_SHIFT (0U)

#define	SDL_STC_TEST_DONE_ENABLE (0x1U)

#define	SDL_STC_TEST_DONE_DISABLE (0x0U)

#define	SDL_STC_FSEG_ID_MASK (0x00000018U)

#define	SDL_STC_FSEG_ID_SHIFT (3U)

#define	SDL_STC_TO_ER_B1_MASK (0x00000004U)

#define	SDL_STC_TO_ER_B1_SHIFT (2U)

#define	SDL_STC_TO_ER_B1_ENABLE (0x1U)

#define	SDL_STC_TO_ER_B1_DISABLE (0x0U)

#define	SDL_STC_CPU2_FAIL_B1_MASK (0x00000002U)

#define	SDL_STC_CPU2_FAIL_B1_SHIFT (0x1U)

#define	SDL_STC_CPU2_FAIL_B1_ENABLE (0x1U)

#define	SDL_STC_CPU2_FAIL_B1_DISABLE (0x0U)

#define	SDL_STC_CPU1_FAIL_B1_MASK (0x00000001U)

#define	SDL_STC_CPU1_FAIL_B1_SHIFT (0U)

#define	SDL_STC_CPU1_FAIL_B1_ENABLE (0x1U)

#define	SDL_STC_CPU1_FAIL_B1_DISABLE (0x0U)

#define	SDL_STC_FAULT_INS_B1_MASK (0x00000010U)

#define	SDL_STC_FAULT_INS_B1_SHIFT (4U)

#define	SDL_STC_FAULT_INS_B1_ENABLE (0x1U)

#define	SDL_STC_FAULT_INS_B1_DISABLE (0x0U)

#define	SDL_STC_SELF_CHECK_KEY_B4_MASK (0x0000000FU)

#define	SDL_STC_SELF_CHECK_KEY_B4_SHIFT (0U)

#define	SDL_STC_SELF_CHECK_KEY_B4_ENABLE (0xAU)

#define	SDL_STC_SELF_CHECK_KEY_B4_DISABLE (0U)

#define	SDL_STC_ADDR2_MASK (0xFFFFFFFFU)

#define	SDL_STC_ADDR2_SHIFT (0x00000000U)

#define	SDL_STC_CLKDIV0_MASK (0x07000000U)

#define	SDL_STC_CLKDIV0_SHIFT (24U)

#define	SDL_STC_CLKDIV1_MASK (0x00070000U)

#define	SDL_STC_CLKDIV1_SHIFT (16U)

#define	SDL_STC_CLKDIV2_MASK (0x00000700U)

#define	SDL_STC_CLKDIV2_SHIFT (8U)

#define	SDL_STC_CLKDIV3_MASK (0x00000007U)

#define	SDL_STC_CLKDIV3_SHIFT (0U)

#define	SDL_STC_SEGPLR_MASK (0x00000003U)

#define	SDL_STC_SEGPLR_SHIFT (0U)

#define	SDL_STC_SEG0_START_ADDR_MASK (0x000FFFFFU)

#define	SDL_STC_SEG0_START_ADDR_SHIFT (0U)

#define	SDL_STC_SEG1_START_ADDR0_MASK (0x000FFFFFU)

#define	SDL_STC_SEG1_START_ADDR0_SHIFT (0U)

#define	SDL_STC_SEG2_START_ADDR0_MASK (0x000FFFFFU)

#define	SDL_STC_SEG2_START_ADDR0_SHIFT (0U)

#define	SDL_STC_SEG3_START_ADDR0_MASK (0x000FFFFFU)

#define	SDL_STC_SEG3_START_ADDR0_SHIFT (0U)

#define	SDL_MSS_STC_RESET_MASK (0x00000004U)

#define	SDL_MSS_STC_RESET_SHIFT (2U)

#define	SDL_MSS_STC_RESET_CLEAR_MASK (0x00000007)

#define	SDL_MSS_STC_RESET_CLEAR_SHIFT (0U)

#define	SDL_MSS_STC_RESET_CLEAR_ENABLE (0x7U)

#define	SDL_DSS_STC_RESET_MASK (0x00000020U)

#define	SDL_DSS_STC_RESET_SHIFT (5U)

Enumerations
enum	SDL_STC_TestResult { SDL_STC_COMPLETED_SUCCESS, SDL_STC_COMPLETED_FAILURE, SDL_STC_NOT_COMPLETED, SDL_STC_NOT_RUN, INVALID_RESULT }

enum	SDL_STC_TestType { SDL_STC_TEST, SDL_STC_NEG_TEST }

Functions
int32_t	SDL_STC_getStatus (SDL_STC_Inst instance)
	This API is used to get status for STC result. More...

int32_t	SDL_STC_selfTest (SDL_STC_Inst instance, SDL_STC_TestType testType, SDL_STC_Config *pConfig)
	This API is used to run the STC module. More...

static int32_t	SDL_STC_configure (SDL_STC_Inst instance, SDL_STC_Config *pConfig, SDL_STC_TestType testType)
	This API is used to configure STC module. More...

static int32_t	SDL_STC_runTest (SDL_STC_Inst instance)
	This API is used to enable the STC module. More...

static void	SDL_STC_delay (int32_t count)
	This API is used to provide delay for processor core. More...

Macro Definition Documentation

◆ SDL_STC_STCGCR0

#define SDL_STC_STCGCR0 (0x00000000U)

◆ SDL_STC_STCGCR1

#define SDL_STC_STCGCR1 (0x00000004U)

◆ SDL_STC_STCTPR

#define SDL_STC_STCTPR (0x00000008U)

◆ SDL_STC_CADDR

#define SDL_STC_CADDR (0x0000000CU)

◆ SDL_STC_STCCICR

#define SDL_STC_STCCICR (0x00000010U)

◆ SDL_STC_STCGSTAT

#define SDL_STC_STCGSTAT (0x00000014U)

◆ SDL_STC_STCFSTAT

#define SDL_STC_STCFSTAT (0x00000018U)

◆ SDL_STC_STCSCSCR

#define SDL_STC_STCSCSCR (0x0000001CU)

◆ SDL_STC_CADDR2

#define SDL_STC_CADDR2 (0x00000020U)

◆ SDL_STC_CLKDIV

#define SDL_STC_CLKDIV (0x00000024U)

◆ SDL_STC_SEGPLR

#define SDL_STC_SEGPLR (0x00000028U)

◆ SDL_STC_SEG0_START_ADDR

#define SDL_STC_SEG0_START_ADDR (0x0000002CU)

◆ SDL_STC_SEG1_START_ADDR

#define SDL_STC_SEG1_START_ADDR (0x00000030U)

◆ SDL_STC_SEG2_START_ADDR

#define SDL_STC_SEG2_START_ADDR (0x00000034U)

◆ SDL_STC_SEG3_START_ADDR

#define SDL_STC_SEG3_START_ADDR (0x00000038U)

◆ SDL_STC_STCGCR0_INTCOUNT_B16_MASK

#define SDL_STC_STCGCR0_INTCOUNT_B16_MASK (0xFFFF0000U)

◆ SDL_STC_STCGCR0_INTCOUNT_B16_SHIFT

#define SDL_STC_STCGCR0_INTCOUNT_B16_SHIFT (16U)

◆ SDL_STC_STCGCR0_INTCOUNT_B16_MAX

#define SDL_STC_STCGCR0_INTCOUNT_B16_MAX (0xFFFF0000U)

◆ SDL_STC_STCGCR0_CAP_IDLE_CYCLE_MASK

#define SDL_STC_STCGCR0_CAP_IDLE_CYCLE_MASK (0x00000700U)

◆ SDL_STC_STCGCR0_CAP_IDLE_CYCLE_SHIFT

#define SDL_STC_STCGCR0_CAP_IDLE_CYCLE_SHIFT (8U)

◆ SDL_STC_STCGCR0_CAP_IDLE_CYCLE_MAX

#define SDL_STC_STCGCR0_CAP_IDLE_CYCLE_MAX (0x00000700U)

◆ SDL_STC_STCGCR0_SCANEN_HIGH_CAP_IDLE_CYCLE_MASK

#define SDL_STC_STCGCR0_SCANEN_HIGH_CAP_IDLE_CYCLE_MASK (0x000000E0U)

◆ SDL_STC_STCGCR0_SCANEN_HIGH_CAP_IDLE_CYCLE_SHIFT

#define SDL_STC_STCGCR0_SCANEN_HIGH_CAP_IDLE_CYCLE_SHIFT (5U)

◆ SDL_STC_STCGCR0_SCANEN_HIGH_CAP_IDLE_CYCLE_MAX

#define SDL_STC_STCGCR0_SCANEN_HIGH_CAP_IDLE_CYCLE_MAX (0x000000E0U)

◆ SDL_STC_STCGCR0_RS_CNT_B1_MASK

#define SDL_STC_STCGCR0_RS_CNT_B1_MASK (0x00000003U)

◆ SDL_STC_STCGCR0_RS_CNT_B1_SHIFT

#define SDL_STC_STCGCR0_RS_CNT_B1_SHIFT (0U)

◆ SDL_STC_SEG0_CORE_SEL_MASK

#define SDL_STC_SEG0_CORE_SEL_MASK (0x00000F00U)

◆ SDL_STC_SEG0_CORE_SEL_SHIFT

#define SDL_STC_SEG0_CORE_SEL_SHIFT (8U)

◆ SDL_STC_SEG0_CORE_SEL_ENABLE

#define SDL_STC_SEG0_CORE_SEL_ENABLE (0x1U)

◆ SDL_STC_CODEC_SPREAD_MODE_MASK

#define SDL_STC_CODEC_SPREAD_MODE_MASK (0x00000040U)

◆ SDL_STC_CODEC_SPREAD_MODE_SHIFT

#define SDL_STC_CODEC_SPREAD_MODE_SHIFT (6U)

◆ SDL_STC_CODEC_SPREAD_MODE_ENABLE

#define SDL_STC_CODEC_SPREAD_MODE_ENABLE (0x1U)

◆ SDL_STC_CODEC_SPREAD_MODE_DISABLE

#define SDL_STC_CODEC_SPREAD_MODE_DISABLE (0x0U)

◆ SDL_STC_LP_SCAN_MODE_MASK

#define SDL_STC_LP_SCAN_MODE_MASK (0x00000020U)

◆ SDL_STC_LP_SCAN_MODE_SHIFT

#define SDL_STC_LP_SCAN_MODE_SHIFT (5U)

◆ SDL_STC_LP_SCAN_MODE_ENABLE

#define SDL_STC_LP_SCAN_MODE_ENABLE (0x1U)

◆ SDL_STC_LP_SCAN_MODE_DISABLE

#define SDL_STC_LP_SCAN_MODE_DISABLE (0x0U)

◆ SDL_STC_ROM_ACCESS_INV_MASK

#define SDL_STC_ROM_ACCESS_INV_MASK (0x00000010U)

◆ SDL_STC_ROM_ACCESS_INV_SHIFT

#define SDL_STC_ROM_ACCESS_INV_SHIFT (4U)

◆ SDL_STC_ROM_ACCESS_INV_DISABLE

#define SDL_STC_ROM_ACCESS_INV_DISABLE (0x0U)

◆ SDL_STC_ST_ENA_B4_MASK

#define SDL_STC_ST_ENA_B4_MASK (0x0000000FU)

◆ SDL_STC_ST_ENA_B4_SHIFT

#define SDL_STC_ST_ENA_B4_SHIFT (0x00000000U)

◆ SDL_STC_ST_ENA_B4_ENABLE

#define SDL_STC_ST_ENA_B4_ENABLE (0xAU)

◆ SDL_STC_TO_PRELOAD_MASK

#define SDL_STC_TO_PRELOAD_MASK (0xFFFFFFFFU)

◆ SDL_STC_TO_PRELOAD_SHIFT

#define SDL_STC_TO_PRELOAD_SHIFT (0x00000000U)

◆ SDL_STC_TO_PRELOAD_MAX

#define SDL_STC_TO_PRELOAD_MAX (0xFFFFFFFFU)

◆ SDL_STC_ADDR1_MASK

#define SDL_STC_ADDR1_MASK (0xFFFFFFFFU)

◆ SDL_STC_ADDR1_SHIFT

#define SDL_STC_ADDR1_SHIFT (0x00000000U)

◆ SDL_STC_CORE2_ICOUNT_MASK

#define SDL_STC_CORE2_ICOUNT_MASK (0xFFFF0000U)

◆ SDL_STC_CORE2_ICOUNT_SHIFT

#define SDL_STC_CORE2_ICOUNT_SHIFT (16U)

◆ SDL_STC_CORE1_ICOUNT_MASK

#define SDL_STC_CORE1_ICOUNT_MASK (0x0000FFFFU)

◆ SDL_STC_CORE1_ICOUNT_SHIFT

#define SDL_STC_CORE1_ICOUNT_SHIFT (0x00000000U)

◆ SDL_STC_ST_ACTIVE_MASK

#define SDL_STC_ST_ACTIVE_MASK (0x00000F00U)

◆ SDL_STC_ST_ACTIVE_SHIFT

#define SDL_STC_ST_ACTIVE_SHIFT (8U)

◆ SDL_STC_ST_ACTIVE_ENABLE

#define SDL_STC_ST_ACTIVE_ENABLE (0xAU)

◆ SDL_STC_TEST_FAIL_MASK

#define SDL_STC_TEST_FAIL_MASK (0x00000002U)

◆ SDL_STC_TEST_FAIL_SHIFT

#define SDL_STC_TEST_FAIL_SHIFT (1U)

◆ SDL_STC_TEST_FAIL_ENABLE

#define SDL_STC_TEST_FAIL_ENABLE (0x1U)

◆ SDL_STC_TEST_FAIL_DISABLE

#define SDL_STC_TEST_FAIL_DISABLE (0x0U)

◆ SDL_STC_TEST_DONE_MASK

#define SDL_STC_TEST_DONE_MASK (0x00000001U)

◆ SDL_STC_TEST_DONE_SHIFT

#define SDL_STC_TEST_DONE_SHIFT (0U)

◆ SDL_STC_TEST_DONE_ENABLE

#define SDL_STC_TEST_DONE_ENABLE (0x1U)

◆ SDL_STC_TEST_DONE_DISABLE

#define SDL_STC_TEST_DONE_DISABLE (0x0U)

◆ SDL_STC_FSEG_ID_MASK

#define SDL_STC_FSEG_ID_MASK (0x00000018U)

◆ SDL_STC_FSEG_ID_SHIFT

#define SDL_STC_FSEG_ID_SHIFT (3U)

◆ SDL_STC_TO_ER_B1_MASK

#define SDL_STC_TO_ER_B1_MASK (0x00000004U)

◆ SDL_STC_TO_ER_B1_SHIFT

#define SDL_STC_TO_ER_B1_SHIFT (2U)

◆ SDL_STC_TO_ER_B1_ENABLE

#define SDL_STC_TO_ER_B1_ENABLE (0x1U)

◆ SDL_STC_TO_ER_B1_DISABLE

#define SDL_STC_TO_ER_B1_DISABLE (0x0U)

◆ SDL_STC_CPU2_FAIL_B1_MASK

#define SDL_STC_CPU2_FAIL_B1_MASK (0x00000002U)

◆ SDL_STC_CPU2_FAIL_B1_SHIFT

#define SDL_STC_CPU2_FAIL_B1_SHIFT (0x1U)

◆ SDL_STC_CPU2_FAIL_B1_ENABLE

#define SDL_STC_CPU2_FAIL_B1_ENABLE (0x1U)

◆ SDL_STC_CPU2_FAIL_B1_DISABLE

#define SDL_STC_CPU2_FAIL_B1_DISABLE (0x0U)

◆ SDL_STC_CPU1_FAIL_B1_MASK

#define SDL_STC_CPU1_FAIL_B1_MASK (0x00000001U)

◆ SDL_STC_CPU1_FAIL_B1_SHIFT

#define SDL_STC_CPU1_FAIL_B1_SHIFT (0U)

◆ SDL_STC_CPU1_FAIL_B1_ENABLE

#define SDL_STC_CPU1_FAIL_B1_ENABLE (0x1U)

◆ SDL_STC_CPU1_FAIL_B1_DISABLE

#define SDL_STC_CPU1_FAIL_B1_DISABLE (0x0U)

◆ SDL_STC_FAULT_INS_B1_MASK

#define SDL_STC_FAULT_INS_B1_MASK (0x00000010U)

◆ SDL_STC_FAULT_INS_B1_SHIFT

#define SDL_STC_FAULT_INS_B1_SHIFT (4U)

◆ SDL_STC_FAULT_INS_B1_ENABLE

#define SDL_STC_FAULT_INS_B1_ENABLE (0x1U)

◆ SDL_STC_FAULT_INS_B1_DISABLE

#define SDL_STC_FAULT_INS_B1_DISABLE (0x0U)

◆ SDL_STC_SELF_CHECK_KEY_B4_MASK

#define SDL_STC_SELF_CHECK_KEY_B4_MASK (0x0000000FU)

◆ SDL_STC_SELF_CHECK_KEY_B4_SHIFT

#define SDL_STC_SELF_CHECK_KEY_B4_SHIFT (0U)

◆ SDL_STC_SELF_CHECK_KEY_B4_ENABLE

#define SDL_STC_SELF_CHECK_KEY_B4_ENABLE (0xAU)

◆ SDL_STC_SELF_CHECK_KEY_B4_DISABLE

#define SDL_STC_SELF_CHECK_KEY_B4_DISABLE (0U)

◆ SDL_STC_ADDR2_MASK

#define SDL_STC_ADDR2_MASK (0xFFFFFFFFU)

◆ SDL_STC_ADDR2_SHIFT

#define SDL_STC_ADDR2_SHIFT (0x00000000U)

◆ SDL_STC_CLKDIV0_MASK

#define SDL_STC_CLKDIV0_MASK (0x07000000U)

◆ SDL_STC_CLKDIV0_SHIFT

#define SDL_STC_CLKDIV0_SHIFT (24U)

◆ SDL_STC_CLKDIV1_MASK

#define SDL_STC_CLKDIV1_MASK (0x00070000U)

◆ SDL_STC_CLKDIV1_SHIFT

#define SDL_STC_CLKDIV1_SHIFT (16U)

◆ SDL_STC_CLKDIV2_MASK

#define SDL_STC_CLKDIV2_MASK (0x00000700U)

◆ SDL_STC_CLKDIV2_SHIFT

#define SDL_STC_CLKDIV2_SHIFT (8U)

◆ SDL_STC_CLKDIV3_MASK

#define SDL_STC_CLKDIV3_MASK (0x00000007U)

◆ SDL_STC_CLKDIV3_SHIFT

#define SDL_STC_CLKDIV3_SHIFT (0U)

◆ SDL_STC_SEGPLR_MASK

#define SDL_STC_SEGPLR_MASK (0x00000003U)

◆ SDL_STC_SEGPLR_SHIFT

#define SDL_STC_SEGPLR_SHIFT (0U)

◆ SDL_STC_SEG0_START_ADDR_MASK

#define SDL_STC_SEG0_START_ADDR_MASK (0x000FFFFFU)

◆ SDL_STC_SEG0_START_ADDR_SHIFT

#define SDL_STC_SEG0_START_ADDR_SHIFT (0U)

◆ SDL_STC_SEG1_START_ADDR0_MASK

#define SDL_STC_SEG1_START_ADDR0_MASK (0x000FFFFFU)

◆ SDL_STC_SEG1_START_ADDR0_SHIFT

#define SDL_STC_SEG1_START_ADDR0_SHIFT (0U)

◆ SDL_STC_SEG2_START_ADDR0_MASK

#define SDL_STC_SEG2_START_ADDR0_MASK (0x000FFFFFU)

◆ SDL_STC_SEG2_START_ADDR0_SHIFT

#define SDL_STC_SEG2_START_ADDR0_SHIFT (0U)

◆ SDL_STC_SEG3_START_ADDR0_MASK

#define SDL_STC_SEG3_START_ADDR0_MASK (0x000FFFFFU)

◆ SDL_STC_SEG3_START_ADDR0_SHIFT

#define SDL_STC_SEG3_START_ADDR0_SHIFT (0U)

◆ SDL_MSS_STC_RESET_MASK

#define SDL_MSS_STC_RESET_MASK (0x00000004U)

◆ SDL_MSS_STC_RESET_SHIFT

#define SDL_MSS_STC_RESET_SHIFT (2U)

◆ SDL_MSS_STC_RESET_CLEAR_MASK

#define SDL_MSS_STC_RESET_CLEAR_MASK (0x00000007)

◆ SDL_MSS_STC_RESET_CLEAR_SHIFT

#define SDL_MSS_STC_RESET_CLEAR_SHIFT (0U)

◆ SDL_MSS_STC_RESET_CLEAR_ENABLE

#define SDL_MSS_STC_RESET_CLEAR_ENABLE (0x7U)

◆ SDL_DSS_STC_RESET_MASK

#define SDL_DSS_STC_RESET_MASK (0x00000020U)

◆ SDL_DSS_STC_RESET_SHIFT

#define SDL_DSS_STC_RESET_SHIFT (5U)