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AM263x MCU+ SDK
08.05.00
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66 #include <sdl/include/hw_types.h>
67 #include <sdl/include/sdl_types.h>
69 #include <sdl/stc/v0/soc/sdl_soc_stc.h>
108 #define STC_MSS_INTERVAL_NUM (uint32_t)(1U)
109 #define STC_MSS_LP_SCAN_MODE (uint32_t)(0U)
110 #define STC_MSS_CODEC_SPREAD_MODE (uint32_t)(1U)
111 #define STC_MSS_CAP_IDLE_CYCLE (uint32_t)(3U)
112 #define STC_MSS_SCANEN_HIGH_CAP_IDLE_CYCLE (uint32_t)(3U)
113 #define STC_MSS_MAX_RUN_TIME (uint32_t)(0xFFFFFFFFU)
114 #define STC_MSS_CLK_DIV (uint32_t)(1U)
115 #define STC_ROM_START_ADDRESS (uint32_t)(0U)
116 #define STC_pROM_START_ADDRESS (uint32_t)(1U)
123 #define STC_DSS_INTERVAL_NUM (uint32_t)(2U)
124 #define STC_DSS_LP_SCAN_MODE (uint32_t)(0U)
125 #define STC_DSS_CODEC_SPREAD_MODE (uint32_t)(1U)
126 #define STC_DSS_CAP_IDLE_CYCLE (uint32_t)(3U)
127 #define STC_DSS_SCANEN_HIGH_CAP_IDLE_CYCLE (uint32_t)(3U)
128 #define STC_DSS_MAX_RUN_TIME (uint32_t)(0x13332U)
129 #define STC_DSS_CLK_DIV (uint32_t)(1U)
130 #define STC_ROM_START_ADDRESS (uint32_t)(0U)
131 #define STC_pROM_START_ADDRESS (uint32_t)(1U)
164 SDL_STC_ScanModeconfig;
405 #define SDL_STC_STCGCR0 (0x00000000U)
406 #define SDL_STC_STCGCR1 (0x00000004U)
407 #define SDL_STC_STCTPR (0x00000008U)
408 #define SDL_STC_CADDR (0x0000000CU)
409 #define SDL_STC_STCCICR (0x00000010U)
410 #define SDL_STC_STCGSTAT (0x00000014U)
411 #define SDL_STC_STCFSTAT (0x00000018U)
412 #define SDL_STC_STCSCSCR (0x0000001CU)
413 #define SDL_STC_CADDR2 (0x00000020U)
414 #define SDL_STC_CLKDIV (0x00000024U)
415 #define SDL_STC_SEGPLR (0x00000028U)
416 #define SDL_STC_SEG0_START_ADDR (0x0000002CU)
417 #define SDL_STC_SEG1_START_ADDR (0x00000030U)
418 #define SDL_STC_SEG2_START_ADDR (0x00000034U)
419 #define SDL_STC_SEG3_START_ADDR (0x00000038U)
429 #define SDL_STC_STCGCR0_INTCOUNT_B16_MASK (0xFFFF0000U)
430 #define SDL_STC_STCGCR0_INTCOUNT_B16_SHIFT (16U)
431 #define SDL_STC_STCGCR0_INTCOUNT_B16_MAX (0xFFFF0000U)
433 #define SDL_STC_STCGCR0_CAP_IDLE_CYCLE_MASK (0x00000700U)
434 #define SDL_STC_STCGCR0_CAP_IDLE_CYCLE_SHIFT (8U)
435 #define SDL_STC_STCGCR0_CAP_IDLE_CYCLE_MAX (0x00000700U)
437 #define SDL_STC_STCGCR0_SCANEN_HIGH_CAP_IDLE_CYCLE_MASK (0x000000E0U)
438 #define SDL_STC_STCGCR0_SCANEN_HIGH_CAP_IDLE_CYCLE_SHIFT (5U)
439 #define SDL_STC_STCGCR0_SCANEN_HIGH_CAP_IDLE_CYCLE_MAX (0x000000E0U)
441 #define SDL_STC_STCGCR0_RS_CNT_B1_MASK (0x00000003U)
442 #define SDL_STC_STCGCR0_RS_CNT_B1_SHIFT (0U)
447 #define SDL_STC_SEG0_CORE_SEL_MASK (0x00000F00U)
448 #define SDL_STC_SEG0_CORE_SEL_SHIFT (8U)
449 #define SDL_STC_SEG0_CORE_SEL_ENABLE (0x1U)
452 #define SDL_STC_CODEC_SPREAD_MODE_MASK (0x00000040U)
453 #define SDL_STC_CODEC_SPREAD_MODE_SHIFT (6U)
454 #define SDL_STC_CODEC_SPREAD_MODE_ENABLE (0x1U)
455 #define SDL_STC_CODEC_SPREAD_MODE_DISABLE (0x0U)
457 #define SDL_STC_LP_SCAN_MODE_MASK (0x00000020U)
458 #define SDL_STC_LP_SCAN_MODE_SHIFT (5U)
459 #define SDL_STC_LP_SCAN_MODE_ENABLE (0x1U)
460 #define SDL_STC_LP_SCAN_MODE_DISABLE (0x0U)
463 #define SDL_STC_ROM_ACCESS_INV_MASK (0x00000010U)
464 #define SDL_STC_ROM_ACCESS_INV_SHIFT (4U)
465 #define SDL_STC_ROM_ACCESS_INV_DISABLE (0x0U)
467 #define SDL_STC_ST_ENA_B4_MASK (0x0000000FU)
468 #define SDL_STC_ST_ENA_B4_SHIFT (0x00000000U)
469 #define SDL_STC_ST_ENA_B4_ENABLE (0xAU)
475 #define SDL_STC_TO_PRELOAD_MASK (0xFFFFFFFFU)
476 #define SDL_STC_TO_PRELOAD_SHIFT (0x00000000U)
477 #define SDL_STC_TO_PRELOAD_MAX (0xFFFFFFFFU)
481 #define SDL_STC_ADDR1_MASK (0xFFFFFFFFU)
482 #define SDL_STC_ADDR1_SHIFT (0x00000000U)
487 #define SDL_STC_CORE2_ICOUNT_MASK (0xFFFF0000U)
488 #define SDL_STC_CORE2_ICOUNT_SHIFT (16U)
490 #define SDL_STC_CORE1_ICOUNT_MASK (0x0000FFFFU)
491 #define SDL_STC_CORE1_ICOUNT_SHIFT (0x00000000U)
496 #define SDL_STC_ST_ACTIVE_MASK (0x00000F00U)
497 #define SDL_STC_ST_ACTIVE_SHIFT (8U)
498 #define SDL_STC_ST_ACTIVE_ENABLE (0xAU)
501 #define SDL_STC_TEST_FAIL_MASK (0x00000002U)
502 #define SDL_STC_TEST_FAIL_SHIFT (1U)
503 #define SDL_STC_TEST_FAIL_ENABLE (0x1U)
504 #define SDL_STC_TEST_FAIL_DISABLE (0x0U)
506 #define SDL_STC_TEST_DONE_MASK (0x00000001U)
507 #define SDL_STC_TEST_DONE_SHIFT (0U)
508 #define SDL_STC_TEST_DONE_ENABLE (0x1U)
509 #define SDL_STC_TEST_DONE_DISABLE (0x0U)
513 #define SDL_STC_FSEG_ID_MASK (0x00000018U)
514 #define SDL_STC_FSEG_ID_SHIFT (3U)
517 #define SDL_STC_TO_ER_B1_MASK (0x00000004U)
518 #define SDL_STC_TO_ER_B1_SHIFT (2U)
519 #define SDL_STC_TO_ER_B1_ENABLE (0x1U)
520 #define SDL_STC_TO_ER_B1_DISABLE (0x0U)
522 #define SDL_STC_CPU2_FAIL_B1_MASK (0x00000002U)
523 #define SDL_STC_CPU2_FAIL_B1_SHIFT (0x1U)
524 #define SDL_STC_CPU2_FAIL_B1_ENABLE (0x1U)
525 #define SDL_STC_CPU2_FAIL_B1_DISABLE (0x0U)
527 #define SDL_STC_CPU1_FAIL_B1_MASK (0x00000001U)
528 #define SDL_STC_CPU1_FAIL_B1_SHIFT (0U)
529 #define SDL_STC_CPU1_FAIL_B1_ENABLE (0x1U)
530 #define SDL_STC_CPU1_FAIL_B1_DISABLE (0x0U)
534 #define SDL_STC_FAULT_INS_B1_MASK (0x00000010U)
535 #define SDL_STC_FAULT_INS_B1_SHIFT (4U)
536 #define SDL_STC_FAULT_INS_B1_ENABLE (0x1U)
537 #define SDL_STC_FAULT_INS_B1_DISABLE (0x0U)
540 #define SDL_STC_SELF_CHECK_KEY_B4_MASK (0x0000000FU)
541 #define SDL_STC_SELF_CHECK_KEY_B4_SHIFT (0U)
542 #define SDL_STC_SELF_CHECK_KEY_B4_ENABLE (0xAU)
543 #define SDL_STC_SELF_CHECK_KEY_B4_DISABLE (0U)
549 #define SDL_STC_ADDR2_MASK (0xFFFFFFFFU)
550 #define SDL_STC_ADDR2_SHIFT (0x00000000U)
554 #define SDL_STC_CLKDIV0_MASK (0x07000000U)
555 #define SDL_STC_CLKDIV0_SHIFT (24U)
556 #define SDL_STC_CLKDIV1_MASK (0x00070000U)
557 #define SDL_STC_CLKDIV1_SHIFT (16U)
558 #define SDL_STC_CLKDIV2_MASK (0x00000700U)
559 #define SDL_STC_CLKDIV2_SHIFT (8U)
560 #define SDL_STC_CLKDIV3_MASK (0x00000007U)
561 #define SDL_STC_CLKDIV3_SHIFT (0U)
565 #define SDL_STC_SEGPLR_MASK (0x00000003U)
566 #define SDL_STC_SEGPLR_SHIFT (0U)
570 #define SDL_STC_SEG0_START_ADDR_MASK (0x000FFFFFU)
571 #define SDL_STC_SEG0_START_ADDR_SHIFT (0U)
575 #define SDL_STC_SEG1_START_ADDR0_MASK (0x000FFFFFU)
576 #define SDL_STC_SEG1_START_ADDR0_SHIFT (0U)
580 #define SDL_STC_SEG2_START_ADDR0_MASK (0x000FFFFFU)
581 #define SDL_STC_SEG2_START_ADDR0_SHIFT (0U)
585 #define SDL_STC_SEG3_START_ADDR0_MASK (0x000FFFFFU)
586 #define SDL_STC_SEG3_START_ADDR0_SHIFT (0U)
589 #define SDL_MSS_STC_RESET_MASK (0x00000004U)
590 #define SDL_MSS_STC_RESET_SHIFT (2U)
592 #define SDL_MSS_STC_RESET_CLEAR_MASK (0x00000007)
593 #define SDL_MSS_STC_RESET_CLEAR_SHIFT (0U)
594 #define SDL_MSS_STC_RESET_CLEAR_ENABLE (0x7U)
597 #define SDL_DSS_STC_RESET_MASK (0x00000020U)
598 #define SDL_DSS_STC_RESET_SHIFT (5U)
@ SDL_STC_COMPLETED_FAILURE
Definition: stc/v0/sdl_stc.h:201
volatile uint32_t CORE1_CURMISR_8
Definition: stc/v0/sdl_stc.h:357
volatile uint32_t STCSCSCR
Definition: stc/v0/sdl_stc.h:323
uint32_t maxRunTime
Definition: stc/v0/sdl_stc.h:171
@ SDL_STC_COMPLETED_SUCCESS
Definition: stc/v0/sdl_stc.h:199
volatile uint32_t CORE1_CURMISR_24
Definition: stc/v0/sdl_stc.h:389
volatile uint32_t CORE1_CURMISR_13
Definition: stc/v0/sdl_stc.h:367
volatile uint32_t CORE1_CURMISR_4
Definition: stc/v0/sdl_stc.h:349
int32_t SDL_STC_getStatus(SDL_STC_Inst instance)
This API is used to get status for STC result.
uint32_t intervalNum
Definition: stc/v0/sdl_stc.h:169
@ SDL_STC_NOT_RUN
Definition: stc/v0/sdl_stc.h:205
uint32_t stcDiagnostic
Definition: stc/v0/sdl_stc.h:181
volatile uint32_t CORE1_CURMISR_0
Definition: stc/v0/sdl_stc.h:341
volatile uint32_t CORE1_CURMISR_14
Definition: stc/v0/sdl_stc.h:369
volatile uint32_t CORE1_CURMISR_18
Definition: stc/v0/sdl_stc.h:377
uint32_t romStartAddress
Definition: stc/v0/sdl_stc.h:175
volatile uint32_t SEG0_START_ADDR
Definition: stc/v0/sdl_stc.h:331
union HsmVer_t_ __attribute__((packed)) HsmVer_t
type for reading HSMRt version.
volatile uint32_t CORE1_CURMISR_21
Definition: stc/v0/sdl_stc.h:383
volatile uint32_t CORE1_CURMISR_25
Definition: stc/v0/sdl_stc.h:391
volatile uint32_t STC_CADDR2
Definition: stc/v0/sdl_stc.h:325
volatile uint32_t CORE1_CURMISR_10
Definition: stc/v0/sdl_stc.h:361
volatile uint32_t CORE1_CURMISR_3
Definition: stc/v0/sdl_stc.h:347
volatile uint32_t CORE1_CURMISR_15
Definition: stc/v0/sdl_stc.h:371
SDL_STC_ScanModeconfig modeConfig
Definition: stc/v0/sdl_stc.h:183
volatile uint32_t CORE1_CURMISR_9
Definition: stc/v0/sdl_stc.h:359
volatile uint32_t CORE1_CURMISR_11
Definition: stc/v0/sdl_stc.h:363
SDL_STC_Inst
Definition: sdl_stc_soc.h:79
@ SDL_STC_NEG_TEST
Definition: stc/v0/sdl_stc.h:216
SDL_STC_TestResult
Definition: stc/v0/sdl_stc.h:197
uint32_t scanEnHighCap_idleCycle
Definition: stc/v0/sdl_stc.h:161
volatile uint32_t STCGSTAT
Definition: stc/v0/sdl_stc.h:319
volatile uint32_t CORE1_CURMISR_22
Definition: stc/v0/sdl_stc.h:385
volatile uint32_t CORE1_CURMISR_17
Definition: stc/v0/sdl_stc.h:375
uint32_t codecSpreadMode
Definition: stc/v0/sdl_stc.h:157
static int32_t SDL_STC_runTest(SDL_STC_Inst instance)
This API is used to enable the STC module.
volatile uint32_t CORE1_CURMISR_2
Definition: stc/v0/sdl_stc.h:345
volatile uint32_t CORE1_CURMISR_6
Definition: stc/v0/sdl_stc.h:353
volatile uint32_t CORE1_CURMISR_7
Definition: stc/v0/sdl_stc.h:355
uint32_t faultInsert
Definition: stc/v0/sdl_stc.h:179
volatile uint32_t CORE1_CURMISR_19
Definition: stc/v0/sdl_stc.h:379
uint32_t pRomStartAdd
Definition: stc/v0/sdl_stc.h:177
@ SDL_STC_NOT_COMPLETED
Definition: stc/v0/sdl_stc.h:203
volatile uint32_t CORE1_CURMISR_12
Definition: stc/v0/sdl_stc.h:365
volatile uint32_t STC_CLKDIV
Definition: stc/v0/sdl_stc.h:327
volatile uint32_t SEG1_START_ADDR
Definition: stc/v0/sdl_stc.h:333
int32_t SDL_STC_selfTest(SDL_STC_Inst instance, SDL_STC_TestType testType, SDL_STC_Config *pConfig)
This API is used to run the STC module.
static void SDL_STC_delay(int32_t count)
This API is used to provide delay for processor core.
@ INVALID_RESULT
Definition: stc/v0/sdl_stc.h:207
volatile uint32_t STCTPR
Definition: stc/v0/sdl_stc.h:313
uint32_t lpScanMode
Definition: stc/v0/sdl_stc.h:155
uint32_t clkDiv
Definition: stc/v0/sdl_stc.h:173
static int32_t SDL_STC_configure(SDL_STC_Inst instance, SDL_STC_Config *pConfig, SDL_STC_TestType testType)
This API is used to configure STC module.
@ SDL_STC_TEST
Definition: stc/v0/sdl_stc.h:214
uint32_t capIdleCycle
Definition: stc/v0/sdl_stc.h:159
volatile uint32_t CORE1_CURMISR_5
Definition: stc/v0/sdl_stc.h:351
volatile uint32_t STCGCR1
Definition: stc/v0/sdl_stc.h:311
volatile uint32_t STCCICR
Definition: stc/v0/sdl_stc.h:317
volatile uint32_t CORE1_CURMISR_20
Definition: stc/v0/sdl_stc.h:381
volatile uint32_t STCFSTAT
Definition: stc/v0/sdl_stc.h:321
This file contains the macro definations for Register layer.
Definition: stc/v0/sdl_stc.h:307
volatile uint32_t CORE1_CURMISR_26
Definition: stc/v0/sdl_stc.h:393
volatile uint32_t STC_CADDR
Definition: stc/v0/sdl_stc.h:315
volatile uint32_t SEG3_START_ADDR
Definition: stc/v0/sdl_stc.h:337
volatile uint32_t CORE1_CURMISR_1
Definition: stc/v0/sdl_stc.h:343
volatile uint32_t CORE1_CURMISR_23
Definition: stc/v0/sdl_stc.h:387
volatile uint32_t CORE1_CURMISR_27
Definition: stc/v0/sdl_stc.h:395
SDL_STC_TestType
Definition: stc/v0/sdl_stc.h:212
volatile uint32_t STC_SEGPLR
Definition: stc/v0/sdl_stc.h:329
volatile uint32_t STCGCR0
Definition: stc/v0/sdl_stc.h:309
volatile uint32_t SEG2_START_ADDR
Definition: stc/v0/sdl_stc.h:335
volatile uint32_t CORE1_CURMISR_16
Definition: stc/v0/sdl_stc.h:373