AM263x MCU+ SDK  08.03.00
sipc_notify_src.h File Reference

Go to the source code of this file.

Data Structures

struct  SIPC_InterruptConfig
 This structure describes the information related to one interrupt that is setup for receiving mailbox messages One interrupt can be used to handle messages from multiple cores. More...
 
struct  SIPC_MailboxConfig
 This structure describes the mailbox information to send a message from core A to core B. More...
 

Variables

SIPC_MailboxConfig gSIPC_R5MboxConfig [CORE_ID_MAX - 1]
 Global structure that is pre-defined for this SOC to configure any R5 CPU to HSM mailbox communication. More...
 
SIPC_MailboxConfig gSIPC_HsmMboxConfig [CORE_ID_MAX - 1]
 Global structure that is pre-defined for this SOC to configure any R5 CPU to HSM mailbox communication. More...
 
SIPC_SwQueuegSIPC_QueR5ToHsm [MAX_SEC_CORES_WITH_HSM - 1]
 Global structure holding R5 to HSM queues addresses indexed by sec core id. More...
 
SIPC_SwQueuegSIPC_QueHsmToR5 [MAX_SEC_CORES_WITH_HSM - 1]
 Global structure holding HSM -> R5 queues addresses indexed by sec core id. More...
 

Variable Documentation

◆ gSIPC_R5MboxConfig

SIPC_MailboxConfig gSIPC_R5MboxConfig[CORE_ID_MAX - 1]
extern

Global structure that is pre-defined for this SOC to configure any R5 CPU to HSM mailbox communication.

This is a pre-defined global since this config typically does not need to change based on end user use-cases for this SOC.

◆ gSIPC_HsmMboxConfig

SIPC_MailboxConfig gSIPC_HsmMboxConfig[CORE_ID_MAX - 1]
extern

Global structure that is pre-defined for this SOC to configure any R5 CPU to HSM mailbox communication.

This is a pre-defined global since this config typically does not need to change based on end user use-cases for this SOC.

◆ gSIPC_QueR5ToHsm

SIPC_SwQueue* gSIPC_QueR5ToHsm[MAX_SEC_CORES_WITH_HSM - 1]
extern

Global structure holding R5 to HSM queues addresses indexed by sec core id.

This is a pre-defined global since this config typically does not need to change based on end user use-cases for this SOC.

◆ gSIPC_QueHsmToR5

SIPC_SwQueue* gSIPC_QueHsmToR5[MAX_SEC_CORES_WITH_HSM - 1]
extern

Global structure holding HSM -> R5 queues addresses indexed by sec core id.

This is a pre-defined global since this config typically does not need to change based on end user use-cases for this SOC.