AM263x MCU+ SDK  08.03.00
sipc_notify_src.h
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32 
33 #ifndef SIPC_NOTIFY__H_
34 #define SIPC_NOTIFY__H_
35 
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39 
40 #include <drivers/sipc_notify.h>
41 #include <drivers/secure_ipc_notify/soc/sipc_notify_soc.h>
42 #include <kernel/dpl/HwiP.h>
43 #include <kernel/dpl/ClockP.h>
44 #include <kernel/dpl/CpuIdP.h>
46 
52 typedef struct SIPC_InterruptConfig_s
53 {
54  uint32_t intNum;
55  uint32_t eventId;
57  uint8_t numCores;
59  uint8_t coreIdList[MAX_SEC_CORES_WITH_HSM];
63  uint32_t clearIntOnInit; /* 0: do not clear pending interrupts during SIPC_init, 1: clear pending interrupts */
65 
69 typedef struct SIPC_MailboxConfig_s
70 {
73  uint8_t wrIntrBitPos;
74  uint8_t rdIntrBitPos;
78 
93 
108 
109 #ifdef __cplusplus
110 }
111 #endif
112 
113 #endif /* IPC_NOTIFY_V0_H_ */
114 
gSIPC_R5MboxConfig
SIPC_MailboxConfig gSIPC_R5MboxConfig[CORE_ID_MAX - 1]
Global structure that is pre-defined for this SOC to configure any R5 CPU to HSM mailbox communicatio...
SIPC_InterruptConfig
This structure describes the information related to one interrupt that is setup for receiving mailbox...
Definition: sipc_notify_src.h:53
SIPC_MailboxConfig::writeDoneMailboxBaseAddr
uint32_t writeDoneMailboxBaseAddr
Definition: sipc_notify_src.h:71
sipc_notify.h
CORE_ID_MAX
@ CORE_ID_MAX
Definition: sipc_notify_cfg.h:114
ClockP.h
SIPC_SwQueue
SIPC swQ structure which holds the data pointer to a fifo Queue in HSM MBOX memory.
Definition: sipc_notify_mailbox.h:63
HwiP.h
gSIPC_HsmMboxConfig
SIPC_MailboxConfig gSIPC_HsmMboxConfig[CORE_ID_MAX - 1]
Global structure that is pre-defined for this SOC to configure any R5 CPU to HSM mailbox communicatio...
SIPC_InterruptConfig::intNum
uint32_t intNum
Definition: sipc_notify_src.h:54
SIPC_InterruptConfig::clearIntOnInit
uint32_t clearIntOnInit
Definition: sipc_notify_src.h:63
SIPC_InterruptConfig::numCores
uint8_t numCores
Definition: sipc_notify_src.h:57
gSIPC_QueHsmToR5
SIPC_SwQueue * gSIPC_QueHsmToR5[MAX_SEC_CORES_WITH_HSM - 1]
Global structure holding HSM -> R5 queues addresses indexed by sec core id.
MAX_SEC_CORES_WITH_HSM
@ MAX_SEC_CORES_WITH_HSM
Definition: sipc_notify_cfg.h:128
SIPC_InterruptConfig::hwiObj
HwiP_Object hwiObj
Definition: sipc_notify_src.h:56
CpuIdP.h
SIPC_MailboxConfig::rdIntrBitPos
uint8_t rdIntrBitPos
Definition: sipc_notify_src.h:74
SIPC_MailboxConfig
This structure describes the mailbox information to send a message from core A to core B.
Definition: sipc_notify_src.h:70
gSIPC_QueR5ToHsm
SIPC_SwQueue * gSIPC_QueR5ToHsm[MAX_SEC_CORES_WITH_HSM - 1]
Global structure holding R5 to HSM queues addresses indexed by sec core id.
HwiP_Object
Opaque Hwi object used with the Hwi APIs.
Definition: HwiP.h:91
SIPC_MailboxConfig::swQ
SIPC_SwQueue * swQ
Definition: sipc_notify_src.h:75
SIPC_MailboxConfig::readReqMailboxBaseAddr
uint32_t readReqMailboxBaseAddr
Definition: sipc_notify_src.h:72
sipc_notify_mailbox.h
SIPC_MailboxConfig::wrIntrBitPos
uint8_t wrIntrBitPos
Definition: sipc_notify_src.h:73
SIPC_InterruptConfig::eventId
uint32_t eventId
Definition: sipc_notify_src.h:55