adc/v1/adc.h

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/*
 * Copyright (C) 2021 Texas Instruments Incorporated
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *   Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 *
 *   Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the
 *   distribution.
 *
 *   Neither the name of Texas Instruments Incorporated nor the names of
 *   its contributors may be used to endorse or promote products derived
 *   from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef ADC_V1_H_
#define ADC_V1_H_
 
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
 
//*****************************************************************************
//
//
//*****************************************************************************
#include <stdint.h>
#include <stdbool.h>
#include <drivers/hw_include/hw_types.h>
#include <drivers/hw_include/cslr_soc.h>
#include <kernel/dpl/DebugP.h>
#include <drivers/hw_include/cslr_adc.h>
 
//*****************************************************************************
//
// Values that can be passed to ADC_enablePPBEvent(), ADC_disablePPBEvent(),
// ADC_enablePPBEventInterrupt(), ADC_disablePPBEventInterrupt(), and
// ADC_clearPPBEventStatus() as the intFlags and evtFlags parameters. They also
// make up the enumerated bit field returned by ADC_getPPBEventStatus().
//
//*****************************************************************************
#define ADC_EVT_TRIPHI    (0x0001U) 
#define ADC_EVT_TRIPLO    (0x0002U) 
#define ADC_EVT_ZERO    (0x0004U) 
 
//*****************************************************************************
//
// Values that can be passed to ADC_forceMultipleSOC() as socMask parameter.
// These values can be OR'd together to trigger multiple SOCs at a time.
//
//*****************************************************************************
#define ADC_FORCE_SOC0    (0x0001U)  
#define ADC_FORCE_SOC1    (0x0002U)  
#define ADC_FORCE_SOC2    (0x0004U)  
#define ADC_FORCE_SOC3    (0x0008U)  
#define ADC_FORCE_SOC4    (0x0010U)  
#define ADC_FORCE_SOC5    (0x0020U)  
#define ADC_FORCE_SOC6    (0x0040U)  
#define ADC_FORCE_SOC7    (0x0080U)  
#define ADC_FORCE_SOC8    (0x0100U)  
#define ADC_FORCE_SOC9    (0x0200U)  
#define ADC_FORCE_SOC10    (0x0400U)  
#define ADC_FORCE_SOC11    (0x0800U)  
#define ADC_FORCE_SOC12    (0x1000U)  
#define ADC_FORCE_SOC13    (0x2000U)  
#define ADC_FORCE_SOC14    (0x4000U)  
#define ADC_FORCE_SOC15    (0x8000U)  
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    ADC_CLK_DIV_1_0 = 0,  
    ADC_CLK_DIV_2_0 = 2,  
    ADC_CLK_DIV_2_5 = 3,  
    ADC_CLK_DIV_3_0 = 4,  
    ADC_CLK_DIV_3_5 = 5,  
    ADC_CLK_DIV_4_0 = 6,  
    ADC_CLK_DIV_4_5 = 7,  
    ADC_CLK_DIV_5_0 = 8,  
    ADC_CLK_DIV_5_5 = 9,  
    ADC_CLK_DIV_6_0 = 10, 
    ADC_CLK_DIV_6_5 = 11,  
    ADC_CLK_DIV_7_0 = 12,  
    ADC_CLK_DIV_7_5 = 13,  
    ADC_CLK_DIV_8_0 = 14,  
    ADC_CLK_DIV_8_5 = 15   
} ADC_ClkPrescale;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    ADC_RESOLUTION_12BIT = 0  
} ADC_Resolution;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    ADC_MODE_SINGLE_ENDED = 0,  
    ADC_MODE_DIFFERENTIAL = 1   
} ADC_SignalMode;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    ADC_TRIGGER_SW_ONLY = 0x00,  
    ADC_TRIGGER_RTI0 = 0x01,  
    ADC_TRIGGER_RTI1 = 0x02,  
    ADC_TRIGGER_RTI2 = 0x03,  
    ADC_TRIGGER_RTI3 = 0x04,  
    ADC_TRIGGER_INPUT_XBAR_OUT5 = 0x05,  
    ADC_TRIGGER_EPWM0_SOCA = 0x08,  
    ADC_TRIGGER_EPWM0_SOCB = 0x09,  
    ADC_TRIGGER_EPWM1_SOCA = 0x0A,  
    ADC_TRIGGER_EPWM1_SOCB = 0x0B,  
    ADC_TRIGGER_EPWM2_SOCA = 0x0C,  
    ADC_TRIGGER_EPWM2_SOCB = 0x0D,  
    ADC_TRIGGER_EPWM3_SOCA = 0x0E,  
    ADC_TRIGGER_EPWM3_SOCB = 0x0F,  
    ADC_TRIGGER_EPWM4_SOCA = 0x10,  
    ADC_TRIGGER_EPWM4_SOCB = 0x11,  
    ADC_TRIGGER_EPWM5_SOCA = 0x12,  
    ADC_TRIGGER_EPWM5_SOCB = 0x13,  
    ADC_TRIGGER_EPWM6_SOCA = 0x14,  
    ADC_TRIGGER_EPWM6_SOCB = 0x15,  
    ADC_TRIGGER_EPWM7_SOCA = 0x16,  
    ADC_TRIGGER_EPWM7_SOCB = 0x17,  
    ADC_TRIGGER_EPWM8_SOCA = 0x18,  
    ADC_TRIGGER_EPWM8_SOCB = 0x19,  
    ADC_TRIGGER_EPWM9_SOCA = 0x1A,  
    ADC_TRIGGER_EPWM9_SOCB = 0x1B,  
    ADC_TRIGGER_EPWM10_SOCA = 0x1C,  
    ADC_TRIGGER_EPWM10_SOCB = 0x1D,  
    ADC_TRIGGER_EPWM11_SOCA = 0x1E,  
    ADC_TRIGGER_EPWM11_SOCB = 0x1F,  
    ADC_TRIGGER_EPWM12_SOCA = 0x20,  
    ADC_TRIGGER_EPWM12_SOCB = 0x21,  
    ADC_TRIGGER_EPWM13_SOCA = 0x22,  
    ADC_TRIGGER_EPWM13_SOCB = 0x23,  
    ADC_TRIGGER_EPWM14_SOCA = 0x24,  
    ADC_TRIGGER_EPWM14_SOCB = 0x25,  
    ADC_TRIGGER_EPWM15_SOCA = 0x26,  
    ADC_TRIGGER_EPWM15_SOCB = 0x27,  
    ADC_TRIGGER_EPWM16_SOCA = 0x28,  
    ADC_TRIGGER_EPWM16_SOCB = 0x29,  
    ADC_TRIGGER_EPWM17_SOCA = 0x2A,  
    ADC_TRIGGER_EPWM17_SOCB = 0x2B,  
    ADC_TRIGGER_EPWM18_SOCA = 0x2C,  
    ADC_TRIGGER_EPWM18_SOCB = 0x2D,  
    ADC_TRIGGER_EPWM19_SOCA = 0x2E,  
    ADC_TRIGGER_EPWM19_SOCB = 0x2F,  
    ADC_TRIGGER_EPWM20_SOCA = 0x30,  
    ADC_TRIGGER_EPWM20_SOCB = 0x31,  
    ADC_TRIGGER_EPWM21_SOCA = 0x32,  
    ADC_TRIGGER_EPWM21_SOCB = 0x33,  
    ADC_TRIGGER_EPWM22_SOCA = 0x34,  
    ADC_TRIGGER_EPWM22_SOCB = 0x35,  
    ADC_TRIGGER_EPWM23_SOCA = 0x36,  
    ADC_TRIGGER_EPWM23_SOCB = 0x37,  
    ADC_TRIGGER_EPWM24_SOCA = 0x38,  
    ADC_TRIGGER_EPWM24_SOCB = 0x39,  
    ADC_TRIGGER_EPWM25_SOCA = 0x3A,  
    ADC_TRIGGER_EPWM25_SOCB = 0x3B,  
    ADC_TRIGGER_EPWM26_SOCA = 0x3C,  
    ADC_TRIGGER_EPWM26_SOCB = 0x3D,  
    ADC_TRIGGER_EPWM27_SOCA = 0x3E,  
    ADC_TRIGGER_EPWM27_SOCB = 0x3F,  
    ADC_TRIGGER_EPWM28_SOCA = 0x40,  
    ADC_TRIGGER_EPWM28_SOCB = 0x41,  
    ADC_TRIGGER_EPWM29_SOCA = 0x42,  
    ADC_TRIGGER_EPWM29_SOCB = 0x43,  
    ADC_TRIGGER_EPWM30_SOCA = 0x44,  
    ADC_TRIGGER_EPWM30_SOCB = 0x45,  
    ADC_TRIGGER_EPWM31_SOCA = 0x46,  
    ADC_TRIGGER_EPWM31_SOCB = 0x47   
} ADC_Trigger;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    ADC_CH_ADCIN0 = 0,  
    ADC_CH_ADCIN1 = 1,  
    ADC_CH_ADCIN2 = 2,  
    ADC_CH_ADCIN3 = 3,  
    ADC_CH_ADCIN4 = 4,  
    ADC_CH_ADCIN5 = 5,  
    ADC_CH_CAL0 = 6, 
    ADC_CH_CAL1 = 7, 
    ADC_CH_ADCIN0_ADCIN1 = 0,  
    ADC_CH_ADCIN1_ADCIN0 = 1,  
    ADC_CH_ADCIN2_ADCIN3 = 2,  
    ADC_CH_ADCIN3_ADCIN2 = 3,  
    ADC_CH_ADCIN4_ADCIN5 = 4,  
    ADC_CH_ADCIN5_ADCIN4 = 5,  
    ADC_CH_CAL0_CAL1 = 6, 
} ADC_Channel;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    ADC_PULSE_END_OF_ACQ_WIN = 0,
    ADC_PULSE_END_OF_CONV = 1
} ADC_PulseMode;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    ADC_INT_NUMBER1 = 0,  
    ADC_INT_NUMBER2 = 1,  
    ADC_INT_NUMBER3 = 2,  
    ADC_INT_NUMBER4 = 3   
} ADC_IntNumber;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    ADC_PPB_NUMBER1 = 0,  
    ADC_PPB_NUMBER2 = 1,  
    ADC_PPB_NUMBER3 = 2,  
    ADC_PPB_NUMBER4 = 3   
} ADC_PPBNumber;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    ADC_SOC_NUMBER0 = 0,  
    ADC_SOC_NUMBER1 = 1,  
    ADC_SOC_NUMBER2 = 2,  
    ADC_SOC_NUMBER3 = 3,  
    ADC_SOC_NUMBER4 = 4,  
    ADC_SOC_NUMBER5 = 5,  
    ADC_SOC_NUMBER6 = 6,  
    ADC_SOC_NUMBER7 = 7,  
    ADC_SOC_NUMBER8 = 8,  
    ADC_SOC_NUMBER9 = 9,  
    ADC_SOC_NUMBER10 = 10,  
    ADC_SOC_NUMBER11 = 11,  
    ADC_SOC_NUMBER12 = 12,  
    ADC_SOC_NUMBER13 = 13,  
    ADC_SOC_NUMBER14 = 14,  
    ADC_SOC_NUMBER15 = 15   
} ADC_SOCNumber;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    ADC_INT_SOC_TRIGGER_NONE = 0,  
    ADC_INT_SOC_TRIGGER_ADCINT1 = 1,  
    ADC_INT_SOC_TRIGGER_ADCINT2 = 2   
} ADC_IntSOCTrigger;
 
//*****************************************************************************
//
//
//*****************************************************************************
typedef enum
{
    ADC_PRI_ALL_ROUND_ROBIN = 0,  
    ADC_PRI_SOC0_HIPRI = 1,  
    ADC_PRI_THRU_SOC1_HIPRI = 2,  
    ADC_PRI_THRU_SOC2_HIPRI = 3,  
    ADC_PRI_THRU_SOC3_HIPRI = 4,  
    ADC_PRI_THRU_SOC4_HIPRI = 5,  
    ADC_PRI_THRU_SOC5_HIPRI = 6,  
    ADC_PRI_THRU_SOC6_HIPRI = 7,  
    ADC_PRI_THRU_SOC7_HIPRI = 8,  
    ADC_PRI_THRU_SOC8_HIPRI = 9,  
    ADC_PRI_THRU_SOC9_HIPRI = 10,  
    ADC_PRI_THRU_SOC10_HIPRI = 11,  
    ADC_PRI_THRU_SOC11_HIPRI = 12,  
    ADC_PRI_THRU_SOC12_HIPRI = 13,  
    ADC_PRI_THRU_SOC13_HIPRI = 14,  
    ADC_PRI_THRU_SOC14_HIPRI = 15,  
    ADC_PRI_ALL_HIPRI = 16  
} ADC_PriorityMode;
 
//*****************************************************************************
//
//
//*****************************************************************************
#define ADC_ADCSOCxCTL_STEP (CSL_ADC_ADCSOC1CTL - CSL_ADC_ADCSOC0CTL)
#define ADC_ADCINTSELxNy_STEP (CSL_ADC_ADCINTSEL3N4 - CSL_ADC_ADCINTSEL1N2)
#define ADC_ADCPPBx_STEP (CSL_ADC_ADCPPB2CONFIG - CSL_ADC_ADCPPB1CONFIG)
#define ADC_ADCPPBTRIP_MASK ((uint32_t)CSL_ADC_ADCPPB1TRIPHI_LIMITHI_MASK \
                               | (uint32_t)CSL_ADC_ADCPPB1TRIPHI_HSIGN_MASK)
#define ADC_RESULT_ADCPPBxRESULT_STEP (CSL_ADC_RESULT_ADCPPB2RESULT -\
                                                CSL_ADC_RESULT_ADCPPB1RESULT)
#define ADC_RESULT_ADCRESULTx_STEP (CSL_ADC_RESULT_ADCRESULT1 - \
                                        CSL_ADC_RESULT_ADCRESULT0)
 
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
ADC_setPrescaler(uint32_t base, ADC_ClkPrescale clkPrescale)
{
    //
    // Set the configuration of the ADC module prescaler.
    //
    HW_WR_REG16(base + CSL_ADC_ADCCTL2,
        ((HW_RD_REG16(base + CSL_ADC_ADCCTL2) &
        ~CSL_ADC_ADCCTL2_PRESCALE_MASK) | (uint16_t)clkPrescale));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
ADC_setupSOC(uint32_t base, ADC_SOCNumber socNumber, ADC_Trigger trigger,
             ADC_Channel channel, uint32_t sampleWindow)
{
    uint32_t ctlRegAddr;
 
    //
    // Check the arguments.
    //
    DebugP_assert((sampleWindow >= 1U) && (sampleWindow <= 512U));
 
    //
    // Calculate address for the SOC control register.
    //
    ctlRegAddr = base + CSL_ADC_ADCSOC0CTL +
        ((uint32_t)socNumber * ADC_ADCSOCxCTL_STEP);
 
    //
    // Set the configuration of the specified SOC.
    //
    HW_WR_REG32(ctlRegAddr,
        (((uint32_t)channel << CSL_ADC_ADCSOC0CTL_CHSEL_SHIFT) |
        ((uint32_t)trigger << CSL_ADC_ADCSOC0CTL_TRIGSEL_SHIFT) |
        (sampleWindow - 1U)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
ADC_setInterruptSOCTrigger(uint32_t base, ADC_SOCNumber socNumber,
                           ADC_IntSOCTrigger trigger)
{
    uint16_t shiftVal;
 
    //
    // Each SOC has a 2-bit field in this register.
    //
    shiftVal = (uint16_t)socNumber << 1U;
 
    //
    // Set the configuration of the specified SOC. Note that we're treating
    // ADCINTSOCSEL1 and ADCINTSOCSEL2 as one 32-bit register here.
    //
    HW_WR_REG32(base + CSL_ADC_ADCINTSOCSEL1,
        ((HW_RD_REG32(base + CSL_ADC_ADCINTSOCSEL1) &
        ~((uint32_t)CSL_ADC_ADCINTSOCSEL1_SOC0_MASK << shiftVal)) |
        ((uint32_t)trigger << shiftVal)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
ADC_setInterruptPulseMode(uint32_t base, ADC_PulseMode pulseMode)
{
    //
    // Set the position of the pulse.
    //
    HW_WR_REG16(base + CSL_ADC_ADCCTL1,
        ((HW_RD_REG16(base + CSL_ADC_ADCCTL1) &
        ~CSL_ADC_ADCCTL1_INTPULSEPOS_MASK) |
        ((uint16_t)pulseMode<<CSL_ADC_ADCCTL1_INTPULSEPOS_SHIFT)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
ADC_setInterruptCycleOffset(uint32_t base, uint16_t cycleOffset)
{
    //
    // Set the position of the pulse.
    //
    HW_WR_REG16(base + CSL_ADC_ADCINTCYCLE, cycleOffset);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
ADC_enableConverter(uint32_t base)
{
    //
    // Set the bit that powers up the analog circuitry.
    //
    HW_WR_REG16(base + CSL_ADC_ADCCTL1,
        (HW_RD_REG16(base + CSL_ADC_ADCCTL1) | CSL_ADC_ADCCTL1_ADCPWDNZ_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
ADC_disableConverter(uint32_t base)
{
    //
    // Clear the bit that powers down the analog circuitry.
    //
    HW_WR_REG16(base + CSL_ADC_ADCCTL1,
        (HW_RD_REG16(base + CSL_ADC_ADCCTL1) &
        ~CSL_ADC_ADCCTL1_ADCPWDNZ_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
ADC_forceSOC(uint32_t base, ADC_SOCNumber socNumber)
{
    //
    // Write to the register that will force a 1 to the corresponding SOC flag
    //
    HW_WR_REG16(base + CSL_ADC_ADCSOCFRC1, (1U << (uint16_t)socNumber));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
ADC_forceMultipleSOC(uint32_t base, uint16_t socMask)
{
    //
    // Write to the register that will force a 1 to desired SOCs
    //
    HW_WR_REG16(base + CSL_ADC_ADCSOCFRC1, socMask);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline bool
ADC_getInterruptStatus(uint32_t base, ADC_IntNumber adcIntNum)
{
    //
    // Get the specified ADC interrupt status.
    //
    return((HW_RD_REG16(base + CSL_ADC_ADCINTFLG) &
        (1U << (uint16_t)adcIntNum)) != 0U);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
ADC_clearInterruptStatus(uint32_t base, ADC_IntNumber adcIntNum)
{
    //
    // Clear the specified interrupt.
    //
    HW_WR_REG16(base + CSL_ADC_ADCINTFLGCLR, (1U << (uint16_t)adcIntNum));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline bool
ADC_getInterruptOverflowStatus(uint32_t base, ADC_IntNumber adcIntNum)
{
    //
    // Get the specified ADC interrupt status.
    //
    return((HW_RD_REG16(base + CSL_ADC_ADCINTOVF) &
        (1U << (uint16_t)adcIntNum)) != 0U);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
ADC_clearInterruptOverflowStatus(uint32_t base, ADC_IntNumber adcIntNum)
{
    //
    // Clear the specified interrupt overflow bit.
    //
    HW_WR_REG16(base + CSL_ADC_ADCINTOVFCLR, (1U << (uint16_t)adcIntNum));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint16_t
ADC_readResult(uint32_t resultBase, ADC_SOCNumber socNumber)
{
    //
    // Return the ADC result for the selected SOC.
    //
    return(HW_RD_REG16(resultBase + CSL_ADC_RESULT_ADCRESULT0 +
        socNumber * ADC_RESULT_ADCRESULTx_STEP));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline bool
ADC_isBusy(uint32_t base)
{
    //
    // Determine if the ADC is busy.
    //
    return((HW_RD_REG16(base + CSL_ADC_ADCCTL1) &
        CSL_ADC_ADCCTL1_ADCBSY_MASK) != 0U);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
ADC_setBurstModeConfig(uint32_t base, ADC_Trigger trigger, uint16_t burstSize)
{
    uint16_t regValue;
 
    //
    // Check the arguments.
    //
    DebugP_assert((trigger & ~0x7FU) == 0U);
    DebugP_assert((burstSize >= 1U) && (burstSize <= 16U));
 
    //
    // Write the burst mode configuration to the register.
    //
    regValue = (uint16_t)trigger |
        ((burstSize - 1U) << CSL_ADC_ADCBURSTCTL_BURSTSIZE_SHIFT);
 
    HW_WR_REG16(base + CSL_ADC_ADCBURSTCTL,
        ((HW_RD_REG16(base + CSL_ADC_ADCBURSTCTL) &
        ~((uint16_t)CSL_ADC_ADCBURSTCTL_BURSTTRIGSEL_MASK |
        CSL_ADC_ADCBURSTCTL_BURSTSIZE_MASK)) | regValue));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
ADC_enableBurstMode(uint32_t base)
{
    //
    // Enable burst mode.
    //
    HW_WR_REG16(base + CSL_ADC_ADCBURSTCTL,
        (HW_RD_REG16(base + CSL_ADC_ADCBURSTCTL) |
        CSL_ADC_ADCBURSTCTL_BURSTEN_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
ADC_disableBurstMode(uint32_t base)
{
    //
    // Disable burst mode.
    //
    HW_WR_REG16(base + CSL_ADC_ADCBURSTCTL,
        (HW_RD_REG16(base + CSL_ADC_ADCBURSTCTL) &
        ~CSL_ADC_ADCBURSTCTL_BURSTEN_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
ADC_setSOCPriority(uint32_t base, ADC_PriorityMode priMode)
{
    //
    // Set SOC priority
    //
    HW_WR_REG16(base + CSL_ADC_ADCSOCPRICTL,
        ((HW_RD_REG16(base + CSL_ADC_ADCSOCPRICTL) &
        ~CSL_ADC_ADCSOCPRICTL_SOCPRIORITY_MASK) | (uint16_t)priMode));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
ADC_setupPPB(uint32_t base, ADC_PPBNumber ppbNumber, ADC_SOCNumber socNumber)
{
    uint32_t ppbOffset;
 
    //
    // Get the offset to the appropriate PPB configuration register.
    //
    ppbOffset = (ADC_ADCPPBx_STEP * (uint32_t)ppbNumber) +
        CSL_ADC_ADCPPB1CONFIG;
 
    //
    // Write the configuration to the register.
    //
    HW_WR_REG16(base + ppbOffset,
        ((HW_RD_REG16(base + ppbOffset) & ~CSL_ADC_ADCPPB1CONFIG_CONFIG_MASK) |
        ((uint16_t)socNumber & CSL_ADC_ADCPPB1CONFIG_CONFIG_MASK)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
ADC_enablePPBEvent(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t evtFlags)
{
    //
    // Check the arguments.
    //
    DebugP_assert((evtFlags & ~0x7U) == 0U);
 
    //
    // Enable the specified event.
    //
    HW_WR_REG16(base + CSL_ADC_ADCEVTSEL,
        (HW_RD_REG16(base + CSL_ADC_ADCEVTSEL) |
        (evtFlags << ((uint16_t)ppbNumber * 4U))));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
ADC_disablePPBEvent(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t evtFlags)
{
    //
    // Check the arguments.
    //
    DebugP_assert((evtFlags & ~0x7U) == 0U);
 
    //
    // Disable the specified event.
    //
    HW_WR_REG16(base + CSL_ADC_ADCEVTSEL,
        (HW_RD_REG16(base + CSL_ADC_ADCEVTSEL) &
        ~(evtFlags << ((uint16_t)ppbNumber * 4U))));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
ADC_enablePPBEventInterrupt(uint32_t base, ADC_PPBNumber ppbNumber,
                            uint16_t intFlags)
{
    //
    // Check the arguments.
    //
    DebugP_assert((intFlags & ~0x7U) == 0U);
 
    //
    // Enable the specified event interrupts.
    //
    HW_WR_REG16(base + CSL_ADC_ADCEVTINTSEL,
        (HW_RD_REG16(base + CSL_ADC_ADCEVTINTSEL) |
        (intFlags << ((uint16_t)ppbNumber * 4U))));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
ADC_disablePPBEventInterrupt(uint32_t base, ADC_PPBNumber ppbNumber,
                             uint16_t intFlags)
{
    //
    // Check the arguments.
    //
    DebugP_assert((intFlags & ~0x7U) == 0U);
 
    //
    // Disable the specified event interrupts.
    //
    HW_WR_REG16(base + CSL_ADC_ADCEVTINTSEL,
        (HW_RD_REG16(base + CSL_ADC_ADCEVTINTSEL) &
        ~(intFlags << ((uint16_t)ppbNumber * 4U))));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint16_t
ADC_getPPBEventStatus(uint32_t base, ADC_PPBNumber ppbNumber)
{
    //
    // Get the event status for the specified post-processing block.
    //
    return((HW_RD_REG16(base + CSL_ADC_ADCEVTSTAT) >>
        ((uint16_t)ppbNumber * 4U)) & 0x7U);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
ADC_clearPPBEventStatus(uint32_t base, ADC_PPBNumber ppbNumber,
                        uint16_t evtFlags)
{
    //
    // Check the arguments.
    //
    DebugP_assert((evtFlags & ~0x7U) == 0U);
 
    //
    // Clear the specified event interrupts.
    //
    HW_WR_REG16(base + CSL_ADC_ADCEVTCLR,
        (HW_RD_REG16(base + CSL_ADC_ADCEVTCLR) |
        evtFlags << ((uint16_t)ppbNumber * 4U)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline int32_t
ADC_readPPBResult(uint32_t resultBase, ADC_PPBNumber ppbNumber)
{
    //
    // Return the result of selected PPB.
    //
    return((int32_t)HW_RD_REG32(resultBase + CSL_ADC_RESULT_ADCPPB1RESULT +
           (ppbNumber * ADC_RESULT_ADCPPBxRESULT_STEP)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline uint16_t
ADC_getPPBDelayTimeStamp(uint32_t base, ADC_PPBNumber ppbNumber)
{
    uint32_t ppbOffset;
 
    //
    // Get the offset to the appropriate delay.
    //
    ppbOffset = (ADC_ADCPPBx_STEP * (uint32_t)ppbNumber) +
        CSL_ADC_ADCPPB1STAMP;
 
    //
    // Return the delay time stamp.
    //
    return(HW_RD_REG16(base + ppbOffset) & CSL_ADC_ADCPPB1STAMP_DLYSTAMP_MASK);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
ADC_setPPBCalibrationOffset(uint32_t base, ADC_PPBNumber ppbNumber,
                            int16_t offset)
{
    uint32_t ppbOffset;
 
    //
    // Get the offset to the appropriate offset register.
    //
    ppbOffset = (ADC_ADCPPBx_STEP * (uint32_t)ppbNumber) +
        CSL_ADC_ADCPPB1OFFCAL;
 
    //
    // Write the offset amount.
    //
    HW_WR_REG16(base + ppbOffset,
        ((HW_RD_REG16(base + ppbOffset) & ~CSL_ADC_ADCPPB1OFFCAL_OFFCAL_MASK) |
        ((uint16_t)offset & CSL_ADC_ADCPPB1OFFCAL_OFFCAL_MASK)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
ADC_setPPBReferenceOffset(uint32_t base, ADC_PPBNumber ppbNumber,
                          uint16_t offset)
{
    uint32_t ppbOffset;
 
    //
    // Get the offset to the appropriate offset register.
    //
    ppbOffset = (ADC_ADCPPBx_STEP * (uint32_t)ppbNumber) +
        CSL_ADC_ADCPPB1OFFREF;
 
    //
    // Write the offset amount.
    //
    HW_WR_REG16(base + ppbOffset, offset);
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
ADC_enablePPBTwosComplement(uint32_t base, ADC_PPBNumber ppbNumber)
{
    uint32_t ppbOffset;
 
    //
    // Get the offset to the appropriate PPB configuration register.
    //
    ppbOffset = (ADC_ADCPPBx_STEP * (uint32_t)ppbNumber) +
        CSL_ADC_ADCPPB1CONFIG;
 
    //
    // Enable the twos complement
    //
    HW_WR_REG16(base + ppbOffset,
        (HW_RD_REG16(base + ppbOffset) |
        CSL_ADC_ADCPPB1CONFIG_TWOSCOMPEN_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
ADC_disablePPBTwosComplement(uint32_t base, ADC_PPBNumber ppbNumber)
{
    uint32_t ppbOffset;
 
    //
    // Get the offset to the appropriate PPB configuration register.
    //
    ppbOffset = (ADC_ADCPPBx_STEP * (uint32_t)ppbNumber) +
        CSL_ADC_ADCPPB1CONFIG;
 
    //
    // Disable the twos complement
    //
    HW_WR_REG16(base + ppbOffset,
        (HW_RD_REG16(base + ppbOffset) &
        ~CSL_ADC_ADCPPB1CONFIG_TWOSCOMPEN_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
ADC_enablePPBEventCBCClear(uint32_t base, uint32_t ppbNumber)
{
    uint32_t ppbOffset;
 
    //
    // Get the offset to the appropriate PPB configuration register.
    //
    ppbOffset = (ADC_ADCPPBx_STEP * (uint32_t)ppbNumber) +
        CSL_ADC_ADCPPB1CONFIG;
 
    //
    // Set automatic cycle-by-cycle flag clear bit
    //
    HW_WR_REG16(base + ppbOffset,
        (HW_RD_REG16(base + ppbOffset) | CSL_ADC_ADCPPB1CONFIG_CBCEN_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
ADC_disablePPBEventCBCClear(uint32_t base, uint32_t ppbNumber)
{
    uint32_t ppbOffset;
 
    //
    // Get the offset to the appropriate PPB configuration register.
    //
    ppbOffset = (ADC_ADCPPBx_STEP * (uint32_t)ppbNumber) +
        CSL_ADC_ADCPPB1CONFIG;
 
    //
    // Clear automatic cycle-by-cycle flag clear bit
    //
    HW_WR_REG16(base + ppbOffset,
        (HW_RD_REG16(base + ppbOffset) & ~CSL_ADC_ADCPPB1CONFIG_CBCEN_MASK));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
ADC_enableInterrupt(uint32_t base, ADC_IntNumber adcIntNum)
{
    uint32_t intRegAddr;
    uint16_t shiftVal;
 
    //
    // Each INTSEL register manages two interrupts. If the interrupt number is
    // even, we'll be accessing the upper byte and will need to shift.
    //
    intRegAddr = base + CSL_ADC_ADCINTSEL1N2 +
        ((uint32_t)adcIntNum >> 1) * ADC_ADCINTSELxNy_STEP;
    shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U;
 
    //
    // Enable the specified ADC interrupt.
    //
    HW_WR_REG16(intRegAddr,
        HW_RD_REG16(intRegAddr) |
        (CSL_ADC_ADCINTSEL1N2_INT1E_MASK << shiftVal));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
ADC_disableInterrupt(uint32_t base, ADC_IntNumber adcIntNum)
{
    uint32_t intRegAddr;
    uint16_t shiftVal;
 
    //
    // Each INTSEL register manages two interrupts. If the interrupt number is
    // even, we'll be accessing the upper byte and will need to shift.
    //
    intRegAddr = base + CSL_ADC_ADCINTSEL1N2 +
        ((uint32_t)adcIntNum >> 1) * ADC_ADCINTSELxNy_STEP;
    shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U;
 
    //
    // Disable the specified ADC interrupt.
    //
    HW_WR_REG16(intRegAddr,
        HW_RD_REG16(intRegAddr) &
        ~(CSL_ADC_ADCINTSEL1N2_INT1E_MASK << shiftVal));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
ADC_setInterruptSource(uint32_t base, ADC_IntNumber adcIntNum,
                       ADC_SOCNumber socNumber)
{
    uint32_t intRegAddr;
    uint16_t shiftVal;
 
    //
    // Each INTSEL register manages two interrupts. If the interrupt number is
    // even, we'll be accessing the upper byte and will need to shift.
    //
    intRegAddr = base + CSL_ADC_ADCINTSEL1N2 +
        ((uint32_t)adcIntNum >> 1) * ADC_ADCINTSELxNy_STEP;
    shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U;
 
    //
    // Set the specified ADC interrupt source.
    //
    HW_WR_REG16(intRegAddr,
        ((HW_RD_REG16(intRegAddr) &
        ~(CSL_ADC_ADCINTSEL1N2_INT1SEL_MASK << shiftVal)) |
        ((uint16_t)socNumber << shiftVal)));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
ADC_enableContinuousMode(uint32_t base, ADC_IntNumber adcIntNum)
{
    uint32_t intRegAddr;
    uint16_t shiftVal;
 
    //
    // Each INTSEL register manages two interrupts. If the interrupt number is
    // even, we'll be accessing the upper byte and will need to shift.
    //
    intRegAddr = base + CSL_ADC_ADCINTSEL1N2 +
        ((uint32_t)adcIntNum >> 1) * ADC_ADCINTSELxNy_STEP;
    shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U;
 
    //
    // Enable continuous mode for the specified ADC interrupt.
    //
    HW_WR_REG16(intRegAddr,
        HW_RD_REG16(intRegAddr) |
        (CSL_ADC_ADCINTSEL1N2_INT1CONT_MASK << shiftVal));
}
 
//*****************************************************************************
//
//
//*****************************************************************************
static inline void
ADC_disableContinuousMode(uint32_t base, ADC_IntNumber adcIntNum)
{
    uint32_t intRegAddr;
    uint16_t shiftVal;
 
    //
    // Each INTSEL register manages two interrupts. If the interrupt number is
    // even, we'll be accessing the upper byte and will need to shift.
    //
    intRegAddr = base + CSL_ADC_ADCINTSEL1N2 +
        ((uint32_t)adcIntNum >> 1) * ADC_ADCINTSELxNy_STEP;
    shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U;
 
    //
    // Disable continuous mode for the specified ADC interrupt.
    //
    HW_WR_REG16(intRegAddr,
        HW_RD_REG16(intRegAddr) &
        ~(CSL_ADC_ADCINTSEL1N2_INT1CONT_MASK << shiftVal));
}
 
//
//
//*****************************************************************************
extern void
ADC_setMode(uint32_t base, ADC_Resolution resolution,
            ADC_SignalMode signalMode);
 
//*****************************************************************************
//
//
//*****************************************************************************
extern void
ADC_setPPBTripLimits(uint32_t base, ADC_PPBNumber ppbNumber,
                     int32_t tripHiLimit, int32_t tripLoLimit);
 
//*****************************************************************************
//
// Close the Doxygen group.
//
//*****************************************************************************
 
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
 
#endif // ADC_V1_H_