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AM263x MCU+ SDK
08.02.00
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Go to the documentation of this file.
61 #include <drivers/hw_include/csl_types.h>
62 #include <drivers/hw_include/cslr_mcspi.h>
63 #include <drivers/hw_include/cslr.h>
85 #define MCSPI_CHANNEL_0 (0U)
86 #define MCSPI_CHANNEL_1 (1U)
87 #define MCSPI_CHANNEL_2 (2U)
88 #define MCSPI_CHANNEL_3 (3U)
99 #define MCSPI_OPER_MODE_POLLED (0U)
100 #define MCSPI_OPER_MODE_INTERRUPT (1U)
101 #define MCSPI_OPER_MODE_DMA (2U)
105 #define MCSPI_MAX_NUM_CHANNELS (4U)
115 #define MCSPI_TRANSFER_COMPLETED (0U)
116 #define MCSPI_TRANSFER_STARTED (1U)
117 #define MCSPI_TRANSFER_CANCELLED (2U)
118 #define MCSPI_TRANSFER_FAILED (3U)
119 #define MCSPI_TRANSFER_CSN_DEASSERT (4U)
120 #define MCSPI_TRANSFER_TIMEOUT (5U)
142 #define MCSPI_TRANSFER_MODE_BLOCKING (0U)
147 #define MCSPI_TRANSFER_MODE_CALLBACK (1U)
166 #define MCSPI_MS_MODE_MASTER (CSL_MCSPI_MODULCTRL_MS_MASTER)
168 #define MCSPI_MS_MODE_SLAVE (CSL_MCSPI_MODULCTRL_MS_SLAVE)
185 #define MCSPI_FF_POL0_PHA0 (0U)
186 #define MCSPI_FF_POL0_PHA1 (1U)
187 #define MCSPI_FF_POL1_PHA0 (2U)
188 #define MCSPI_FF_POL1_PHA1 (3U)
200 #define MCSPI_CS_POL_HIGH (CSL_MCSPI_CH0CONF_EPOL_ACTIVEHIGH)
202 #define MCSPI_CS_POL_LOW (CSL_MCSPI_CH0CONF_EPOL_ACTIVELOW)
211 #define MCSPI_TR_MODE_TX_RX (CSL_MCSPI_CH0CONF_TRM_TRANSRECEI)
212 #define MCSPI_TR_MODE_RX_ONLY (CSL_MCSPI_CH0CONF_TRM_RECEIVONLY)
213 #define MCSPI_TR_MODE_TX_ONLY (CSL_MCSPI_CH0CONF_TRM_TRANSONLY)
223 #define MCSPI_IS_D0 (CSL_MCSPI_CH0CONF_IS_LINE0)
225 #define MCSPI_IS_D1 (CSL_MCSPI_CH0CONF_IS_LINE1)
235 #define MCSPI_DPE_ENABLE (CSL_MCSPI_CH0CONF_DPE0_ENABLED)
237 #define MCSPI_DPE_DISABLE (CSL_MCSPI_CH0CONF_DPE0_DISABLED)
246 #define MCSPI_SLV_CS_SELECT_0 (CSL_MCSPI_CH0CONF_SPIENSLV_SPIEN0)
247 #define MCSPI_SLV_CS_SELECT_1 (CSL_MCSPI_CH0CONF_SPIENSLV_SPIEN1)
248 #define MCSPI_SLV_CS_SELECT_2 (CSL_MCSPI_CH0CONF_SPIENSLV_SPIEN2)
249 #define MCSPI_SLV_CS_SELECT_3 (CSL_MCSPI_CH0CONF_SPIENSLV_SPIEN3)
259 #define MCSPI_SB_POL_HIGH (CSL_MCSPI_CH0CONF_SBPOL_HIGHLEVEL)
261 #define MCSPI_SB_POL_LOW (CSL_MCSPI_CH0CONF_SBPOL_LOWLEVEL)
273 #define MCSPI_TCS0_0_CLK (CSL_MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY)
275 #define MCSPI_TCS0_1_CLK (CSL_MCSPI_CH0CONF_TCS0_ONECYCLEDLY)
277 #define MCSPI_TCS0_2_CLK (CSL_MCSPI_CH0CONF_TCS0_TWOCYCLEDLY)
279 #define MCSPI_TCS0_3_CLK (CSL_MCSPI_CH0CONF_TCS0_THREECYCLEDLY)
292 #define MCSPI_CH_MODE_SINGLE (CSL_MCSPI_MODULCTRL_SINGLE_SINGLE)
294 #define MCSPI_CH_MODE_MULTI (CSL_MCSPI_MODULCTRL_SINGLE_MULTI)
307 #define MCSPI_PINMODE_3PIN (CSL_MCSPI_MODULCTRL_PIN34_3PINMODE)
308 #define MCSPI_PINMODE_4PIN (CSL_MCSPI_MODULCTRL_PIN34_4PINMODE)
320 #define MCSPI_INITDLY_0 (CSL_MCSPI_MODULCTRL_INITDLY_NODELAY)
322 #define MCSPI_INITDLY_4 (CSL_MCSPI_MODULCTRL_INITDLY_4CLKDLY)
324 #define MCSPI_INITDLY_8 (CSL_MCSPI_MODULCTRL_INITDLY_8CLKDLY)
326 #define MCSPI_INITDLY_16 (CSL_MCSPI_MODULCTRL_INITDLY_16CLKDLY)
328 #define MCSPI_INITDLY_32 (CSL_MCSPI_MODULCTRL_INITDLY_32CLKDLY)
816 #define MCSPI_FIFO_LENGTH (64U)
820 #define MCSPI_RX_FIFO_ENABLE ((uint32_t) CSL_MCSPI_CH0CONF_FFER_FFENABLED \
822 CSL_MCSPI_CH0CONF_FFER_SHIFT)
827 #define MCSPI_RX_FIFO_DISABLE ((uint32_t) CSL_MCSPI_CH0CONF_FFER_FFDISABLED \
828 << CSL_MCSPI_CH0CONF_FFER_SHIFT)
833 #define MCSPI_TX_FIFO_ENABLE ((uint32_t) CSL_MCSPI_CH0CONF_FFEW_FFENABLED \
834 << CSL_MCSPI_CH0CONF_FFEW_SHIFT)
839 #define MCSPI_TX_FIFO_DISABLE ((uint32_t) CSL_MCSPI_CH0CONF_FFEW_FFDISABLED \
840 << CSL_MCSPI_CH0CONF_FFEW_SHIFT)
845 #define MCSPI_REG_OFFSET (0x14U)
847 #define MCSPI_CHCONF(x) ((uint32_t) CSL_MCSPI_CH0CONF + \
848 (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
851 #define MCSPI_CHSTAT(x) ((uint32_t) CSL_MCSPI_CH0STAT + \
852 (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
855 #define MCSPI_CHCTRL(x) ((uint32_t) CSL_MCSPI_CH0CTRL + \
856 (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
859 #define MCSPI_CHTX(x) ((uint32_t) CSL_MCSPI_TX0 + \
860 (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
863 #define MCSPI_CHRX(x) ((uint32_t) CSL_MCSPI_RX0 + \
864 (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
867 #define MCSPI_CLKD_MASK (0x0FU)
870 #define MCSPI_IRQSTATUS_CLEAR_ALL (CSL_MCSPI_IRQSTATUS_EOW_MASK | \
871 CSL_MCSPI_IRQSTATUS_WKS_MASK | \
872 CSL_MCSPI_IRQSTATUS_RX3_FULL_MASK | \
873 CSL_MCSPI_IRQSTATUS_TX3_UNDERFLOW_MASK | \
874 CSL_MCSPI_IRQSTATUS_TX3_EMPTY_MASK | \
875 CSL_MCSPI_IRQSTATUS_RX2_FULL_MASK | \
876 CSL_MCSPI_IRQSTATUS_TX2_UNDERFLOW_MASK | \
877 CSL_MCSPI_IRQSTATUS_TX2_EMPTY_MASK | \
878 CSL_MCSPI_IRQSTATUS_RX1_FULL_MASK | \
879 CSL_MCSPI_IRQSTATUS_TX1_UNDERFLOW_MASK | \
880 CSL_MCSPI_IRQSTATUS_TX1_EMPTY_MASK | \
881 CSL_MCSPI_IRQSTATUS_RX0_OVERFLOW_MASK | \
882 CSL_MCSPI_IRQSTATUS_RX0_FULL_MASK | \
883 CSL_MCSPI_IRQSTATUS_TX0_UNDERFLOW_MASK | \
884 CSL_MCSPI_IRQSTATUS_TX0_EMPTY_MASK)
912 uint32_t numWordsRxTx);
1043 uint32_t enableFlag);
1065 uint32_t enableFlag);
1102 uint32_t dataWidth);
1109 uint32_t bufWidthShift = 0U;
1115 else if(dataSize <= 16U)
1124 return bufWidthShift;
1160 CSL_REG32_WR(baseAddr +
MCSPI_CHTX(chNum), txData);
1165 uint32_t enableFlag)
1171 enableFlag >> CSL_MCSPI_CH0CONF_FFEW_SHIFT);
1176 uint32_t enableFlag)
1182 enableFlag >> CSL_MCSPI_CH0CONF_FFER_SHIFT);
1188 return (CSL_REG32_RD(baseAddr +
MCSPI_CHRX(chNum)));
1197 CSL_FINS(regVal, MCSPI_CH0CONF_WL, (dataWidth - 1U));
#define MCSPI_IS_D1
Data line 1 (SPIDAT[1]) selected for reception.
Definition: mcspi/v1/mcspi.h:225
#define MCSPI_CHRX(x)
Base address of McSPI_CHRX(x)
Definition: mcspi/v1/mcspi.h:863
void MCSPI_close(MCSPI_Handle handle)
Function to close a MCSPI peripheral specified by the MCSPI handle.
MCSPI instance attributes - used during init time.
Definition: mcspi/v1/mcspi.h:472
uint32_t transferTimeout
Definition: mcspi/v1/mcspi.h:416
static uint32_t MCSPI_readRxDataReg(uint32_t baseAddr, uint32_t chNum)
This API will return the data present in the MCSPI_RX register.
Definition: mcspi/v1/mcspi.h:1185
MCSPI channel object.
Definition: mcspi/v1/mcspi.h:510
uint32_t count
Definition: mcspi/v1/mcspi.h:365
static void MCSPI_writeTxDataReg(uint32_t baseAddr, uint32_t txData, uint32_t chNum)
This API will put the data on to the McSPI Channel transmit register.
Definition: mcspi/v1/mcspi.h:1155
static uint32_t MCSPI_readChCtrlReg(uint32_t baseAddr, uint32_t chNum)
This API returns Channel control register value.
Definition: mcspi/v1/mcspi.h:1133
void(* MCSPI_CallbackFxn)(MCSPI_Handle handle, MCSPI_Transaction *transaction)
The definition of a callback function used by the SPI driver when used in MCSPI_TRANSFER_MODE_CALLBAC...
Definition: mcspi/v1/mcspi.h:399
uint32_t operMode
Definition: mcspi/v1/mcspi.h:486
uint32_t status
Definition: mcspi/v1/mcspi.h:388
Data structure used with MCSPI_transfer()
Definition: mcspi/v1/mcspi.h:344
uint32_t initDelay
Definition: mcspi/v1/mcspi.h:498
uint32_t effTxFifoDepth
Definition: mcspi/v1/mcspi.h:552
static void MCSPI_enableRxFIFO(uint32_t baseAddr, uint32_t chNum, uint32_t enableFlag)
This API will enable/disable the Rx FIFOs of McSPI peripheral.
Definition: mcspi/v1/mcspi.h:1174
static uint32_t MCSPI_readChStatusReg(uint32_t baseAddr, uint32_t chNum)
This API will return the status of the McSPI channel currently in use.
Definition: mcspi/v1/mcspi.h:1127
MCSPI_ChConfig chCfg
Definition: mcspi/v1/mcspi.h:514
uint32_t intrMask
Definition: mcspi/v1/mcspi.h:556
static uint32_t MCSPI_readChConf(uint32_t baseAddr, uint32_t chNum)
This API returns Channel Config register value.
Definition: mcspi/v1/mcspi.h:1144
#define MCSPI_CS_POL_LOW
SPIEN (CS) is held low during the ACTIVE state.
Definition: mcspi/v1/mcspi.h:202
int32_t MCSPI_reConfigFifo(MCSPI_Handle handle, uint32_t chNum, uint32_t numWordsRxTx)
Function to re-configure Effective FIFO Words.
static uint32_t MCSPI_getBufWidthShift(uint32_t dataSize)
This API will return the buffer width in bytes based on dataSize.
Definition: mcspi/v1/mcspi.h:1107
uint32_t transferMode
Definition: mcspi/v1/mcspi.h:414
#define MCSPI_DPE_DISABLE
No transmission on Data Line.
Definition: mcspi/v1/mcspi.h:237
MCSPI driver object.
Definition: mcspi/v1/mcspi.h:564
uint32_t MCSPI_getBaseAddr(MCSPI_Handle handle)
Function to get base address of MCSPI instance of a particular handle.
#define MCSPI_SB_POL_LOW
Start-bit polarity is held to 0 during MCSPI transfer.
Definition: mcspi/v1/mcspi.h:261
uint32_t bitRate
Definition: mcspi/v1/mcspi.h:441
void MCSPI_deinit(void)
This function de-initializes the MCSPI module.
MCSPI_Handle handle
Definition: mcspi/v1/mcspi.h:568
#define MCSPI_MAX_NUM_CHANNELS
Max number of channels/Chip Select (CS) supported.
Definition: mcspi/v1/mcspi.h:105
MCSPI Parameters.
Definition: mcspi/v1/mcspi.h:413
#define SystemP_WAIT_FOREVER
Value to use when needing a timeout of infinity or wait forver until resource is available.
Definition: SystemP.h:83
uint32_t csDisable
Definition: mcspi/v1/mcspi.h:348
void * MCSPI_Handle
A handle that is returned from a MCSPI_open() call.
Definition: mcspi/v1/mcspi.h:74
uint32_t trMode
Definition: mcspi/v1/mcspi.h:445
MCSPI_Object * object
Definition: mcspi/v1/mcspi.h:609
uint32_t txFifoTrigLvl
Definition: mcspi/v1/mcspi.h:548
uint32_t inputClkFreq
Definition: mcspi/v1/mcspi.h:478
void MCSPI_init(void)
This function initializes the MCSPI module.
#define MCSPI_MS_MODE_MASTER
The module generates the clock and CS.
Definition: mcspi/v1/mcspi.h:166
#define MCSPI_TRANSFER_MODE_BLOCKING
MCSPI_transfer() blocks execution. This mode can only be used when called within a Task context
Definition: mcspi/v1/mcspi.h:142
uint32_t isOpen
Definition: mcspi/v1/mcspi.h:520
HwiP_Object hwiObj
Definition: mcspi/v1/mcspi.h:589
SemaphoreP_Object transferSemObj
Definition: mcspi/v1/mcspi.h:585
uint32_t baseAddr
Definition: mcspi/v1/mcspi.h:476
uint32_t rxFifoTrigLvl
Definition: mcspi/v1/mcspi.h:550
uint32_t curRxWords
Definition: mcspi/v1/mcspi.h:534
#define MCSPI_CHSTAT(x)
Base address of McSPI_CHSTAT(x)
Definition: mcspi/v1/mcspi.h:851
uint32_t csPolarity
Definition: mcspi/v1/mcspi.h:443
static void MCSPI_setDataWidth(uint32_t baseAddr, uint32_t chNum, uint32_t dataWidth)
This API will set the data width in the channel config register.
Definition: mcspi/v1/mcspi.h:1191
uint32_t startBitPolarity
Definition: mcspi/v1/mcspi.h:459
#define MCSPI_SLV_CS_SELECT_0
Definition: mcspi/v1/mcspi.h:246
static void MCSPI_writeChCtrlReg(uint32_t baseAddr, uint32_t chNum, uint32_t regVal)
This API sets Channel control register value.
Definition: mcspi/v1/mcspi.h:1138
uint32_t chMode
Definition: mcspi/v1/mcspi.h:494
int32_t MCSPI_transfer(MCSPI_Handle handle, MCSPI_Transaction *transaction)
Function to perform MCSPI transactions.
uint32_t intrNum
Definition: mcspi/v1/mcspi.h:484
int32_t MCSPI_transferCancel(MCSPI_Handle handle)
Function to cancel MCSPI transactions on channel of a SPI peripheral specified by the MCSPI handle.
uint32_t msMode
Definition: mcspi/v1/mcspi.h:420
const uint8_t * curTxBufPtr
Definition: mcspi/v1/mcspi.h:526
static void MCSPI_Transaction_init(MCSPI_Transaction *trans)
Function to initialize the MCSPI_Transaction struct to its defaults.
Definition: mcspi/v1/mcspi.h:797
uint32_t csDisable
Definition: mcspi/v1/mcspi.h:522
void * args
Definition: mcspi/v1/mcspi.h:386
uint32_t dataWidthBitMask
Definition: mcspi/v1/mcspi.h:546
uint32_t pinMode
Definition: mcspi/v1/mcspi.h:496
#define MCSPI_CHTX(x)
Base address of McSPI_CHTX(x)
Definition: mcspi/v1/mcspi.h:859
uint32_t startBitEnable
Definition: mcspi/v1/mcspi.h:456
#define MCSPI_TCS0_0_CLK
0.5 clock cycles delay
Definition: mcspi/v1/mcspi.h:273
void * txBuf
Definition: mcspi/v1/mcspi.h:368
void * rxBuf
Definition: mcspi/v1/mcspi.h:379
uint32_t effRxFifoDepth
Definition: mcspi/v1/mcspi.h:554
uint32_t dataSize
Definition: mcspi/v1/mcspi.h:354
static void MCSPI_ChConfig_init(MCSPI_ChConfig *chConfig)
Function to initialize the MCSPI_ChConfig struct to its defaults.
Definition: mcspi/v1/mcspi.h:777
uint32_t curTxWords
Definition: mcspi/v1/mcspi.h:530
uint32_t slvCsSelect
Definition: mcspi/v1/mcspi.h:453
int32_t MCSPI_chConfig(MCSPI_Handle handle, const MCSPI_ChConfig *chCfg)
Function to configure a MCSPI channel.
uint8_t intrPriority
Definition: mcspi/v1/mcspi.h:488
static void MCSPI_enableTxFIFO(uint32_t baseAddr, uint32_t chNum, uint32_t enableFlag)
This API will enable/disable the Tx FIFOs of McSPI peripheral.
Definition: mcspi/v1/mcspi.h:1163
uint8_t bufWidthShift
Definition: mcspi/v1/mcspi.h:540
MCSPI global configuration array.
Definition: mcspi/v1/mcspi.h:606
void * transferSem
Definition: mcspi/v1/mcspi.h:582
MCSPI_Transaction * currTransaction
Definition: mcspi/v1/mcspi.h:592
#define MCSPI_CHCONF(x)
Base address of McSPI_CHCONF(x)
Definition: mcspi/v1/mcspi.h:847
uint8_t * curRxBufPtr
Definition: mcspi/v1/mcspi.h:528
#define MCSPI_FF_POL0_PHA0
Definition: mcspi/v1/mcspi.h:185
Opaque Hwi object used with the Hwi APIs.
Definition: HwiP.h:91
MCSPI_OpenParams openPrms
Definition: mcspi/v1/mcspi.h:570
uint32_t defaultTxData
Definition: mcspi/v1/mcspi.h:465
static void MCSPI_OpenParams_init(MCSPI_OpenParams *openPrms)
Function to initialize the MCSPI_OpenParams struct to its defaults.
Definition: mcspi/v1/mcspi.h:766
uint32_t dpe1
Definition: mcspi/v1/mcspi.h:451
uint32_t gMcspiConfigNum
Externally defined driver configuration array size.
uint32_t csEnable
Definition: mcspi/v1/mcspi.h:524
Opaque semaphore object used with the semaphore APIs.
Definition: SemaphoreP.h:59
#define MCSPI_TRANSFER_COMPLETED
Definition: mcspi/v1/mcspi.h:115
uint32_t channel
Definition: mcspi/v1/mcspi.h:345
#define MCSPI_TR_MODE_TX_RX
Definition: mcspi/v1/mcspi.h:211
uint32_t inputSelect
Definition: mcspi/v1/mcspi.h:447
uint32_t isOpen
Definition: mcspi/v1/mcspi.h:580
uint32_t dpe0
Definition: mcspi/v1/mcspi.h:449
static void MCSPI_writeChConfReg(uint32_t baseAddr, uint32_t chNum, uint32_t regVal)
This API sets Channel Config register value.
Definition: mcspi/v1/mcspi.h:1149
MCSPI_Handle MCSPI_open(uint32_t index, const MCSPI_OpenParams *openPrms)
This function opens a given MCSPI peripheral.
MCSPI configuration parameters for the channel.
Definition: mcspi/v1/mcspi.h:436
MCSPI_Config gMcspiConfig[]
Externally defined driver configuration array.
MCSPI_CallbackFxn transferCallbackFxn
Definition: mcspi/v1/mcspi.h:418
uint32_t baseAddr
Definition: mcspi/v1/mcspi.h:572
const MCSPI_Attrs * attrs
Definition: mcspi/v1/mcspi.h:607
#define MCSPI_CHCTRL(x)
Base address of McSPI_CHCTRL(x)
Definition: mcspi/v1/mcspi.h:855
#define MCSPI_CHANNEL_0
Definition: mcspi/v1/mcspi.h:85
uint32_t frameFormat
Definition: mcspi/v1/mcspi.h:439
uint32_t csIdleTime
Definition: mcspi/v1/mcspi.h:462
#define MCSPI_DPE_ENABLE
Data line selected for transmission.
Definition: mcspi/v1/mcspi.h:235
uint32_t chNum
Definition: mcspi/v1/mcspi.h:437
void * hwiHandle
Definition: mcspi/v1/mcspi.h:587