Introduction

For more details and example usage, see SOC

Data Structures
struct	SOC_RcmClkSrcInfo

struct	SOC_RcmXTALInfo

struct	SOC_RcmADPLLJConfig_t

struct	SOC_RcmPllHsDivOutConfig

Functions
void	SOC_rcmCoreApllConfig (SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg)
	Configure CORE PLL. More...

void	SOC_rcmCoreApllRelockPreRequisite (void)
	Pre-requisite sequence to Re-configure CORE PLL. More...

void	SOC_rcmCoreApllHSDivConfig (SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg)
	Configure CORE PLL HSDIVIDERS. More...

void	SOC_rcmPerApllConfig (SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg)
	Configure PER PLL. More...

void	SOC_rcmsetR5SysClock (uint32_t cr5FreqHz, uint32_t sysClkFreqHz)
	Set R5F and Sysclk frequency (Root clock configuration) More...

void	SOC_rcmsetTraceClock (uint32_t traceFreqHz)
	Set Trace clock frequency. More...

void	SOC_rcmsetClkoutClock (uint32_t clkout0FreqHz, uint32_t clkout1FreqHz)
	Set CLKOUT clock frequency. More...

int32_t	SOC_rcmSetPeripheralClock (SOC_RcmPeripheralId periphId, SOC_RcmPeripheralClockSource clkSource, uint32_t freqHz)
	Set module clock (IP clock configuration) More...

SOC_RcmResetCause	SOC_rcmGetResetCause (SOC_Rcmr5fssNum r5fssNum)
	Get R5FSS reset cause. More...

int32_t	SOC_rcmEnablePeripheralClock (SOC_RcmPeripheralId periphId, uint32_t enable)
	Enable/disable module clock (IP clock configuration) More...

int32_t	SOC_rcmSetR5Clock (uint32_t r5FreqHz, uint32_t sysClkFreqHz)
	Set R5 and SycClk frequency. More...

uint32_t	SOC_rcmGetR5Clock (void)
	Get R5 frequency. More...

void	SOC_rcmR5ConfigLockStep (uint32_t cpuId)
	Configure R5 in lock step mode. More...

void	SOC_rcmR5ConfigDualCore (uint32_t cpuId)
	Configure R5 in dual core mode. More...

void	SOC_rcmR5SS0TriggerReset (void)
	Trigger R5 core reset. More...

void	SOC_rcmCoreR5FUnhalt (uint32_t cpuId)
	Unhalt R5 cores. More...

void	SOC_rcmStartMemInitTCMA (uint32_t cpuId)
	Start memory initialization for R5 TCMA. More...

void	SOC_rcmWaitMemInitTCMA (uint32_t cpuId)
	Wait memory initialization to complete for R5 TCMA. More...

void	SOC_rcmStartMemInitTCMB (uint32_t cpuId)
	Start memory initialization for R5 TCMB. More...

void	SOC_rcmWaitMemInitTCMB (uint32_t cpuId)
	Wait memory initialization to complete for R5 TCMB. More...

void	SOC_rcmMemInitMailboxMemory (void)
	Wait memory initialization to complete for Mailbox memory. More...

void	SOC_rcmMemInitL2Memory (void)
	Wait memory initialization to complete for L2 Bank2 and Bank3 memory. More...

void	SOC_rcmR5SS0PowerOnReset (void)
	Reset R5SS0 Core. More...

void	SOC_rcmR5SS1TriggerReset (void)
	Trigger R5SS1 core reset. More...

void	SOC_rcmR5SS1PowerOnReset (void)
	Reset R5SS1 Core. More...

Enumerations
enum	SOC_RcmResetCause { SOC_RcmResetCause_POWER_ON_RESET = 0x0U, SOC_RcmResetCause_WARM_RESET = 0x1U, SOC_RcmResetCause_STC_RESET = 0x2U, SOC_RcmResetCause_MMR_CPU0_VIM0_RESET = 0x3U, SOC_RcmResetCause_MMR_CPU1_VIM1_RESET = 0x4U, SOC_RcmResetCause_MMR_CPU0_RESET = 0x5U, SOC_RcmResetCause_MMR_CPU1_RESET = 0x6U, SOC_RcmResetCause_DBG_CPU0_RESET = 0x7U, SOC_RcmResetCause_DBG_CPU1_RESET = 0x8U, SOC_RcmResetCause_FSM_TRIGGER_RESET = 0x9U, SOC_RcmResetCause_RST_CAUSE_UNKNOWN = 0xAU }
	Reset Causes. More...

enum	SOC_Rcmr5fssNum { r5fss0 = 0x0U, r5fss1 = 0x1U }
	R5F subsystems. More...

enum	SOC_RcmPeripheralId { SOC_RcmPeripheralId_MCAN0, SOC_RcmPeripheralId_MCAN1, SOC_RcmPeripheralId_MCAN2, SOC_RcmPeripheralId_MCAN3, SOC_RcmPeripheralId_QSPI0, SOC_RcmPeripheralId_RTI0, SOC_RcmPeripheralId_RTI1, SOC_RcmPeripheralId_RTI2, SOC_RcmPeripheralId_RTI3, SOC_RcmPeripheralId_WDT0, SOC_RcmPeripheralId_WDT1, SOC_RcmPeripheralId_WDT2, SOC_RcmPeripheralId_WDT3, SOC_RcmPeripheralId_MCSPI0, SOC_RcmPeripheralId_MCSPI1, SOC_RcmPeripheralId_MCSPI2, SOC_RcmPeripheralId_MCSPI3, SOC_RcmPeripheralId_MCSPI4, SOC_RcmPeripheralId_MMC0, SOC_RcmPeripheralId_ICSSM0_UART0, SOC_RcmPeripheralId_CPTS, SOC_RcmPeripheralId_GPMC, SOC_RcmPeripheralId_CONTROLSS_PLL, SOC_RcmPeripheralId_I2C, SOC_RcmPeripheralId_LIN0_UART0, SOC_RcmPeripheralId_LIN1_UART1, SOC_RcmPeripheralId_LIN2_UART2, SOC_RcmPeripheralId_LIN3_UART3, SOC_RcmPeripheralId_LIN4_UART4, SOC_RcmPeripheralId_LIN5_UART5 }
	Peripheral Ids. More...

enum	SOC_RcmPeripheralClockSource { SOC_RcmPeripheralClockSource_XTALCLK, SOC_RcmPeripheralClockSource_SYS_CLK, SOC_RcmPeripheralClockSource_WUCPUCLK, SOC_RcmPeripheralClockSource_EXT_REFCLK, SOC_RcmPeripheralClockSource_RCCLK10M, SOC_RcmPeripheralClockSource_RCCLK32K, SOC_RcmPeripheralClockSource_CTPS_GENF0, SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT0, SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT1, SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT2, SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT0, SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT1 }
	Peripheral clock sources. More...

enum	SOC_RcmPllFoutFreqId { RCM_PLL_FOUT_FREQID_CLK_2000MHZ, RCM_PLL_FOUT_FREQID_CLK_1920MHZ }
	PLL frequency output IDs. More...

enum	SOC_RcmXtalFreqId { RCM_XTAL_FREQID_CLK_25MHZ }
	XTAL frequency IDs. More...

enum	SOC_RcmPllId { RCM_PLLID_CORE, RCM_PLLID_PER, RCM_PLLID_XTALCLK, RCM_PLLID_WUCPUCLK, RCM_PLLID_RCCLK32K, RCM_PLLID_RCCLK10M, RCM_PLLID_EXTREFCLK }

enum	SOC_RcmPllHSDIVOutId { RCM_PLLHSDIV_OUT_0, RCM_PLLHSDIV_OUT_1, RCM_PLLHSDIV_OUT_2, RCM_PLLHSDIV_OUT_NONE }
	HSDIVIDER IDs. More...

Macros
#define	SOC_RCM_FREQ_MHZ2HZ(x) ((x) * 1000 * 1000)

#define	SOC_RCM_FREQ_HZ2MHZ(x) ((x) / (1000 * 1000))

#define	RCM_PLL_HSDIV_OUTPUT_ENABLE_0 (1U << 0U)

#define	RCM_PLL_HSDIV_OUTPUT_ENABLE_1 (1U << 1U)

#define	RCM_PLL_HSDIV_OUTPUT_ENABLE_2 (1U << 2U)

#define	RCM_PLL_HSDIV_OUTPUT_ENABLE_3 (1U << 3U)

#define	RCM_PLL_HSDIV_OUTPUT_ENABLE_ALL

#define	RCM_PLL_HSDIV_OUTPUT_IDX0 (0)

#define	RCM_PLL_HSDIV_OUTPUT_IDX1 (1)

#define	RCM_PLL_HSDIV_OUTPUT_IDX2 (2)

#define	RCM_PLL_HSDIV_OUTPUT_IDX3 (3)

#define	RCM_PLL_HSDIV_OUTPUT_COUNT (RCM_PLL_HSDIV_OUTPUT_IDX3 + 1)

Macro Definition Documentation

◆ SOC_RCM_FREQ_MHZ2HZ

#define SOC_RCM_FREQ_MHZ2HZ ( x ) ((x) * 1000 * 1000)

◆ SOC_RCM_FREQ_HZ2MHZ

#define SOC_RCM_FREQ_HZ2MHZ ( x ) ((x) / (1000 * 1000))

◆ RCM_PLL_HSDIV_OUTPUT_ENABLE_0

#define RCM_PLL_HSDIV_OUTPUT_ENABLE_0 (1U << 0U)

◆ RCM_PLL_HSDIV_OUTPUT_ENABLE_1

#define RCM_PLL_HSDIV_OUTPUT_ENABLE_1 (1U << 1U)

◆ RCM_PLL_HSDIV_OUTPUT_ENABLE_2

#define RCM_PLL_HSDIV_OUTPUT_ENABLE_2 (1U << 2U)

◆ RCM_PLL_HSDIV_OUTPUT_ENABLE_3

#define RCM_PLL_HSDIV_OUTPUT_ENABLE_3 (1U << 3U)

◆ RCM_PLL_HSDIV_OUTPUT_ENABLE_ALL

#define RCM_PLL_HSDIV_OUTPUT_ENABLE_ALL

Value:

                                             (RCM_PLL_HSDIV_OUTPUT_ENABLE_0   | \
                                             RCM_PLL_HSDIV_OUTPUT_ENABLE_1   | \
                                             RCM_PLL_HSDIV_OUTPUT_ENABLE_2   | \
                                             RCM_PLL_HSDIV_OUTPUT_ENABLE_3)

◆ RCM_PLL_HSDIV_OUTPUT_IDX0

#define RCM_PLL_HSDIV_OUTPUT_IDX0 (0)

◆ RCM_PLL_HSDIV_OUTPUT_IDX1

#define RCM_PLL_HSDIV_OUTPUT_IDX1 (1)

◆ RCM_PLL_HSDIV_OUTPUT_IDX2

#define RCM_PLL_HSDIV_OUTPUT_IDX2 (2)

◆ RCM_PLL_HSDIV_OUTPUT_IDX3

#define RCM_PLL_HSDIV_OUTPUT_IDX3 (3)

◆ RCM_PLL_HSDIV_OUTPUT_COUNT

#define RCM_PLL_HSDIV_OUTPUT_COUNT (RCM_PLL_HSDIV_OUTPUT_IDX3 + 1)

Enumeration Type Documentation

◆ SOC_RcmResetCause

enum SOC_RcmResetCause

Reset Causes.

This enumeration captures all the possible Reset Causes

Enumerator
SOC_RcmResetCause_POWER_ON_RESET	Value specifying Power ON Reset.
SOC_RcmResetCause_WARM_RESET	Value specifying Warm Reset.
SOC_RcmResetCause_STC_RESET	Value specifying STC Reset.
SOC_RcmResetCause_MMR_CPU0_VIM0_RESET	Value specifying R5 Core A Subsytem Reset.
SOC_RcmResetCause_MMR_CPU1_VIM1_RESET	Value specifying R5 Core B Subsytem Reset.
SOC_RcmResetCause_MMR_CPU0_RESET	Value specifying R5 Core A (core only) Reset.
SOC_RcmResetCause_MMR_CPU1_RESET	Value specifying R5 Core B (core only) Reset.
SOC_RcmResetCause_DBG_CPU0_RESET	Value specifying R5 Core A Debug Reset.
SOC_RcmResetCause_DBG_CPU1_RESET	Value specifying R5 Core B Debug Reset.
SOC_RcmResetCause_FSM_TRIGGER_RESET	Value specifying R5 Reset due to FSM Trigger.
SOC_RcmResetCause_RST_CAUSE_UNKNOWN	Value specifying R5 Reset due to Unknown reason.

◆ SOC_Rcmr5fssNum

enum SOC_Rcmr5fssNum

R5F subsystems.

This enumeration lists the R5F subsystems

Enumerator
r5fss0	Value specifying Power ON Reset.
r5fss1	Value specifying Warm Reset.

◆ SOC_RcmPeripheralId

enum SOC_RcmPeripheralId

Peripheral Ids.

This enumeration captures all the Peripherals

Enumerator
SOC_RcmPeripheralId_MCAN0	Value specifying MCAN0.
SOC_RcmPeripheralId_MCAN1	Value specifying MCAN1.
SOC_RcmPeripheralId_MCAN2	Value specifying MCAN2.
SOC_RcmPeripheralId_MCAN3	Value specifying MCAN3.
SOC_RcmPeripheralId_QSPI0	Value specifying QSPI0.
SOC_RcmPeripheralId_RTI0	Value specifying RTI0.
SOC_RcmPeripheralId_RTI1	Value specifying RTI1.
SOC_RcmPeripheralId_RTI2	Value specifying RTI2.
SOC_RcmPeripheralId_RTI3	Value specifying RTI3.
SOC_RcmPeripheralId_WDT0	Value specifying WDT0.
SOC_RcmPeripheralId_WDT1	Value specifying WDT1.
SOC_RcmPeripheralId_WDT2	Value specifying WDT2.
SOC_RcmPeripheralId_WDT3	Value specifying WDT3.
SOC_RcmPeripheralId_MCSPI0	Value specifying MCSPI0.
SOC_RcmPeripheralId_MCSPI1	Value specifying MCSPI1.
SOC_RcmPeripheralId_MCSPI2	Value specifying MCSPI2.
SOC_RcmPeripheralId_MCSPI3	Value specifying MCSPI3.
SOC_RcmPeripheralId_MCSPI4	Value specifying MCSPI4.
SOC_RcmPeripheralId_MMC0	Value specifying MMC0.
SOC_RcmPeripheralId_ICSSM0_UART0	Value specifying ICSSM0_UART0.
SOC_RcmPeripheralId_CPTS	Value specifying CPTS.
SOC_RcmPeripheralId_GPMC	Value specifying GPMC.
SOC_RcmPeripheralId_CONTROLSS_PLL	Value specifying CONTROLSS_PLL.
SOC_RcmPeripheralId_I2C	Value specifying I2C.
SOC_RcmPeripheralId_LIN0_UART0	Value specifying LIN0_UART0.
SOC_RcmPeripheralId_LIN1_UART1	Value specifying LIN1_UART1.
SOC_RcmPeripheralId_LIN2_UART2	Value specifying LIN2_UART2.
SOC_RcmPeripheralId_LIN3_UART3	Value specifying LIN3_UART3.
SOC_RcmPeripheralId_LIN4_UART4	Value specifying LIN4_UART4.
SOC_RcmPeripheralId_LIN5_UART5	Value specifying LIN5_UART5.

◆ SOC_RcmPeripheralClockSource

enum SOC_RcmPeripheralClockSource

Peripheral clock sources.

This enumeration clock sources of all the modules

Enumerator
SOC_RcmPeripheralClockSource_XTALCLK	Value specifying Crystal Clock.
SOC_RcmPeripheralClockSource_SYS_CLK	Value specifying System Clock (200Mhz)
SOC_RcmPeripheralClockSource_WUCPUCLK	Value specifying wake up clock.
SOC_RcmPeripheralClockSource_EXT_REFCLK	Value specifying external reference clock.
SOC_RcmPeripheralClockSource_RCCLK10M	Value specifying RC clock (10MHz)
SOC_RcmPeripheralClockSource_RCCLK32K	Value specifying RC clock (32KHz)
SOC_RcmPeripheralClockSource_CTPS_GENF0	Value specifying CPTS GENF0 clock.
SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT0	Value specifying PLL Core Clock Out 0 (400 Mhz)
SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT1	Value specifying PLL Core Clock Out 1 (500 Mhz)
SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT2	Value specifying PLL Core Clock Out 2 (400 Mhz)
SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT0	Value specifying PLL Core Clock Out 0 (160 Mhz)
SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT1	Value specifying PLL Core Clock Out 1 (192 Mhz)

◆ SOC_RcmPllFoutFreqId

enum SOC_RcmPllFoutFreqId

PLL frequency output IDs.

This enumeration lists output frequencies supported by PLLs

Enumerator
RCM_PLL_FOUT_FREQID_CLK_2000MHZ	Value specifying PLL output frequency 2000MHz.
RCM_PLL_FOUT_FREQID_CLK_1920MHZ	Value specifying PLL output frequency 1920MHz.

◆ SOC_RcmXtalFreqId

enum SOC_RcmXtalFreqId

XTAL frequency IDs.

This enumeration lists XTAL frequency IDs

Enumerator
RCM_XTAL_FREQID_CLK_25MHZ	Value specifying XTAL frequency 25MHZ.

◆ SOC_RcmPllId

enum SOC_RcmPllId

Enumerator
RCM_PLLID_CORE
RCM_PLLID_PER
RCM_PLLID_XTALCLK
RCM_PLLID_WUCPUCLK
RCM_PLLID_RCCLK32K
RCM_PLLID_RCCLK10M
RCM_PLLID_EXTREFCLK

◆ SOC_RcmPllHSDIVOutId

enum SOC_RcmPllHSDIVOutId

HSDIVIDER IDs.

This enumeration HSDIVIDER IDs

Enumerator
RCM_PLLHSDIV_OUT_0	Value specifying HSDIVIDER 0.
RCM_PLLHSDIV_OUT_1	Value specifying HSDIVIDER 1.
RCM_PLLHSDIV_OUT_2	Value specifying HSDIVIDER 2.
RCM_PLLHSDIV_OUT_NONE	Value specifying invalid/no HSDIVIDER ID.

Function Documentation

◆ SOC_rcmCoreApllConfig()

void SOC_rcmCoreApllConfig	(	SOC_RcmPllFoutFreqId	outFreqId,
		SOC_RcmPllHsDivOutConfig *	hsDivCfg
	)

Configure CORE PLL.

Parameters

outFreqId	[in] PLL output frequency ID. Enumberation: SOC_RcmPllFoutFreqId
*hsDivCfg	[in] HSDIVIDER configuration

◆ SOC_rcmCoreApllRelockPreRequisite()

void SOC_rcmCoreApllRelockPreRequisite ( void )

Pre-requisite sequence to Re-configure CORE PLL.

◆ SOC_rcmCoreApllHSDivConfig()

void SOC_rcmCoreApllHSDivConfig	(	SOC_RcmPllFoutFreqId	outFreqId,
		SOC_RcmPllHsDivOutConfig *	hsDivCfg
	)

Configure CORE PLL HSDIVIDERS.

Parameters

outFreqId	[in] PLL output frequency ID. Enumberation: SOC_RcmPllFoutFreqId
*hsDivCfg	[in] HSDIVIDER configuration

◆ SOC_rcmPerApllConfig()

void SOC_rcmPerApllConfig	(	SOC_RcmPllFoutFreqId	outFreqId,
		SOC_RcmPllHsDivOutConfig *	hsDivCfg
	)

Configure PER PLL.

Parameters

outFreqId	[in] PLL output frequency ID. Enumberation: SOC_RcmPllFoutFreqId
*hsDivCfg	[in] HSDIVIDER configuration

◆ SOC_rcmsetR5SysClock()

void SOC_rcmsetR5SysClock	(	uint32_t	cr5FreqHz,
		uint32_t	sysClkFreqHz
	)

Set R5F and Sysclk frequency (Root clock configuration)

Parameters

cr5FreqHz	[in] R5F frequency
sysClkFreqHz	[in] SYSCLK frequency

◆ SOC_rcmsetTraceClock()

void SOC_rcmsetTraceClock ( uint32_t traceFreqHz )

Set Trace clock frequency.

Parameters

traceFreqHz [in] Trace frequency

◆ SOC_rcmsetClkoutClock()

void SOC_rcmsetClkoutClock	(	uint32_t	clkout0FreqHz,
		uint32_t	clkout1FreqHz
	)

Set CLKOUT clock frequency.

Parameters

clkout0FreqHz	[in] CLKOUT0 frequency
clkout1FreqHz	[in] CLKOUT1 frequency

◆ SOC_rcmSetPeripheralClock()

int32_t SOC_rcmSetPeripheralClock	(	SOC_RcmPeripheralId	periphId,
		SOC_RcmPeripheralClockSource	clkSource,
		uint32_t	freqHz
	)

Set module clock (IP clock configuration)

 This API programs the Clock Source Selection and Clock divider values
 for a specified peripheral Id.

Parameters

periphId	[in] Peripheral ID
clkSource	[in] Clock source
freqHz	[in] Frequency

Returns: SystemP_SUCCESS Module clock is set; SystemP_FAILURE Module clock could not be set

◆ SOC_rcmGetResetCause()

SOC_RcmResetCause SOC_rcmGetResetCause ( SOC_Rcmr5fssNum r5fssNum )

Get R5FSS reset cause.

 This API returns the reset cause for R5 core. It also clears the Reset
 cause.

Parameters

r5fssNum [in] R5FSS0 or R5FSS1

Returns: SOC_RcmResetCause reset cause

◆ SOC_rcmEnablePeripheralClock()

int32_t SOC_rcmEnablePeripheralClock	(	SOC_RcmPeripheralId	periphId,
		uint32_t	enable
	)

Enable/disable module clock (IP clock configuration)

 This API programs the IP clock gates
 for a specified peripheral Id.

Parameters

periphId	[in] Peripheral ID
enable	[in] ungate (1)/gate clock (0)

Returns: SystemP_SUCCESS Module clock is set; SystemP_FAILURE Module clock could not be set

◆ SOC_rcmSetR5Clock()

int32_t SOC_rcmSetR5Clock	(	uint32_t	r5FreqHz,
		uint32_t	sysClkFreqHz
	)

Set R5 and SycClk frequency.

Parameters

r5FreqHz	[in] R5 frequency, in Hz
sysClkFreqHz	[in] SysClk frequency, in Hz

Returns: SystemP_SUCCESS on success, else failure

◆ SOC_rcmGetR5Clock()

uint32_t SOC_rcmGetR5Clock ( void )

Get R5 frequency.

Returns: R5 frequency, in Hz

◆ SOC_rcmR5ConfigLockStep()

void SOC_rcmR5ConfigLockStep ( uint32_t cpuId )

Configure R5 in lock step mode.

◆ SOC_rcmR5ConfigDualCore()

void SOC_rcmR5ConfigDualCore ( uint32_t cpuId )

Configure R5 in dual core mode.

◆ SOC_rcmR5SS0TriggerReset()

void SOC_rcmR5SS0TriggerReset ( void )

Trigger R5 core reset.

◆ SOC_rcmCoreR5FUnhalt()

void SOC_rcmCoreR5FUnhalt ( uint32_t cpuId )

Unhalt R5 cores.

◆ SOC_rcmStartMemInitTCMA()

void SOC_rcmStartMemInitTCMA ( uint32_t cpuId )

Start memory initialization for R5 TCMA.

◆ SOC_rcmWaitMemInitTCMA()

void SOC_rcmWaitMemInitTCMA ( uint32_t cpuId )

Wait memory initialization to complete for R5 TCMA.

◆ SOC_rcmStartMemInitTCMB()

void SOC_rcmStartMemInitTCMB ( uint32_t cpuId )

Start memory initialization for R5 TCMB.

◆ SOC_rcmWaitMemInitTCMB()

void SOC_rcmWaitMemInitTCMB ( uint32_t cpuId )

Wait memory initialization to complete for R5 TCMB.

◆ SOC_rcmMemInitMailboxMemory()

void SOC_rcmMemInitMailboxMemory ( void )

Wait memory initialization to complete for Mailbox memory.

◆ SOC_rcmMemInitL2Memory()

void SOC_rcmMemInitL2Memory ( void )

Wait memory initialization to complete for L2 Bank2 and Bank3 memory.

◆ SOC_rcmR5SS0PowerOnReset()

void SOC_rcmR5SS0PowerOnReset ( void )

Reset R5SS0 Core.

◆ SOC_rcmR5SS1TriggerReset()

void SOC_rcmR5SS1TriggerReset ( void )

Trigger R5SS1 core reset.

◆ SOC_rcmR5SS1PowerOnReset()

void SOC_rcmR5SS1PowerOnReset ( void )

Reset R5SS1 Core.

Introduction

Data Structures

Functions

Enumerations

Macros

Macro Definition Documentation

◆ SOC_RCM_FREQ_MHZ2HZ

◆ SOC_RCM_FREQ_HZ2MHZ

◆ RCM_PLL_HSDIV_OUTPUT_ENABLE_0

◆ RCM_PLL_HSDIV_OUTPUT_ENABLE_1

◆ RCM_PLL_HSDIV_OUTPUT_ENABLE_2

◆ RCM_PLL_HSDIV_OUTPUT_ENABLE_3

◆ RCM_PLL_HSDIV_OUTPUT_ENABLE_ALL

◆ RCM_PLL_HSDIV_OUTPUT_IDX0

◆ RCM_PLL_HSDIV_OUTPUT_IDX1

◆ RCM_PLL_HSDIV_OUTPUT_IDX2

◆ RCM_PLL_HSDIV_OUTPUT_IDX3

◆ RCM_PLL_HSDIV_OUTPUT_COUNT

Enumeration Type Documentation

◆ SOC_RcmResetCause

◆ SOC_Rcmr5fssNum

◆ SOC_RcmPeripheralId

◆ SOC_RcmPeripheralClockSource

◆ SOC_RcmPllFoutFreqId

◆ SOC_RcmXtalFreqId

◆ SOC_RcmPllId

◆ SOC_RcmPllHSDIVOutId

Function Documentation

◆ SOC_rcmCoreApllConfig()

◆ SOC_rcmCoreApllRelockPreRequisite()

◆ SOC_rcmCoreApllHSDivConfig()

◆ SOC_rcmPerApllConfig()

◆ SOC_rcmsetR5SysClock()

◆ SOC_rcmsetTraceClock()

◆ SOC_rcmsetClkoutClock()

◆ SOC_rcmSetPeripheralClock()

◆ SOC_rcmGetResetCause()

◆ SOC_rcmEnablePeripheralClock()

◆ SOC_rcmSetR5Clock()

◆ SOC_rcmGetR5Clock()

◆ SOC_rcmR5ConfigLockStep()

◆ SOC_rcmR5ConfigDualCore()

◆ SOC_rcmR5SS0TriggerReset()

◆ SOC_rcmCoreR5FUnhalt()

◆ SOC_rcmStartMemInitTCMA()

◆ SOC_rcmWaitMemInitTCMA()

◆ SOC_rcmStartMemInitTCMB()

◆ SOC_rcmWaitMemInitTCMB()

◆ SOC_rcmMemInitMailboxMemory()

◆ SOC_rcmMemInitL2Memory()

◆ SOC_rcmR5SS0PowerOnReset()

◆ SOC_rcmR5SS1TriggerReset()

◆ SOC_rcmR5SS1PowerOnReset()